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Merge pull request #15650 from aabadie/pr/cpu/stm32_clk_merge_f0f1f3

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cpu/stm32: merge f0/f1/f3 clock configuration headers
This commit is contained in:
benpicco 2020-12-20 02:31:12 +01:00 committed by GitHub
commit 7d8f801b20
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11 changed files with 52 additions and 169 deletions
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2
boards/nucleo-f030r8/include/periph_conf.h
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@ -32,7 +32,7 @@
#endif
#include "periph_cpu.h"
#include "f0/cfg_clock_default.h"
#include "clk_conf.h"
#ifdef __cplusplus
extern "C" {

2
boards/nucleo-f031k6/include/periph_conf.h
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@ -21,7 +21,7 @@
#define PERIPH_CONF_H
#include "periph_cpu.h"
#include "f0/cfg_clock_default.h"
#include "clk_conf.h"
#include "cfg_timer_tim2.h"
#ifdef __cplusplus

2
boards/nucleo-f042k6/include/periph_conf.h
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@ -20,7 +20,7 @@
#define PERIPH_CONF_H
#include "periph_cpu.h"
#include "f0/cfg_clock_default.h"
#include "clk_conf.h"
#include "cfg_timer_tim2.h"
#ifdef __cplusplus

2
boards/nucleo-f070rb/include/periph_conf.h
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@ -32,7 +32,7 @@
#endif
#include "periph_cpu.h"
#include "f0/cfg_clock_default.h"
#include "clk_conf.h"
#include "cfg_i2c1_pb8_pb9.h"
#ifdef __cplusplus

2
boards/nucleo-f072rb/include/periph_conf.h
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@ -31,7 +31,7 @@
#endif
#include "periph_cpu.h"
#include "f0/cfg_clock_default.h"
#include "clk_conf.h"
#include "cfg_i2c1_pb8_pb9.h"
#ifdef __cplusplus

2
boards/nucleo-f091rc/include/periph_conf.h
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@ -30,7 +30,7 @@
#endif
#include "periph_cpu.h"
#include "f0/cfg_clock_default.h"
#include "clk_conf.h"
#include "cfg_i2c1_pb8_pb9.h"
#ifdef __cplusplus

2
boards/stm32f030f4-demo/include/periph_conf.h
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@ -28,7 +28,7 @@
#endif
#include "periph_cpu.h"
#include "f0/cfg_clock_default.h"
#include "clk_conf.h"
#ifdef __cplusplus
extern "C" {

2
boards/stm32f0discovery/include/periph_conf.h
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@ -25,7 +25,7 @@
#endif
#include "periph_cpu.h"
#include "f0/cfg_clock_default.h"
#include "clk_conf.h"
#ifdef __cplusplus
extern "C" {

7
cpu/stm32/include/clk/clk_conf.h
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@ -22,10 +22,9 @@
#include "kernel_defines.h"
#include "macros/units.h"
#if defined(CPU_FAM_STM32F0)
#include "f0/cfg_clock_default.h"
#elif defined(CPU_FAM_STM32F1) || defined(CPU_FAM_STM32F3)
#include "f1f3/cfg_clock_default.h"
#if defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F1) || \
defined(CPU_FAM_STM32F3)
#include "f0f1f3/cfg_clock_default.h"
#elif defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4) || \
defined(CPU_FAM_STM32F7)
#include "f2f4f7/cfg_clock_default.h"

146
cpu/stm32/include/clk/f0/cfg_clock_default.h
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@ -1,146 +0,0 @@
/*
* Copyright (C) 2020 Inria
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup cpu_stm32
* @{
*
* @file
* @brief Default clock configuration for STM32F0
*
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
* @author José Ignacio Alamos <jialamos@uc.cl>
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
*/
#ifndef CLK_F0_CFG_CLOCK_DEFAULT_H
#define CLK_F0_CFG_CLOCK_DEFAULT_H
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name Clock settings
* @{
*/
/* Select the desired system clock source between PLL, HSE or HSI */
#ifndef CONFIG_USE_CLOCK_PLL
#if IS_ACTIVE(CONFIG_USE_CLOCK_HSE) || IS_ACTIVE(CONFIG_USE_CLOCK_HSI)
#define CONFIG_USE_CLOCK_PLL 0
#else
#define CONFIG_USE_CLOCK_PLL 1 /* Use PLL by default */
#endif
#endif /* CONFIG_USE_CLOCK_PLL */
#ifndef CONFIG_USE_CLOCK_HSE
#define CONFIG_USE_CLOCK_HSE 0
#endif /* CONFIG_USE_CLOCK_HSE */
#ifndef CONFIG_USE_CLOCK_HSI
#define CONFIG_USE_CLOCK_HSI 0
#endif /* CONFIG_USE_CLOCK_HSI */
#if IS_ACTIVE(CONFIG_USE_CLOCK_PLL) && \
(IS_ACTIVE(CONFIG_USE_CLOCK_HSE) || IS_ACTIVE(CONFIG_USE_CLOCK_HSI))
#error "Cannot use PLL as clock source with other clock configurations"
#endif
#if IS_ACTIVE(CONFIG_USE_CLOCK_HSE) && \
(IS_ACTIVE(CONFIG_USE_CLOCK_PLL) || IS_ACTIVE(CONFIG_USE_CLOCK_HSI))
#error "Cannot use HSE as clock source with other clock configurations"
#endif
#if IS_ACTIVE(CONFIG_USE_CLOCK_HSI) && \
(IS_ACTIVE(CONFIG_USE_CLOCK_PLL) || IS_ACTIVE(CONFIG_USE_CLOCK_HSE))
#error "Cannot use HSI as clock source with other clock configurations"
#endif
#ifndef CONFIG_BOARD_HAS_HSE
#define CONFIG_BOARD_HAS_HSE 0
#endif
#ifndef CLOCK_HSE
#define CLOCK_HSE MHZ(8)
#endif
#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE < MHZ(4) || CLOCK_HSE > MHZ(32))
#error "HSE clock frequency must be between 4MHz and 32MHz"
#endif
#ifndef CONFIG_BOARD_HAS_LSE
#define CONFIG_BOARD_HAS_LSE 0
#endif
#define CLOCK_HSI MHZ(8)
/* The following parameters configure a 48MHz system clock with HSI (or default HSE) as input clock
On stm32f031x6 and stm32f042x6 lines, there's no HSE and PREDIV is hard-wired to 2,
so to reach 48MHz set PLL_PREDIV to 2 and PLL_MUL to 12 so core clock = (HSI8 / 2) * 12 = 48MHz */
#ifndef CONFIG_CLOCK_PLL_PREDIV
#if defined(CPU_LINE_STM32F031x6) || defined(CPU_LINE_STM32F042x6)
#define CONFIG_CLOCK_PLL_PREDIV (2)
#else
#define CONFIG_CLOCK_PLL_PREDIV (1)
#endif
#endif
#ifndef CONFIG_CLOCK_PLL_MUL
#if defined(CPU_LINE_STM32F031x6) || defined(CPU_LINE_STM32F042x6)
#define CONFIG_CLOCK_PLL_MUL (12)
#else
#define CONFIG_CLOCK_PLL_MUL (6)
#endif
#endif
#if IS_ACTIVE(CONFIG_USE_CLOCK_HSI)
#define CLOCK_CORECLOCK (CLOCK_HSI)
#elif IS_ACTIVE(CONFIG_USE_CLOCK_HSE)
#if !IS_ACTIVE(CONFIG_BOARD_HAS_HSE)
#error "The board doesn't provide an HSE oscillator"
#endif
#define CLOCK_CORECLOCK (CLOCK_HSE)
#elif IS_ACTIVE(CONFIG_USE_CLOCK_PLL)
#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE)
#define CLOCK_PLL_SRC (CLOCK_HSE)
#else /* CLOCK_HSI */
#define CLOCK_PLL_SRC (CLOCK_HSI)
#endif
/* PLL configuration: make sure your values are legit!
*
* compute by: CORECLOCK = ((PLL_IN / PLL_PREDIV) * PLL_MUL)
* with:
* PLL_IN: input clock is HSE if available or HSI otherwise
* PLL_PREDIV : pre-divider, allowed range: [1:16]
* PLL_MUL: multiplier, allowed range: [2:16]
* CORECLOCK -> 48MHz MAX!
*/
#define CLOCK_CORECLOCK ((CLOCK_PLL_SRC / CONFIG_CLOCK_PLL_PREDIV) * CONFIG_CLOCK_PLL_MUL)
#if CLOCK_CORECLOCK > MHZ(48)
#error "SYSCLK cannot exceed 48MHz"
#endif
#endif /* CONFIG_USE_CLOCK_PLL */
#define CLOCK_AHB CLOCK_CORECLOCK /* max: 48MHz */
#ifndef CONFIG_CLOCK_APB1_DIV
#define CONFIG_CLOCK_APB1_DIV (1)
#endif
#define CLOCK_APB1 (CLOCK_AHB / CONFIG_CLOCK_APB1_DIV) /* max: 48MHz */
/* APB2 and APB1 are the same bus but configuration registers still follows the
* split between APB1 and APB2. Since it's the same bus, APB2 clock is equal to APB1 clock.
*/
#define CLOCK_APB2 (CLOCK_APB1)
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* CLK_F0_CFG_CLOCK_DEFAULT_H */
/** @} */

52
cpu/stm32/include/clk/f1f3/cfg_clock_default.h → cpu/stm32/include/clk/f0f1f3/cfg_clock_default.h
View File

@ -13,7 +13,7 @@
* @{
*
* @file
* @brief Default clock configuration for STM32F1/F3
* @brief Default clock configuration for STM32F0/F1/F3
*
* @author Víctor Ariño <victor.arino@triagnosys.com>
* @author Sören Tempel <tempel@uni-bremen.de>
@ -23,8 +23,8 @@
*
*/
#ifndef CLK_F1F3_CFG_CLOCK_DEFAULT_H
#define CLK_F1F3_CFG_CLOCK_DEFAULT_H
#ifndef CLK_F0F1F3_CFG_CLOCK_DEFAULT_H
#define CLK_F0F1F3_CFG_CLOCK_DEFAULT_H
#ifdef __cplusplus
extern "C" {
@ -83,8 +83,12 @@ extern "C" {
#define CLOCK_HSI MHZ(8)
/* The following parameters configure a 72MHz system clock with HSE (8MHz or
16MHz) and HSI (8MHz) as input clock
/* The following parameters configure:
- on F0: a 48MHz system clock with HSI (or default HSE) as input clock
On stm32f031x6 and stm32f042x6 lines, there's no HSE and PREDIV is
hard-wired to 2, so to reach 48MHz set PLL_PREDIV to 2 and PLL_MUL to 12 so
system clock = (HSI8 / 2) * 12 = 48MHz
- on F1/F3: a 72MHz system clock with HSE (8MHz or 16MHz) and HSI (8MHz) as input clock
On stm32f303x6, stm32f303x8, stm32f303xB, stm32f303xC, stm32f328x8 and
stm32f358xC lines, PREDIV is hard-wired to 2 (see RM0316 p.126 to p.128).
To reach the maximum possible system clock (64MHz) set PLL_PREDIV to 2 and
@ -94,19 +98,28 @@ extern "C" {
#if (IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(16))) || \
defined(CPU_LINE_STM32F303x6) || defined(CPU_LINE_STM32F303x8) || \
defined(CPU_LINE_STM32F303xB) || defined(CPU_LINE_STM32F303xC) || \
defined(CPU_LINE_STM32F328x8) || defined(CPU_LINE_STM32F358xC)
defined(CPU_LINE_STM32F328x8) || defined(CPU_LINE_STM32F358xC) || \
defined(CPU_LINE_STM32F031x6) || defined(CPU_LINE_STM32F042x6)
#define CONFIG_CLOCK_PLL_PREDIV (2)
#else
#define CONFIG_CLOCK_PLL_PREDIV (1)
#endif
#endif
#ifndef CONFIG_CLOCK_PLL_MUL
#ifdef CPU_FAM_STM32F0
#if defined(CPU_LINE_STM32F031x6) || defined(CPU_LINE_STM32F042x6)
#define CONFIG_CLOCK_PLL_MUL (12)
#else
#define CONFIG_CLOCK_PLL_MUL (6)
#endif
#else /* CPU_FAM_F1 || CPU_FAM_F3 */
#if defined(CPU_LINE_STM32F303x8)
#define CONFIG_CLOCK_PLL_MUL (16)
#else
#define CONFIG_CLOCK_PLL_MUL (9)
#endif
#endif
#endif /* CPU_FAM_STM32F0 */
#endif /* CONFIG_CLOCK_PLL_MUL */
#if IS_ACTIVE(CONFIG_USE_CLOCK_HSI)
#define CLOCK_CORECLOCK (CLOCK_HSI)
@ -130,29 +143,46 @@ extern "C" {
* PLL_IN: input clock is HSE if available or HSI otherwise
* PLL_PREDIV : pre-divider, allowed range: [1:16]
* PLL_MUL: multiplier, allowed range: [2:16]
* CORECLOCK -> 72MHz MAX!
* CORECLOCK -> 48MHz Max on F0, 72MHz MAX on F1/F3!
*/
#define CLOCK_CORECLOCK ((CLOCK_PLL_SRC / CONFIG_CLOCK_PLL_PREDIV) * CONFIG_CLOCK_PLL_MUL)
#ifdef CPU_FAM_STM32F0
#if CLOCK_CORECLOCK > MHZ(48)
#error "SYSCLK cannot exceed 48MHz"
#endif
#else
#if CLOCK_CORECLOCK > MHZ(72)
#error "SYSCLK cannot exceed 72MHz"
#endif
#endif
#endif /* CONFIG_USE_CLOCK_PLL */
#define CLOCK_AHB CLOCK_CORECLOCK /* HCLK, max: 72MHz */
#define CLOCK_AHB CLOCK_CORECLOCK /* HCLK, max: 48MHz (F0), 72MHz (F1/F3)*/
#ifndef CONFIG_CLOCK_APB1_DIV
#ifdef CPU_FAM_STM32F0
#define CONFIG_CLOCK_APB1_DIV (1)
#else
#define CONFIG_CLOCK_APB1_DIV (2)
#endif
#define CLOCK_APB1 (CLOCK_AHB / CONFIG_CLOCK_APB1_DIV) /* PCLK1, max: 36MHz */
#endif
#define CLOCK_APB1 (CLOCK_AHB / CONFIG_CLOCK_APB1_DIV) /* PCLK1, max: 48MHz (F0), 36MHz (F1/F3)*/
#ifdef CPU_FAM_STM32F0
/* APB2 and APB1 are the same bus but configuration registers still follows the
* split between APB1 and APB2. Since it's the same bus, APB2 clock is equal to APB1 clock.
*/
#define CLOCK_APB2 (CLOCK_APB1)
#else
#ifndef CONFIG_CLOCK_APB2_DIV
#define CONFIG_CLOCK_APB2_DIV (1)
#endif
#define CLOCK_APB2 (CLOCK_AHB / CONFIG_CLOCK_APB2_DIV) /* PCLK2, max: 72MHz */
#endif
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* CLK_F1F3_CFG_CLOCK_DEFAULT_H */
#endif /* CLK_F0F1F3_CFG_CLOCK_DEFAULT_H */
/** @} */