From 45c2b19f25bc5120b18b4dd18b08503f43355749 Mon Sep 17 00:00:00 2001 From: Alexandre Abadie Date: Wed, 16 Dec 2020 14:32:30 +0100 Subject: [PATCH 1/3] cpu/stm32: merge f0f1f3 clock configuration headers --- cpu/stm32/include/clk/clk_conf.h | 7 ++- .../clk/{f1f3 => f0f1f3}/cfg_clock_default.h | 52 +++++++++++++++---- 2 files changed, 44 insertions(+), 15 deletions(-) rename cpu/stm32/include/clk/{f1f3 => f0f1f3}/cfg_clock_default.h (74%) diff --git a/cpu/stm32/include/clk/clk_conf.h b/cpu/stm32/include/clk/clk_conf.h index 2714dee16a..fc183f50ec 100644 --- a/cpu/stm32/include/clk/clk_conf.h +++ b/cpu/stm32/include/clk/clk_conf.h @@ -22,10 +22,9 @@ #include "kernel_defines.h" #include "macros/units.h" -#if defined(CPU_FAM_STM32F0) -#include "f0/cfg_clock_default.h" -#elif defined(CPU_FAM_STM32F1) || defined(CPU_FAM_STM32F3) -#include "f1f3/cfg_clock_default.h" +#if defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F1) || \ + defined(CPU_FAM_STM32F3) +#include "f0f1f3/cfg_clock_default.h" #elif defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4) || \ defined(CPU_FAM_STM32F7) #include "f2f4f7/cfg_clock_default.h" diff --git a/cpu/stm32/include/clk/f1f3/cfg_clock_default.h b/cpu/stm32/include/clk/f0f1f3/cfg_clock_default.h similarity index 74% rename from cpu/stm32/include/clk/f1f3/cfg_clock_default.h rename to cpu/stm32/include/clk/f0f1f3/cfg_clock_default.h index a531ed9a76..89187621cd 100644 --- a/cpu/stm32/include/clk/f1f3/cfg_clock_default.h +++ b/cpu/stm32/include/clk/f0f1f3/cfg_clock_default.h @@ -13,7 +13,7 @@ * @{ * * @file - * @brief Default clock configuration for STM32F1/F3 + * @brief Default clock configuration for STM32F0/F1/F3 * * @author Víctor Ariño * @author Sören Tempel @@ -23,8 +23,8 @@ * */ -#ifndef CLK_F1F3_CFG_CLOCK_DEFAULT_H -#define CLK_F1F3_CFG_CLOCK_DEFAULT_H +#ifndef CLK_F0F1F3_CFG_CLOCK_DEFAULT_H +#define CLK_F0F1F3_CFG_CLOCK_DEFAULT_H #ifdef __cplusplus extern "C" { @@ -83,8 +83,12 @@ extern "C" { #define CLOCK_HSI MHZ(8) -/* The following parameters configure a 72MHz system clock with HSE (8MHz or - 16MHz) and HSI (8MHz) as input clock +/* The following parameters configure: + - on F0: a 48MHz system clock with HSI (or default HSE) as input clock + On stm32f031x6 and stm32f042x6 lines, there's no HSE and PREDIV is + hard-wired to 2, so to reach 48MHz set PLL_PREDIV to 2 and PLL_MUL to 12 so + system clock = (HSI8 / 2) * 12 = 48MHz + - on F1/F3: a 72MHz system clock with HSE (8MHz or 16MHz) and HSI (8MHz) as input clock On stm32f303x6, stm32f303x8, stm32f303xB, stm32f303xC, stm32f328x8 and stm32f358xC lines, PREDIV is hard-wired to 2 (see RM0316 p.126 to p.128). To reach the maximum possible system clock (64MHz) set PLL_PREDIV to 2 and @@ -94,19 +98,28 @@ extern "C" { #if (IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(16))) || \ defined(CPU_LINE_STM32F303x6) || defined(CPU_LINE_STM32F303x8) || \ defined(CPU_LINE_STM32F303xB) || defined(CPU_LINE_STM32F303xC) || \ - defined(CPU_LINE_STM32F328x8) || defined(CPU_LINE_STM32F358xC) + defined(CPU_LINE_STM32F328x8) || defined(CPU_LINE_STM32F358xC) || \ + defined(CPU_LINE_STM32F031x6) || defined(CPU_LINE_STM32F042x6) #define CONFIG_CLOCK_PLL_PREDIV (2) #else #define CONFIG_CLOCK_PLL_PREDIV (1) #endif #endif #ifndef CONFIG_CLOCK_PLL_MUL +#ifdef CPU_FAM_STM32F0 +#if defined(CPU_LINE_STM32F031x6) || defined(CPU_LINE_STM32F042x6) +#define CONFIG_CLOCK_PLL_MUL (12) +#else +#define CONFIG_CLOCK_PLL_MUL (6) +#endif +#else /* CPU_FAM_F1 || CPU_FAM_F3 */ #if defined(CPU_LINE_STM32F303x8) #define CONFIG_CLOCK_PLL_MUL (16) #else #define CONFIG_CLOCK_PLL_MUL (9) #endif -#endif +#endif /* CPU_FAM_STM32F0 */ +#endif /* CONFIG_CLOCK_PLL_MUL */ #if IS_ACTIVE(CONFIG_USE_CLOCK_HSI) #define CLOCK_CORECLOCK (CLOCK_HSI) @@ -130,29 +143,46 @@ extern "C" { * PLL_IN: input clock is HSE if available or HSI otherwise * PLL_PREDIV : pre-divider, allowed range: [1:16] * PLL_MUL: multiplier, allowed range: [2:16] - * CORECLOCK -> 72MHz MAX! + * CORECLOCK -> 48MHz Max on F0, 72MHz MAX on F1/F3! */ #define CLOCK_CORECLOCK ((CLOCK_PLL_SRC / CONFIG_CLOCK_PLL_PREDIV) * CONFIG_CLOCK_PLL_MUL) +#ifdef CPU_FAM_STM32F0 +#if CLOCK_CORECLOCK > MHZ(48) +#error "SYSCLK cannot exceed 48MHz" +#endif +#else #if CLOCK_CORECLOCK > MHZ(72) #error "SYSCLK cannot exceed 72MHz" #endif +#endif #endif /* CONFIG_USE_CLOCK_PLL */ -#define CLOCK_AHB CLOCK_CORECLOCK /* HCLK, max: 72MHz */ +#define CLOCK_AHB CLOCK_CORECLOCK /* HCLK, max: 48MHz (F0), 72MHz (F1/F3)*/ #ifndef CONFIG_CLOCK_APB1_DIV +#ifdef CPU_FAM_STM32F0 +#define CONFIG_CLOCK_APB1_DIV (1) +#else #define CONFIG_CLOCK_APB1_DIV (2) #endif -#define CLOCK_APB1 (CLOCK_AHB / CONFIG_CLOCK_APB1_DIV) /* PCLK1, max: 36MHz */ +#endif +#define CLOCK_APB1 (CLOCK_AHB / CONFIG_CLOCK_APB1_DIV) /* PCLK1, max: 48MHz (F0), 36MHz (F1/F3)*/ +#ifdef CPU_FAM_STM32F0 +/* APB2 and APB1 are the same bus but configuration registers still follows the + * split between APB1 and APB2. Since it's the same bus, APB2 clock is equal to APB1 clock. + */ +#define CLOCK_APB2 (CLOCK_APB1) +#else #ifndef CONFIG_CLOCK_APB2_DIV #define CONFIG_CLOCK_APB2_DIV (1) #endif #define CLOCK_APB2 (CLOCK_AHB / CONFIG_CLOCK_APB2_DIV) /* PCLK2, max: 72MHz */ +#endif /** @} */ #ifdef __cplusplus } #endif -#endif /* CLK_F1F3_CFG_CLOCK_DEFAULT_H */ +#endif /* CLK_F0F1F3_CFG_CLOCK_DEFAULT_H */ /** @} */ From 048e8446ef9c334cdc7c0b603b2625eb5369cf61 Mon Sep 17 00:00:00 2001 From: Alexandre Abadie Date: Wed, 16 Dec 2020 14:33:05 +0100 Subject: [PATCH 2/3] cpu/stm32f0: remove old clock configuration header --- cpu/stm32/include/clk/f0/cfg_clock_default.h | 146 ------------------- 1 file changed, 146 deletions(-) delete mode 100644 cpu/stm32/include/clk/f0/cfg_clock_default.h diff --git a/cpu/stm32/include/clk/f0/cfg_clock_default.h b/cpu/stm32/include/clk/f0/cfg_clock_default.h deleted file mode 100644 index d380e973e6..0000000000 --- a/cpu/stm32/include/clk/f0/cfg_clock_default.h +++ /dev/null @@ -1,146 +0,0 @@ -/* - * Copyright (C) 2020 Inria - * - * This file is subject to the terms and conditions of the GNU Lesser - * General Public License v2.1. See the file LICENSE in the top level - * directory for more details. - */ - -/** - * @ingroup cpu_stm32 - * @{ - * - * @file - * @brief Default clock configuration for STM32F0 - * - * @author Hauke Petersen - * @author José Ignacio Alamos - * @author Alexandre Abadie - */ - -#ifndef CLK_F0_CFG_CLOCK_DEFAULT_H -#define CLK_F0_CFG_CLOCK_DEFAULT_H - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @name Clock settings - * @{ - */ -/* Select the desired system clock source between PLL, HSE or HSI */ -#ifndef CONFIG_USE_CLOCK_PLL -#if IS_ACTIVE(CONFIG_USE_CLOCK_HSE) || IS_ACTIVE(CONFIG_USE_CLOCK_HSI) -#define CONFIG_USE_CLOCK_PLL 0 -#else -#define CONFIG_USE_CLOCK_PLL 1 /* Use PLL by default */ -#endif -#endif /* CONFIG_USE_CLOCK_PLL */ - -#ifndef CONFIG_USE_CLOCK_HSE -#define CONFIG_USE_CLOCK_HSE 0 -#endif /* CONFIG_USE_CLOCK_HSE */ - -#ifndef CONFIG_USE_CLOCK_HSI -#define CONFIG_USE_CLOCK_HSI 0 -#endif /* CONFIG_USE_CLOCK_HSI */ - -#if IS_ACTIVE(CONFIG_USE_CLOCK_PLL) && \ - (IS_ACTIVE(CONFIG_USE_CLOCK_HSE) || IS_ACTIVE(CONFIG_USE_CLOCK_HSI)) -#error "Cannot use PLL as clock source with other clock configurations" -#endif - -#if IS_ACTIVE(CONFIG_USE_CLOCK_HSE) && \ - (IS_ACTIVE(CONFIG_USE_CLOCK_PLL) || IS_ACTIVE(CONFIG_USE_CLOCK_HSI)) -#error "Cannot use HSE as clock source with other clock configurations" -#endif - -#if IS_ACTIVE(CONFIG_USE_CLOCK_HSI) && \ - (IS_ACTIVE(CONFIG_USE_CLOCK_PLL) || IS_ACTIVE(CONFIG_USE_CLOCK_HSE)) -#error "Cannot use HSI as clock source with other clock configurations" -#endif - -#ifndef CONFIG_BOARD_HAS_HSE -#define CONFIG_BOARD_HAS_HSE 0 -#endif - -#ifndef CLOCK_HSE -#define CLOCK_HSE MHZ(8) -#endif -#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE < MHZ(4) || CLOCK_HSE > MHZ(32)) -#error "HSE clock frequency must be between 4MHz and 32MHz" -#endif - -#ifndef CONFIG_BOARD_HAS_LSE -#define CONFIG_BOARD_HAS_LSE 0 -#endif - -#define CLOCK_HSI MHZ(8) - -/* The following parameters configure a 48MHz system clock with HSI (or default HSE) as input clock -On stm32f031x6 and stm32f042x6 lines, there's no HSE and PREDIV is hard-wired to 2, -so to reach 48MHz set PLL_PREDIV to 2 and PLL_MUL to 12 so core clock = (HSI8 / 2) * 12 = 48MHz */ -#ifndef CONFIG_CLOCK_PLL_PREDIV -#if defined(CPU_LINE_STM32F031x6) || defined(CPU_LINE_STM32F042x6) -#define CONFIG_CLOCK_PLL_PREDIV (2) -#else -#define CONFIG_CLOCK_PLL_PREDIV (1) -#endif -#endif -#ifndef CONFIG_CLOCK_PLL_MUL -#if defined(CPU_LINE_STM32F031x6) || defined(CPU_LINE_STM32F042x6) -#define CONFIG_CLOCK_PLL_MUL (12) -#else -#define CONFIG_CLOCK_PLL_MUL (6) -#endif -#endif - -#if IS_ACTIVE(CONFIG_USE_CLOCK_HSI) -#define CLOCK_CORECLOCK (CLOCK_HSI) - -#elif IS_ACTIVE(CONFIG_USE_CLOCK_HSE) -#if !IS_ACTIVE(CONFIG_BOARD_HAS_HSE) -#error "The board doesn't provide an HSE oscillator" -#endif -#define CLOCK_CORECLOCK (CLOCK_HSE) - -#elif IS_ACTIVE(CONFIG_USE_CLOCK_PLL) -#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) -#define CLOCK_PLL_SRC (CLOCK_HSE) -#else /* CLOCK_HSI */ -#define CLOCK_PLL_SRC (CLOCK_HSI) -#endif -/* PLL configuration: make sure your values are legit! - * - * compute by: CORECLOCK = ((PLL_IN / PLL_PREDIV) * PLL_MUL) - * with: - * PLL_IN: input clock is HSE if available or HSI otherwise - * PLL_PREDIV : pre-divider, allowed range: [1:16] - * PLL_MUL: multiplier, allowed range: [2:16] - * CORECLOCK -> 48MHz MAX! - */ -#define CLOCK_CORECLOCK ((CLOCK_PLL_SRC / CONFIG_CLOCK_PLL_PREDIV) * CONFIG_CLOCK_PLL_MUL) -#if CLOCK_CORECLOCK > MHZ(48) -#error "SYSCLK cannot exceed 48MHz" -#endif -#endif /* CONFIG_USE_CLOCK_PLL */ - -#define CLOCK_AHB CLOCK_CORECLOCK /* max: 48MHz */ - -#ifndef CONFIG_CLOCK_APB1_DIV -#define CONFIG_CLOCK_APB1_DIV (1) -#endif -#define CLOCK_APB1 (CLOCK_AHB / CONFIG_CLOCK_APB1_DIV) /* max: 48MHz */ -/* APB2 and APB1 are the same bus but configuration registers still follows the - * split between APB1 and APB2. Since it's the same bus, APB2 clock is equal to APB1 clock. - */ -#define CLOCK_APB2 (CLOCK_APB1) -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif /* CLK_F0_CFG_CLOCK_DEFAULT_H */ -/** @} */ From 2d97581d062d18b046068ee6926d458ab5bd7890 Mon Sep 17 00:00:00 2001 From: Alexandre Abadie Date: Wed, 16 Dec 2020 14:43:18 +0100 Subject: [PATCH 3/3] boards/stm32f0: use clk_conf.h --- boards/nucleo-f030r8/include/periph_conf.h | 2 +- boards/nucleo-f031k6/include/periph_conf.h | 2 +- boards/nucleo-f042k6/include/periph_conf.h | 2 +- boards/nucleo-f070rb/include/periph_conf.h | 2 +- boards/nucleo-f072rb/include/periph_conf.h | 2 +- boards/nucleo-f091rc/include/periph_conf.h | 2 +- boards/stm32f030f4-demo/include/periph_conf.h | 2 +- boards/stm32f0discovery/include/periph_conf.h | 2 +- 8 files changed, 8 insertions(+), 8 deletions(-) diff --git a/boards/nucleo-f030r8/include/periph_conf.h b/boards/nucleo-f030r8/include/periph_conf.h index c3acb24fb2..e2ec7f1b55 100644 --- a/boards/nucleo-f030r8/include/periph_conf.h +++ b/boards/nucleo-f030r8/include/periph_conf.h @@ -32,7 +32,7 @@ #endif #include "periph_cpu.h" -#include "f0/cfg_clock_default.h" +#include "clk_conf.h" #ifdef __cplusplus extern "C" { diff --git a/boards/nucleo-f031k6/include/periph_conf.h b/boards/nucleo-f031k6/include/periph_conf.h index a51f9814b2..1bc732e4d4 100644 --- a/boards/nucleo-f031k6/include/periph_conf.h +++ b/boards/nucleo-f031k6/include/periph_conf.h @@ -21,7 +21,7 @@ #define PERIPH_CONF_H #include "periph_cpu.h" -#include "f0/cfg_clock_default.h" +#include "clk_conf.h" #include "cfg_timer_tim2.h" #ifdef __cplusplus diff --git a/boards/nucleo-f042k6/include/periph_conf.h b/boards/nucleo-f042k6/include/periph_conf.h index f70473b546..5d2c69a0ec 100644 --- a/boards/nucleo-f042k6/include/periph_conf.h +++ b/boards/nucleo-f042k6/include/periph_conf.h @@ -20,7 +20,7 @@ #define PERIPH_CONF_H #include "periph_cpu.h" -#include "f0/cfg_clock_default.h" +#include "clk_conf.h" #include "cfg_timer_tim2.h" #ifdef __cplusplus diff --git a/boards/nucleo-f070rb/include/periph_conf.h b/boards/nucleo-f070rb/include/periph_conf.h index deecb2c539..abd546e737 100644 --- a/boards/nucleo-f070rb/include/periph_conf.h +++ b/boards/nucleo-f070rb/include/periph_conf.h @@ -32,7 +32,7 @@ #endif #include "periph_cpu.h" -#include "f0/cfg_clock_default.h" +#include "clk_conf.h" #include "cfg_i2c1_pb8_pb9.h" #ifdef __cplusplus diff --git a/boards/nucleo-f072rb/include/periph_conf.h b/boards/nucleo-f072rb/include/periph_conf.h index b128a9f180..d4493d4f81 100644 --- a/boards/nucleo-f072rb/include/periph_conf.h +++ b/boards/nucleo-f072rb/include/periph_conf.h @@ -31,7 +31,7 @@ #endif #include "periph_cpu.h" -#include "f0/cfg_clock_default.h" +#include "clk_conf.h" #include "cfg_i2c1_pb8_pb9.h" #ifdef __cplusplus diff --git a/boards/nucleo-f091rc/include/periph_conf.h b/boards/nucleo-f091rc/include/periph_conf.h index 96f6681a77..47a4abeccb 100644 --- a/boards/nucleo-f091rc/include/periph_conf.h +++ b/boards/nucleo-f091rc/include/periph_conf.h @@ -30,7 +30,7 @@ #endif #include "periph_cpu.h" -#include "f0/cfg_clock_default.h" +#include "clk_conf.h" #include "cfg_i2c1_pb8_pb9.h" #ifdef __cplusplus diff --git a/boards/stm32f030f4-demo/include/periph_conf.h b/boards/stm32f030f4-demo/include/periph_conf.h index a7e80d6586..5ec1c429aa 100644 --- a/boards/stm32f030f4-demo/include/periph_conf.h +++ b/boards/stm32f030f4-demo/include/periph_conf.h @@ -28,7 +28,7 @@ #endif #include "periph_cpu.h" -#include "f0/cfg_clock_default.h" +#include "clk_conf.h" #ifdef __cplusplus extern "C" { diff --git a/boards/stm32f0discovery/include/periph_conf.h b/boards/stm32f0discovery/include/periph_conf.h index 520b672e82..5560dc6bcf 100644 --- a/boards/stm32f0discovery/include/periph_conf.h +++ b/boards/stm32f0discovery/include/periph_conf.h @@ -25,7 +25,7 @@ #endif #include "periph_cpu.h" -#include "f0/cfg_clock_default.h" +#include "clk_conf.h" #ifdef __cplusplus extern "C" {