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cpu/qn908x: Implement ADC support
The ADC in the QN908x cpu offers multiple options for ADC conversion using up to 8 external pins, one external reference pin and some internal signals like a 1.2V reference, Vss, Vcc and an internal temperature monitor. This patch implements support for sampling ADC values from the ADC lines defined in the board configuration. Some configurations are really always present and don't require a board configuration, like the Vcc or internal temperature monitor but to coexist with other board ADC line options they are only set as part of the board configuration.
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@ -30,6 +30,83 @@ The GPIO driver uses the @ref GPIO_PIN(port, pin) macro to declare pins.
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No configuration is necessary.
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@defgroup cpu_qn908x_adc NXP QN908x ADC - Analog to Digital converter
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@ingroup cpu_qn908x
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@brief NXP QN908x ADC driver
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This ADC is a differential sigma-delta ADC. There are 9 external signals
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named ADC0 to ADC7 and ADC_VREFI that can be connected to specific external GPIO
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pins. There are several combinations of measurements possible with the ADC
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module using these external signals as well as some internal signals, but not
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every combination is a possible input pair to the ADC.
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The ADC block runs at either 4 MHz or 32 KHz from the high speed or low speed
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clock sources respective. An additional divisor is available to select some
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intermediate clock values. However, this is not the sample rate, since a single
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sample from @ref adc_sample() requires multiple internal samples which are then
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filtered and decimated by the hardware, giving about 128 slower sample rate than
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the selected clock.
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Each board-defined ADC line is configured with a single integer value which is
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the logic or of the following values:
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- The differential pair of signals among the options in @ref
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qn908x_adc_channel_t,
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- For those channels that use the "Vinn" signal, a value selecting
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the Vinn signal in @ref qn908x_adc_vinn_t,
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- The reference voltage "Vref" that the ADC will use for its full range
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selected with @ref qn908x_adc_vref_t,
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- The ADC input gain as selected by @ref qn908x_adc_gain_t, which will
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multiply the differential input by a factor between 0.5 and 2, and
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- An optional gain flag @ref ADC_VREF_GAIN_X15.
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- An optional PGA enabled flag @ref ADC_PGA_ENABLE.
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The hardware resolution of the ADC data is always 23-bits signed, but smaller
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resolutions can be requested which will result in a smaller output value.
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An internal temperature sensor is available and connected to the ADC when
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selecting @ref ADC_CHANNEL_TEMP as the channel. In this case the returned
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value is still a number that represents the temperature dependent voltage level
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of the internal signal which then needs to be converted to a temperature by the
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application using calibration parameters. When using the internal temperature
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sensor, the 1.2V bandgap Vref is recommended with a Vinn of 1/2 Vref since the
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measured voltage is about 800 mV at room temperature.
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A special microvolts (ADC_RES_UV) resolution value for @ref adc_res_t is
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supported when using the internal 1.2 V bandgap as the reference voltage, in
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which case @ref adc_sample will return the measured value in microvolts as a
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signed integer, with a max range of +/- 1.8 V when using the x1.5 Vref
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multiplier.
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This special resolution mode takes into account the factory calibration of
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the internal reference voltage for more accurate readings. In any other case,
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the return value is a signed integer with as many bits as resolution
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requested not including the sign bit. Note that the return value may be a
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negative when measuring a negative differential voltage between the plus and
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minus side of the input.
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For example, if 8-bit resolution is requested for an ADC line where the channel
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connects the - side to Vinn configured as Vss, a maximum value of 255 can be
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returned when the + side level is as high as the Vref signal. However, a
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negative value of -255 is also possible if Vinn is configured as Vref and
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the + side level is as low as Vss.
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### ADC configuration example (for periph_conf.h) ###
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@code
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static const adc_conf_t adc_config[] = {
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/* Pin A11 to Vss, 1.8v Vref. */
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ADC_CHANNEL_ADC7_VINN | ADC_VREF_GAIN_X15,
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/* Pin A10 to A11, 1.2V Vref. */
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ADC_CHANNEL_ADC6_ADC7,
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/* Temperature (in V) over to 0.6 V, 1.2 V Vref. */
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ADC_CHANNEL_TEMP | ADC_VINN_VREF_2,
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/* Internal "battery monitor", Vcc/4 to Vss, 1.2V Vref. */
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ADC_CHANNEL_VCC4_VINN | ADC_VINN_AVSS,
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};
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#define ADC_NUMOF ARRAY_SIZE(adc_config)
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#define QN908X_ADC_CLOCK ADC_CLOCK_500K
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@endcode
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@defgroup cpu_qn908x_i2c NXP QN908x I2C
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@ingroup cpu_qn908x
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@ -141,6 +141,196 @@ enum {
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GPIO_PORTS_NUMOF /**< overall number of available ports */
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};
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/**
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* @name ADC CPU configuration
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* @{
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*/
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#if DOXYGEN
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/**
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* @brief Define if ADC external capacitor is connected to PA06 pin.
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*
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* The ADC block can use an external capacitor to better stabilize the reference
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* voltage. This capacitor is optional, but if it is present on the board this
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* macro should be defined by the board to make the ADC block use it.
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*/
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#define BOARD_HAS_ADC_PA06_CAP
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#endif
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#ifndef DOXYGEN
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/**
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* @name ADC resolution values
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* @{
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*/
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#define HAVE_ADC_RES_T
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typedef enum {
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ADC_RES_6BIT = 6u, /**< ADC resolution: 6 bit + sign */
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ADC_RES_8BIT = 8u, /**< ADC resolution: 8 bit + sign */
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ADC_RES_10BIT = 10u, /**< ADC resolution: 10 bit + sign */
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ADC_RES_12BIT = 12u, /**< ADC resolution: 12 bit + sign */
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ADC_RES_14BIT = 14u, /**< ADC resolution: 14 bit + sign */
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ADC_RES_16BIT = 16u, /**< ADC resolution: 16 bit + sign */
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/* Extra modes supported by this CPU. */
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ADC_RES_MAX = 22u, /**< Full ADC resolution: 22 bit + sign */
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ADC_RES_UV = 23u, /**< ADC resolution: signed int in uV */
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} adc_res_t;
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/** @} */
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#endif /* ifndef DOXYGEN */
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/**
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* @brief ADC oversample clock configuration
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*
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* The ADC runs at a given ADC clock frequency which is derived from either the
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* high frequency clock (16 or 32 MHz) or the low frequency one (32 or
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* 32.768 KHz). Running the ADC from the 32 KHz source can be useful in low
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* power applications where the high speed clock is not running.
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*
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* The ADC sample rate for adc_sample() will be about 128 times slower than the
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* ADC clock, due to the decimation filter, meaning that the maximum sampling
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* rate is 31.25 KHz.
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*/
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typedef enum {
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ADC_CLOCK_4M, /**< 4 MHz from the high speed clock. */
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ADC_CLOCK_2M, /**< 2 MHz from the high speed clock. */
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ADC_CLOCK_1M, /**< 1 MHz from the high speed clock. */
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ADC_CLOCK_500K, /**< 500 KHz from the high speed clock. */
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ADC_CLOCK_250K, /**< 250 KHz from the high speed clock. */
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ADC_CLOCK_125K, /**< 125 KHz from the high speed clock. */
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ADC_CLOCK_62K5, /**< 62.5 KHz from the high speed clock. */
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ADC_CLOCK_31K25, /**< 31.25 KHz from the high speed clock. */
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ADC_CLOCK_32K, /**< 32 KHz or 32.768 KHz from the low speed clock. */
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} qn908x_adc_clock_t;
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#ifdef DOXYGEN
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/** @brief Selected ADC oversample clock.
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*
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* Define to one of the qn908x_adc_clock_t values.
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*/
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#define QN908X_ADC_CLOCK
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/** @} */
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#endif /* ifdef DOXYGEN */
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/**
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* @brief ADC channel pair configuration
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*
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* The following are the possible combinations of + and - inputs to the ADC
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* sigma delta. Some of these combinations reference the "Vinn" signal which can
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* be independently selected, see @ref qn908x_adc_vinn_t for details.
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*
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* The first signal is connected to the positive side while the second one is
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* connected to the negative side. For example, ADC_CHANNEL_ADC0_ADC1 will read
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* a positive value if ADC0 voltage is higher than ADC1.
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*
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* The @ref ADC_CHANNEL_TEMP uses the internal temperature signal and
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* @ref ADC_CHANNEL_VCC4_VINN connects the + side to Vcc/4, which is useful to
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* measure the battery level when Vcc is directly connected to a battery.
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*/
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typedef enum {
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ADC_CHANNEL_ADC0_ADC1 = 0u << 9u, /**< Sample ADC0 / ADC1 */
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ADC_CHANNEL_ADC2_ADC3 = 1u << 9u, /**< Sample ADC2 / ADC3 */
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ADC_CHANNEL_ADC4_ADC5 = 2u << 9u, /**< Sample ADC4 / ADC5 */
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ADC_CHANNEL_ADC6_ADC7 = 3u << 9u, /**< Sample ADC6 / ADC7 */
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ADC_CHANNEL_ADC0_VINN = 4u << 9u, /**< Sample ADC0 / Vinn */
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ADC_CHANNEL_ADC1_VINN = 5u << 9u, /**< Sample ADC1 / Vinn */
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ADC_CHANNEL_ADC2_VINN = 6u << 9u, /**< Sample ADC2 / Vinn */
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ADC_CHANNEL_ADC3_VINN = 7u << 9u, /**< Sample ADC3 / Vinn */
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ADC_CHANNEL_ADC4_VINN = 8u << 9u, /**< Sample ADC4 / Vinn */
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ADC_CHANNEL_ADC5_VINN = 9u << 9u, /**< Sample ADC5 / Vinn */
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ADC_CHANNEL_ADC6_VINN = 10u << 9u, /**< Sample ADC6 / Vinn */
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ADC_CHANNEL_ADC7_VINN = 11u << 9u, /**< Sample ADC7 / Vinn */
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ADC_CHANNEL_TEMP = 13u << 9u, /**< Sample internal temperature */
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ADC_CHANNEL_VCC4_VINN = 14u << 9u, /**< Sample 1/4 Vcc / Vinn */
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ADC_CHANNEL_VINN_VINN = 15u << 9u, /**< Sample Vinn / Vinn */
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ADC_CHANNEL_VINN_VSS = 20u << 9u, /**< Sample Vinn / Vss */
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} qn908x_adc_channel_t;
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/**
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* @brief ADC Vref configuration
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*
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* This value affects the reference voltage used by the ADC as the full range.
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* It is also used in some cases to generate the Vinn signal are is only relevant for the channels that reference Vinn when it was
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* set by @ref qn908x_adc_vinn_t to use Vref. The actual values match the field
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* VREF_SEL in ADC CTRL register.
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*/
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typedef enum {
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ADC_VREF_1V2 = 0x0000u, /**< Vref := internal 1.2V. */
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ADC_VREF_VREF = 0x4000u, /**< Vref := external ADC_VREFI pin */
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ADC_VREF_VEXT = 0x8000u, /**< Vref := external ADC_VREFI with the driver */
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ADC_VREF_VCC = 0xC000u, /**< Vref := Vcc */
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} qn908x_adc_vref_t;
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/**
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* @brief ADC Vref x1.5 multiplier flag
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*
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* Note, this is the same value as ADC_CFG_VREF_GAIN_MASK. When enabled the
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* Vref voltage will be multiplied by 1.5x.
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*/
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#define ADC_VREF_GAIN_X15 (0x100u)
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/**
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* @brief ADC PGA Enabled flag
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*
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* Flag to enable the Programmable Gain Amplifier (PGA) with a gain of 1x. This
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* is only useful if the source signal doesn't have any driving capability since
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* the gain is set to 1x. The hardware supports other gain combinations but
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* those are not supported by the driver.
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*
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* Note: this value is defined as the inverse of ADC_CFG_PGA_BP_MASK which is
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* defined if the PGA is bypassed.
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*/
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#define ADC_PGA_ENABLE (0x08u)
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/**
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* @brief ADC Vinn configuration
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*
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* This value is only relevant for the channels that reference Vinn. The value
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* is the same as the PGA_VINN in ADC CFG register with a logic xor 0x30u to
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* make the default AVSS (analog Vss pad).
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*/
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typedef enum {
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ADC_VINN_VREF = 0x30u, /**< Use Vinn := Vref */
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ADC_VINN_VREF_3_4 = 0x20u, /**< Use Vinn := 3/4 * Vref */
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ADC_VINN_VREF_2 = 0x10u, /**< Use Vinn := 1/2 * Vref */
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ADC_VINN_AVSS = 0x00u, /**< Use Vinn := Vss */
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} qn908x_adc_vinn_t;
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/**
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* @brief ADC SD Gain configuration
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*
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* This multiplies the sampled value (difference between +/- signals) by the
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* given value.
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*
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* Note: these values logic xor 0x40 match the values for ADC_CFG_ADC_GAIN
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* field. This is selected so that omitting this flag in the config field
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* defaults to x1.0 gain but it can still be converted to the ADC_GAIN field
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* with a simple logic xor.
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*/
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typedef enum {
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ADC_GAIN_X05 = 0x40u, /**< Use gain := 0.5 */
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ADC_GAIN_X1 = 0x00u, /**< Use gain := 1 */
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ADC_GAIN_X15 = 0xC0u, /**< Use gain := 1.5 */
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ADC_GAIN_X20 = 0x80u, /**< Use gain := 2 */
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} qn908x_adc_gain_t;
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/**
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* @brief CPU specific ADC configuration
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*
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* ADC Channel, Vinn, Vref and gain configuration.
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*
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* This value should be set to the logic or between the following values:
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* * bit 3: the optional flag @ref ADC_PGA_ENABLE,
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* * bits 4-5: a @ref qn908x_adc_vinn_t value defining Vinn if needed,
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* * bits 6-7: a @ref qn908x_adc_gain_t optional gain value,
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* * bit 8: the optional flag @ref ADC_VREF_GAIN_X15,
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* * bits 9-13: the selected @ref qn908x_adc_channel_t, and
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* * bits 14-15: the @ref qn908x_adc_vref_t value defining Vref.
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*
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* The same channels with different settings can be configured as different ADC
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* lines in the board, just using different adc_conf_t entries.
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*/
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typedef uint16_t adc_conf_t;
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/** @} */
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/**
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* @brief CPU specific timer Counter/Timers (CTIMER) configuration
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* @{
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338
cpu/qn908x/periph/adc.c
Normal file
338
cpu/qn908x/periph/adc.c
Normal file
@ -0,0 +1,338 @@
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/*
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* Copyright (C) 2020 iosabi
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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/**
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* @ingroup cpu_qn908x
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* @ingroup drivers_periph_adc
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*
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* @{
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*
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* @file
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* @brief Low-level ADC driver implementation
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*
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* @author iosabi <iosabi@protonmail.com>
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*
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* This driver supports most of the ADC capabilities of the ADC block in this
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* CPU, but there are some functions left out of this driver:
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*
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* * The software decimation is fixed to 32 samples. This could be configured
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* per line instead with many more filtering options.
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*
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* * There's no amplification support (PGA) other than 1x. The main issue with
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* supporting this configuration even at build time only is that it also
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* requires to adjust the signal's common mode voltage level so that it
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* matches roughly Vcc/2, leaving enough dynamic range in the ADC. This is
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* maybe beyond the scope of this interface, but it could be configured from
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* the board if needed. See "PGA output VCM" section in the user manual for
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* details.
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*
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* @}
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*/
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#include <assert.h>
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#include <stdint.h>
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#include <stdlib.h>
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#include "bitarithm.h"
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#include "cpu.h"
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#include "mutex.h"
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#include "xtimer.h"
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#include "gpio_mux.h"
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#include "periph/adc.h"
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#include "vendor/drivers/fsl_clock.h"
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#define ENABLE_DEBUG 0
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#include "debug.h"
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#ifndef QN908X_ADC_CLOCK
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#define QN908X_ADC_CLOCK ADC_CLOCK_500K
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#endif
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/* Value of the ADC_CTRL_CLKSEL field which is actually CLKSEL in the lower two
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* bits (0 for 4 MHz source and 1 for 32 KHz source) and the divisor exponent
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* in the bits 2 to 4 (0 for 128 divisor and 7 for 1 divisor). */
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static const uint8_t adc_ctrl_clksel[] = {
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28, /* 4 MHz*/
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24, /* 2 MHz*/
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20, /* 1 MHz*/
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16, /* 500 KHz*/
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12, /* 250 KHz*/
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8, /* 125 KHz*/
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4, /* 62.5 KHz*/
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0, /* 31.25 KHz*/
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1, /* 32 KHz or 32.768 KHz from the low speed source. */
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};
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/* ADC oversample clock cycle in microseconds (used for delay). */
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static const uint8_t adc_clock_cycle_us[] = {
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1, /* 4 MHz*/
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1, /* 2 MHz*/
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1, /* 1 MHz*/
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2, /* 500 KHz*/
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4, /* 250 KHz*/
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8, /* 125 KHz*/
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16, /* 62.5 KHz*/
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32, /* 31.25 KHz*/
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32, /* 32 KHz or 32.768 KHz from the low speed source. */
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};
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/* Mutex for the public interface. This guards against two threads calling the
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* ADC at the same time. */
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static mutex_t adc_lock = MUTEX_INIT;
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/* Flag telling whether the ADC block was initialized. We only initialize the
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* ADC block once, although some pin initialization is done per ADC line. */
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static bool adc_init_done = false;
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/* Mutex to lock the @ref adc_sample function waiting for the interrupt to
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* retrieve the value. */
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static mutex_t adc_sample_isr_lock = MUTEX_INIT_LOCKED;
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/* Pointer to the variable that should hold the pending ADC result. This is
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* used by the ISR to store the value. */
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static volatile int32_t* adc_data_ptr = NULL;
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/* Factory calibration actual voltage of the internal 1.2V bandgap source. */
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static uint32_t adc_bandgap_calib_mv;
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/**
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* @brief Get the 1.2V bandgap reference voltage in mV.
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*/
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static uint32_t _adc_bandgap_calib_mv(void) {
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uint32_t calib = *(uint32_t*)FSL_FEATURE_FLASH_ADDR_OF_BANDGAP_VOL;
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DEBUG("[adc] bandgap calib = %" PRIu32 " mV\n", calib);
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/* Check that the bandgap calibration value stored in the Flash Information
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* Page (Section 7.3.1.1 in the User Manual) makes sense and use a
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* reasonable default otherwise. */
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if (calib < 1214 || calib > 1228) {
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calib = 1222;
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}
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return calib;
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}
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/* Extract the channel number from the adc_conf_t. */
|
||||
#define ADC_CONF_T_CHANNEL_NUM(conf) (((conf) >> 9u) & 0x1fu)
|
||||
|
||||
/* Mask to and against the adc_conf_t to get the channel enum value. */
|
||||
#define ADC_CONF_T_CHANNEL_MASK (0x1fu << 9u)
|
||||
|
||||
|
||||
int adc_init(adc_t line)
|
||||
{
|
||||
if (line >= ADC_NUMOF) {
|
||||
return -1;
|
||||
}
|
||||
mutex_lock(&adc_lock);
|
||||
if (!adc_init_done) {
|
||||
DEBUG("[adc] ADC block init\n");
|
||||
adc_bandgap_calib_mv = _adc_bandgap_calib_mv();
|
||||
|
||||
/* Power ON the ADC by clearing the disable (DIS) bits. */
|
||||
SYSCON->PMU_CTRL1 &= ~(SYSCON_PMU_CTRL1_ADC_BUF_DIS_MASK | /* PGA */
|
||||
SYSCON_PMU_CTRL1_ADC_BG_DIS_MASK |
|
||||
SYSCON_PMU_CTRL1_ADC_DIS_MASK |
|
||||
SYSCON_PMU_CTRL1_ADC_VCM_DIS_MASK | /* VINN */
|
||||
SYSCON_PMU_CTRL1_ADC_VREF_DIS_MASK);
|
||||
/* Need to wait 100 us before the ADC can be used for sampling. We could
|
||||
* in theory avoid this wait since it is only needed before adc_sample()
|
||||
* is called but it is short enough that it is safer to include it. */
|
||||
xtimer_usleep(100u);
|
||||
|
||||
/* Enable the ADC clock so we can use the ADC. */
|
||||
CLOCK_EnableClock(kCLOCK_Adc);
|
||||
/* Reset the ADC. */
|
||||
SYSCON->RST_SW_SET = SYSCON_RST_SW_SET_SET_ADC_RST_MASK;
|
||||
SYSCON->RST_SW_CLR = SYSCON_RST_SW_CLR_CLR_ADC_RST_MASK;
|
||||
|
||||
/* Enabled the ADC module: single conversion mode, scan disabled, window
|
||||
* mode disabled, 32-bit signed data format, software trigger.
|
||||
*/
|
||||
ADC->CTRL = ADC_CTRL_CLKSEL(adc_ctrl_clksel[QN908X_ADC_CLOCK]) |
|
||||
ADC_CTRL_CONV_MODE(1) | ADC_CTRL_SCAN_EN(0) |
|
||||
ADC_CTRL_CH_IDX_EN(0) |
|
||||
ADC_CTRL_DATA_FORMAT(1) | /* DATA is sign extended. */
|
||||
ADC_CTRL_SIG_INV_EN(0) |
|
||||
#ifdef CONFIG_BOARD_HAS_ADC_PA06_CAP
|
||||
ADC_CTRL_VREFO_EN(1) |
|
||||
#endif /* CONFIG_BOARD_HAS_ADC_PA06_CAP */
|
||||
ADC_CTRL_TRIGGER(35 /* software trigger */);
|
||||
|
||||
#ifdef CONFIG_BOARD_HAS_ADC_PA06_CAP
|
||||
/* Use PA06 as the ADC_EX_CAP signal. */
|
||||
gpio_init_mux(GPIO_PIN(PORT_A, 6), 1);
|
||||
#endif /* CONFIG_BOARD_HAS_ADC_PA06_CAP */
|
||||
|
||||
/* Always use CFG[0] to sample all channels. */
|
||||
ADC->CH_CFG = 0u;
|
||||
|
||||
/* Enable the PGA chopper. */
|
||||
ADC->BG_BF |= ADC_BG_BF_PGA_CHOP_EN_MASK;
|
||||
|
||||
/* Enable interrupts. */
|
||||
ADC->INTEN = ADC_INTEN_DAT_RDY_INTEN_MASK | ADC_INTEN_ADC_INTEN_MASK;
|
||||
|
||||
NVIC_EnableIRQ(ADC_IRQn);
|
||||
|
||||
adc_init_done = true;
|
||||
}
|
||||
const adc_conf_t conf = adc_config[line];
|
||||
DEBUG("[adc] ADC line %u init: ch=%u\n", line, ADC_CONF_T_CHANNEL_NUM(conf));
|
||||
|
||||
uint32_t func1_pins = 0;
|
||||
/* ADC pins are all function 1. */
|
||||
switch (conf & ADC_CONF_T_CHANNEL_MASK) {
|
||||
case ADC_CHANNEL_ADC0_ADC1:
|
||||
func1_pins = (1u << 0) | (1u << 1);
|
||||
break;
|
||||
case ADC_CHANNEL_ADC2_ADC3:
|
||||
func1_pins = (1u << 4) | (1u << 5);
|
||||
break;
|
||||
case ADC_CHANNEL_ADC4_ADC5:
|
||||
func1_pins = (1u << 8) | (1u << 9);
|
||||
break;
|
||||
case ADC_CHANNEL_ADC6_ADC7:
|
||||
func1_pins = (1u << 10) | (1u << 11);
|
||||
break;
|
||||
case ADC_CHANNEL_ADC0_VINN:
|
||||
func1_pins = 1u << 0;
|
||||
break;
|
||||
case ADC_CHANNEL_ADC1_VINN:
|
||||
func1_pins = 1u << 1;
|
||||
break;
|
||||
case ADC_CHANNEL_ADC2_VINN:
|
||||
func1_pins = 1u << 4;
|
||||
break;
|
||||
case ADC_CHANNEL_ADC3_VINN:
|
||||
func1_pins = 1u << 5;
|
||||
break;
|
||||
case ADC_CHANNEL_ADC4_VINN:
|
||||
func1_pins = 1u << 8;
|
||||
break;
|
||||
case ADC_CHANNEL_ADC5_VINN:
|
||||
func1_pins = 1u << 9;
|
||||
break;
|
||||
case ADC_CHANNEL_ADC6_VINN:
|
||||
func1_pins = 1u << 10;
|
||||
break;
|
||||
case ADC_CHANNEL_ADC7_VINN:
|
||||
func1_pins = 1u << 11;
|
||||
break;
|
||||
case ADC_CHANNEL_TEMP:
|
||||
/* Enable the internal temperature source. */
|
||||
ADC->BG_BF |= ADC_BG_BF_TEMP_EN_MASK;
|
||||
break;
|
||||
case ADC_CHANNEL_VCC4_VINN:
|
||||
/* Enable the Vcc/4 source. */
|
||||
SYSCON->ANA_EN |= SYSCON_ANA_EN_BAT_MON_EN_MASK;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
const uint32_t vref_sel = conf & ADC_CTRL_VREF_SEL_MASK;
|
||||
if (ADC_CTRL_VREF_SEL(1) == vref_sel || ADC_CTRL_VREF_SEL(2) == vref_sel) {
|
||||
/* ADC_VREFI (A7 pin) used as Vref input. */
|
||||
gpio_init_mux(GPIO_PIN(PORT_A, 7), 1);
|
||||
}
|
||||
while (func1_pins) {
|
||||
uint8_t pin;
|
||||
func1_pins = bitarithm_test_and_clear(func1_pins, &pin);
|
||||
gpio_init_mux(GPIO_PIN(PORT_A, pin), 1);
|
||||
}
|
||||
mutex_unlock(&adc_lock);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int32_t adc_sample(adc_t line, adc_res_t res) {
|
||||
if (line >= ADC_NUMOF) {
|
||||
return -1;
|
||||
}
|
||||
mutex_lock(&adc_lock);
|
||||
const adc_conf_t conf = adc_config[line];
|
||||
|
||||
/* Enable the ADC and set the Vref selection. */
|
||||
ADC->CTRL = (ADC->CTRL & ~ADC_CTRL_VREF_SEL_MASK) |
|
||||
ADC_CTRL_ENABLE_MASK | (conf & ADC_CTRL_VREF_SEL_MASK) ;
|
||||
/* The ADC needs one ADC clock cycle before it can be triggered after we
|
||||
* enabled it. */
|
||||
|
||||
/* Configure the channel parameters. We always use CFG[0]. */
|
||||
ADC->CH_SEL = 1u << ADC_CONF_T_CHANNEL_NUM(conf);
|
||||
ADC->CFG[0] =
|
||||
ADC_CFG_PGA_GAIN(0) | /* PGA gain = x1 */
|
||||
/* PGA_VINN, ADC_GAIN and VREF_GAIN directly from the config, flipping
|
||||
* 0x40 to default ADC_GAIN to x1.0, flipping 0x30 to default Vinn to
|
||||
* Vss and flipping 0x08 to default to PGA disabled (bypass enabled). */
|
||||
((conf ^ 0x78) & (ADC_CFG_PGA_BP_MASK | ADC_CFG_PGA_VINN_MASK |
|
||||
ADC_CFG_ADC_GAIN_MASK)) |
|
||||
ADC_CFG_PGA_VCM_EN(0) | /* Vcm control disabled. */
|
||||
/* TODO: Allow the board to configure the decimation. */
|
||||
ADC_CFG_DOWN_SAMPLE_RATE(1) | /* down sample 32 */
|
||||
ADC_CFG_DS_DATA_STABLE(7) |
|
||||
ADC_CFG_SCAN_INTV(4); /* Switching ADC source every 32 clock cycles. */
|
||||
|
||||
/* Need to wait for one ADC cycle before it can be started. */
|
||||
xtimer_usleep(adc_clock_cycle_us[QN908X_ADC_CLOCK]);
|
||||
|
||||
/* Configure the destination of the ADC value read from the interrupt. */
|
||||
volatile int32_t adc_data = 0;
|
||||
adc_data_ptr = &adc_data;
|
||||
|
||||
/* Triggers the sample event. When done the interrupt will fire and release
|
||||
* the mutex. */
|
||||
ADC->CTRL |= ADC_CTRL_SW_START_MASK;
|
||||
/* Wait for the interrupt to return a value in adc_data. */
|
||||
mutex_lock(&adc_sample_isr_lock);
|
||||
mutex_unlock(&adc_lock);
|
||||
|
||||
int32_t ret = -1;
|
||||
/* adc_data has 23-bit signed number, with the sign extended to an int32_t.
|
||||
*/
|
||||
if (res <= ADC_RES_MAX) {
|
||||
ret = adc_data >> (22 - res);
|
||||
} else if (res == ADC_RES_UV &&
|
||||
(conf & ADC_CTRL_VREF_SEL_MASK) == ADC_VREF_1V2) {
|
||||
/* Returning in uV is only supported when using Vref as the internal
|
||||
* 1.2v. */
|
||||
uint32_t vref = adc_bandgap_calib_mv;
|
||||
if (conf & ADC_VREF_GAIN_X15) {
|
||||
vref = vref + vref / 2;
|
||||
}
|
||||
/* adc_data is a signed 23 bit number and the Vref is at most 1.8v, so
|
||||
* an unsigned 11 bit number. To make this fit in signed 32-bit
|
||||
* arithmetic we need to drop some bits from the adc_data. Then we
|
||||
* convert the result to uV dividing by (1 << 20) which is now the full
|
||||
* scale of (adc_data >> 2) and multiplying by 1000. The last two
|
||||
* operations can be done as a single division still in 32-bit integer
|
||||
* space. */
|
||||
ret = ((adc_data >> 2) * (int32_t)vref) / ((1 << 20) / 1000);
|
||||
}
|
||||
DEBUG("[adc] sample line %u: ch=%u res=%u conf=0x%.4" PRIx16
|
||||
" adc=0x%.8" PRIx32 " ret=%" PRIi32 "\n",
|
||||
line, ADC_CONF_T_CHANNEL_NUM(conf), (unsigned)res, conf, adc_data,
|
||||
ret);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
void isr_adc(void)
|
||||
{
|
||||
if (ADC->INT & ADC_INT_DAT_RDY_INT_MASK) {
|
||||
uint32_t data = ADC->DATA;
|
||||
/* The DAT_RDY_INT bit clears automatically when reading the data. */
|
||||
if (adc_data_ptr) {
|
||||
*adc_data_ptr = data;
|
||||
}
|
||||
adc_data_ptr = NULL;
|
||||
mutex_unlock(&adc_sample_isr_lock);
|
||||
}
|
||||
|
||||
cortexm_isr_end();
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user