`flashpage_write_raw()` got renamed to `flashpage_write()`.
Now `sam0_flashpage_aux_write_raw()` is the only remaining 'raw'
function, even though it behaves just like `flashpage_write()`.
So let's also rename that for consistency.
The Cortex-m0 based ATSAM devices can use the Single-cycle I/O Port for
GPIO. This commit modifies the gpio_t type to use this port when
available. It is mapped back to the peripheral memory space for
configuration access. When it is not available, the _port_iobus() and
_port() functions behave identical, which is the case for the samd51.
The UART TX and TX lines on SAMD5x and SAML1x can be inverted.
However, the flags don't do exactly what one would expect.
See errata 2.18.5: SERCOM-UART: TXINV and RXINV Bits Reference:
> The TXINV and RXINV bits in the CTRLA register have inverted functionality.
>
> Workaround:
> In software interpret the TXINV bit as a functionality of RXINV, and conversely,
> interpret the RXINV bit as a functionality of TXINV.
Also adapt the defines to the documentation
- CPUs define up to 4 power modes (from zero, the lowest power mode,
to PM_NUM_MODES-1, the highest)
- >> there is an implicit extra idle mode (which has the number PM_NUM_MODES) <<
Previously on saml21 this would always generate pm_set(3) which is an illegal state.
Now pm_layered will correctly generate pm_set(2) for IDLE modes.
Idle power consumption dropped from 750µA to 368µA and wake-up from standby is also
possible. (Before it would just enter STANDBY again as the mode register was never
written with the illegal value.)
Add a fucntion to switch between LDO and Buck concerter to provide the
internal CPU voltage.
The Buck Converter is not compatible with internal fast oscillators (DFLL, DPLL)
and requires an inductivity to be present on the board.
All the more recent vendor files have them, so include them for samr30 too.
It is expected for this to become obsolete with the next vendor file update.
Creating an `exti_config` array for a new MCU manually is tedious and error prone.
Luckiely all information is already availiable in the vendor files.
Credit for this discovery & method goes to @Sizurka
The file was generated with
```C
int main(void) {
puts("static const int8_t exti_config[PORT_GROUPS][32] = {");
for (unsigned port = 1; port < 5; ++port) {
printf("#if PORT_GROUPS >= %d\n{\n", port);
for (unsigned pin = 0; pin < 32; ++pin) {
printf("#ifdef PIN_P%c%02uA_EIC_EXTINT_NUM\n", '@' + port, pin);
printf(" PIN_P%c%02uA_EIC_EXTINT_NUM,\n", '@' + port, pin);
printf("#else\n -1,\n#endif\n");
}
printf("},\n#endif\n\n");
}
puts("};");
return 0;
}
```
No changes in generated code are expected, but this makes adding new members
of the sam0 CPU families much easier.
samr30 is the only MCU of this family where the vendor files do not
define the PIN_($pin)_EIC_EXTINT_NUM macro yet.
This macro is needed to create a generic EXTI configuration for all
sam0 MCUs.
The defines were generated with
sed -Ei '/define PIN_(.*)_EIC_EXTINT([0-9]*)/
{h; x;
s/define PIN_(.*)A_EIC_EXTINT([0-9]*)(.*)/
define PIN_\1A_EIC_EXTINT_NUM _L_\(\2\)
\/**< \brief EIC signal: PIN_\1 External Interrupt Line *\/
/g; G}' samr30g18a.h samr30e18a.h
Instead of hard-coding the peripheral clocks to CLOCK_CORECLOCK
introduce helper functions to return the frequency of the individual
GCLKs and use those for baud-rate calculations.
This requires the GCLK to be part of the peripheral's config struct.
While this is already the case for most peripherals, this also adds
it for those where it wasn't used before.
As it defaults to 0 (CLOCK_CORECLOCK) no change is to be expected.
To simplify board definitions and for unification between samd2x and
newer models, don't use the GCLK bitmask in board definitions.
Instead use the GCLK index and generate the bitmask when needed.
Scan-build detected that sercom_id could return -1 and the value of this function is affected to uint8_t variables. Since these variables are used for shitfing bit in registers, this could lead to undefined behavior
This adds supoprt for the Atmel SAMD51 & SAME54 SoC.
The SAME5x/SAMD5x is a line of Cortex-M4F MCUs that share peripherals
with the samd2x Cortex-M0+ and saml1x Cortex-M23 parts.
Atmel Software Framework (ASF) provides a set of low-level header files
that give access to different hardware peripherals of Atmel's ICs.
Origin: Atmel SAMD51 Series Device Support (1.1.96)
License: Apache-2.0
URL: http://packs.download.atmel.com/Atmel.SAMD51_DFP.1.1.96.atpack
Atmel Software Framework (ASF) provides a set of low-level header
files that give access to different hardware peripherals of Atmel's
ICs.
Origin: Atmel SAME54 Series Device Support (1.0.87)
License: Apache-2.0
URL: http://packs.download.atmel.com/Atmel.SAME54_DFP.1.0.87.atpack
The currently supported SAM0 MCUs (samd21, saml21, saml1x) share the same
Timer peripheral, yet each of them carries it's own copy of the Timer
driver.
This introduces a new timer driver that is common for all sam0 MCUs and
uses structs for configuration instead of defines.
