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cpu/sam0_common: uart: implement the periph_uart_reconfigure feature
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@ -19,6 +19,7 @@ config CPU_COMMON_SAM0
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select HAS_PERIPH_TIMER_PERIODIC
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select HAS_PERIPH_UART_MODECFG
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select HAS_PERIPH_UART_NONBLOCKING
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select HAS_PERIPH_UART_RECONFIGURE
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select HAS_PERIPH_WDT
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select HAS_PERIPH_WDT_CB
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select HAS_PERIPH_WDT_WARNING_PERIOD
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@ -9,6 +9,7 @@ FEATURES_PROVIDED += periph_spi_reconfigure
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FEATURES_PROVIDED += periph_timer_periodic # implements timer_set_periodic()
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FEATURES_PROVIDED += periph_uart_modecfg
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FEATURES_PROVIDED += periph_uart_nonblocking
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FEATURES_PROVIDED += periph_uart_reconfigure
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FEATURES_PROVIDED += periph_wdt periph_wdt_cb periph_wdt_warning_period
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-include $(RIOTCPU)/cortexm_common/Makefile.features
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@ -189,6 +189,15 @@ typedef enum {
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UART_DATA_BITS_8 = 0x0, /**< 8 data bits */
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} uart_data_bits_t;
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/** @} */
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/**
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* @brief UART pin getters
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* @{
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*/
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#define uart_pin_rx(dev) uart_config[dev].rx_pin
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#define uart_pin_tx(dev) uart_config[dev].tx_pin
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/** @} */
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#endif /* ndef DOXYGEN */
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@ -188,6 +188,42 @@ int uart_init(uart_t uart, uint32_t baudrate, uart_rx_cb_t rx_cb, void *arg)
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return UART_OK;
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}
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void uart_init_pins(uart_t uart)
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{
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_configure_pins(uart);
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uart_poweron(uart);
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}
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void uart_deinit_pins(uart_t uart)
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{
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uart_poweroff(uart);
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/* de-configure RX pin */
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if (uart_config[uart].rx_pin != GPIO_UNDEF) {
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gpio_disable_mux(uart_config[uart].rx_pin);
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}
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/* de-configure TX pin */
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if (uart_config[uart].tx_pin != GPIO_UNDEF) {
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gpio_disable_mux(uart_config[uart].tx_pin);
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}
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#ifdef MODULE_PERIPH_UART_HW_FC
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/* If RTS/CTS needed, enable them */
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if (uart_config[uart].tx_pad == UART_PAD_TX_0_RTS_2_CTS_3) {
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/* Ensure RTS is defined */
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if (uart_config[uart].rts_pin != GPIO_UNDEF) {
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gpio_disable_mux(uart_config[uart].rts_pin);
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}
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/* Ensure CTS is defined */
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if (uart_config[uart].cts_pin != GPIO_UNDEF) {
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gpio_disable_mux(uart_config[uart].cts_pin);
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}
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}
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#endif
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}
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void uart_write(uart_t uart, const uint8_t *data, size_t len)
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{
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if (uart_config[uart].tx_pin == GPIO_UNDEF) {
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