From the ARMv7-M ARM section B3.5.3:
Where there is an overlap between two regions, the register with
the highest region number takes priority.
We want to make sure the mpu_noexec_ram region has the lowest
priority to allow the mpu_stack_guard region to overwrite the first N
bytes of it.
This change fixes using mpu_noexec_ram and mpu_stack_guard together.
cc2538 implements 4 sleep modes.
In the lightest mode (3) any interrupt source can wake up the CPU.
In mode 2, only RTT, GPIO or USB may wake the CPU.
In mode 1 only RTT and GPIO can wake the CPU.
In mode 0 only GPIO can wake the CPU.
In mode 0 and 1 the lower 16k RAM are lost. This is a problem since those
are usually used by RIOT.
The linkerscripts in cc2538/ldscripts take different approaches towards that.
Some only use the upper 16k and leave the other half to be managed by the
application.
`cc2538sf53.ld` which is used by `openmote-b` uses the entire RAM starting
at the lower half, so it will not be able to wake up from those modes.
A quick fix to test those modes with `tests/periph_pm` would be
--- a/cpu/cc2538/ldscripts/cc2538sf53.ld
+++ b/cpu/cc2538/ldscripts/cc2538sf53.ld
@@ -21,7 +21,7 @@ MEMORY
{
rom (rx) : ORIGIN = 0x00200000, LENGTH = 512K - 44
cca : ORIGIN = 0x0027ffd4, LENGTH = 44
- ram (w!rx) : ORIGIN = 0x20000000, LENGTH = 32K
+ ram (w!rx) : ORIGIN = 0x20004000, LENGTH = 16K
}
We have to read the DR for every byte that we write.
Just reading DR while SPI is busy in a loop can lead to bytes being
left in the fifo, corrupting subsequent reads.
- cpu/stm32f1: Removed previous code in gpio_init() to provide PB4 on the
Nucleo-F103RB only
- cpu/stm32_common: Introduced STM32F1_DISABLE_JTAG which, if defined in
board.h, exposes the JTAG only pins as GPIOs. This keeps the SWD pins, so that
SWD debugging remains possible
The internal DC/DC converter is more efficient compared to the LDO
regulator. The downside of the DC/DC converter is that it requires an
external inductor to be present on the board. Enabling the DC/DC
converter is guarded with NRF5X_ENABLE_DCDC, this macro must be defined
if the DC/DC converter is to be enabled.
This implements a basic Real Time Clock based on TIM2.
As the timer is too fast and wraps around after just 8 bits, it is
not used directly. Instead TIM2 is responsible for providing a 1 Hz
tick by generating an alarm every second.
The current time data is kept in the `.noinit` section, so it will survive
a reboot, but the clock will not be updated while the bootloader runs, so
expect inaccuracies.
By using a custom EPOCH for the RTC implementation, we can extend the
range of the 32 bit counter based RTC by 118 years.
It also reduces the code size compared to the stdlib based POSIX functions.
To be able to define common configurations for all ESP CPUs, the CPU specific configuration cpu_conf.h has to include a common configuration. For that purpose cpu_conf.h in cpu/esp_common is renamed to cpu_conf_common.h and included in CPU specific configurations.
The split between GEN2_ULP32K and GEN3_ULP32K was introduced to fix
a failure in tests/periph_wdt when the external oscillator was used.
By not running the external oscillator on demand, the failure can no
longer be observed, so default GEN3_ULP32K to GEN2_ULP32K.
The lpc23xx MCU has up to three I2C interfaces.
This adds a driver for it.
The peripheral works in interrupt mode, each change of the state machine
will generate an interrupt.
The response to the states are laid out in the data sheet.
This replaces the old driver that was removed in c560e28eb6
All the more recent vendor files have them, so include them for samr30 too.
It is expected for this to become obsolete with the next vendor file update.
During the write access to the SPI flash, the IROM cache is not available and only code from the IRAM can be executed. Therefore, the code of file system implementations which access the SPI flash must reside in IRAM.
For consistency, use named GCLKs.
- `SAM0_GCLK_32KHZ` will always be 2 for samd21
- `SAM0_GCLK_MAIN` will always be 0
So no change in functionality, just makes the code easier to understand.
The same tool 'gen_esp32part.py' is used for the generation of partition tables on ESP8266 as well as n ESP32. The tool is therefore added to 'dist/tools/esptool'
Creating an `exti_config` array for a new MCU manually is tedious and error prone.
Luckiely all information is already availiable in the vendor files.
Credit for this discovery & method goes to @Sizurka
The file was generated with
```C
int main(void) {
puts("static const int8_t exti_config[PORT_GROUPS][32] = {");
for (unsigned port = 1; port < 5; ++port) {
printf("#if PORT_GROUPS >= %d\n{\n", port);
for (unsigned pin = 0; pin < 32; ++pin) {
printf("#ifdef PIN_P%c%02uA_EIC_EXTINT_NUM\n", '@' + port, pin);
printf(" PIN_P%c%02uA_EIC_EXTINT_NUM,\n", '@' + port, pin);
printf("#else\n -1,\n#endif\n");
}
printf("},\n#endif\n\n");
}
puts("};");
return 0;
}
```
No changes in generated code are expected, but this makes adding new members
of the sam0 CPU families much easier.
Set the ONDEMAND bit so clocks are only run if they have a user configured.
This saves 390 µA on same54-xpro.
examples/default:
before: 3.88 mA
after : 3.49 mA
examples/gnrc_networking: (with REB215-XPRO EXT3)
before: 13.29 mA
after : 12.9 mA
samr30 is the only MCU of this family where the vendor files do not
define the PIN_($pin)_EIC_EXTINT_NUM macro yet.
This macro is needed to create a generic EXTI configuration for all
sam0 MCUs.
The defines were generated with
sed -Ei '/define PIN_(.*)_EIC_EXTINT([0-9]*)/
{h; x;
s/define PIN_(.*)A_EIC_EXTINT([0-9]*)(.*)/
define PIN_\1A_EIC_EXTINT_NUM _L_\(\2\)
\/**< \brief EIC signal: PIN_\1 External Interrupt Line *\/
/g; G}' samr30g18a.h samr30e18a.h
Previous value was 20 K, now it's 80 K. The older family of these MCUs
(cc13x0, cc26x0) had that size, currently for cc13x2 and cc26x2 it's
80 K.
Signed-off-by: Jean Pierre Dudey <jeandudey@hotmail.com>
From the data sheet:
> **Note:** Only in case when a reset occurs and the POR = 0, the BODR bit
indicates if the V DD(DCDC)(3V3) voltage was below 2.6 V or not.
So the value of BODR is undefined if POR is set.
Clear it to bring it to a defined state.
The function would always return `true` after early boot, so it
is not very useful for applications.
Now it will only (but always) return true when we woke from Deep Sleep
*after* early boot. This makes it behave the same ways as the function
of the same name on SAME54.
Rename the existing function to cpu_backup_ram_is_initialized() to better
match it's semantics.
On the MCB2388 plugging the power will result in both the POR and EXTR
bit being set.
Not sure if this is a property of the board, but it means RTC is also
reset after programming, so it behaves just like Backup RAM.
If we woke from Deep Sleep the POR bit will be cleared, so the RTC is not
reset.
RSIR is 0x1 (POR) if we woke from Deep Sleep.
This makes it hard to distinguish between real power-on and waking from
Deep Sleep, which is why the Backup RAM signature was introduced.
However, calling cpu_woke_from_backup() a second time will always return
true, as the signature will have been set up by early boot then.
Thus, clear the POR bit if the signature was already in place.
The result is:
RSIR == 0 -> woke from sleep
RSIR == 1 -> cold boot
Calling localtime() adds considerable overhead.
There are easier ways to set the date to 1970.
For tests/periph_rtc this results in this ROM change:
master:
text data bss dec hex
31328 240 98064 129632 1fa60
with this patch:
text data bss dec hex
20036 140 98168 118344 1ce48
The reboot process for ATmegas is to enable the watchdog timer and loop until
the wdt reboots this MCU. However, this reboot will keep the wdt configuration,
so that the wdt needs to be disabled during boot. This is done in get_mcusr,
but without the attribute "used" it will be optimized out in LTO builds. This
commits adds the attribute "used" to get_mcusr.
Also simplified the backward compatibility with older ATmegas (currently not
supported by RIOT) on outdated versions of avrlibc.
bitarithm.h is not needed for the interface of shed but may cause conflicts
due to different definitions of SETBIT and CLRBIT
common implementations are: (value, offset) xor (value, mask) bitarithm
implements the later
frac.c and nrf52/usbdev.c use bitarithm.h but where missing the include
sam0/rtt.c defined a bit using mask from bitarithm,
changed that to the soulution used in sam0/rtc.c
Instead of hard-coding the peripheral clocks to CLOCK_CORECLOCK
introduce helper functions to return the frequency of the individual
GCLKs and use those for baud-rate calculations.
This requires the GCLK to be part of the peripheral's config struct.
While this is already the case for most peripherals, this also adds
it for those where it wasn't used before.
As it defaults to 0 (CLOCK_CORECLOCK) no change is to be expected.
To simplify board definitions and for unification between samd2x and
newer models, don't use the GCLK bitmask in board definitions.
Instead use the GCLK index and generate the bitmask when needed.
There is size difference for atomic_int_fast8 and atomiic_uint_fast8
on FreeBSD, i.e., they match uint32_t with size of 4 bytes instead of
uint8_t with size of 8. Hence, tests/c11_atomics_cpp_compat buildtest
fails on FreeBSD.
The CC26x2 and CC13x2 share the same register definitions, and both are
treated equally in the TI's technical reference manual. [1]
- To avoid confusions in the future I renamed it to `cc26x2_cc13x2`.
- Documentation was updated.
- The `cc1312-launchpad` board that uses the `cc13x2` MCU was updated.
- The `cc1352-launchpad` board that uses the `cc13x2` MCU was updated.
[1]: https://www.ti.com/lit/ug/swcu185d/swcu185d.pdf
Signed-off-by: Jean Pierre Dudey <jeandudey@hotmail.com>
With the new toolchain version required to fix issue #13133, the compilation of `examples/posix_socket` fails due to a C linkage error in `atomic_base.h`. The reason is that including `drivers/include/mtd.h` in `boards/esp32/board_common.h` inside the `extern C` block finally leads to including `atomic_base.h` inside the `extern C` block which in turn to the C linkage error for the template definitions in this file.
For atmega boards a TX has not actually completed until UDRn is empty
as well as the Transmit Shift Register.
To avoid resetting an UART before a TX has completed we use the TXCn
flash and ISR to set a variables that indicates TX is ongoing. This
allows not reseting the UART while there are ongoing TX pending.
This fixes an issue where part of the last byte is not shifted out
of the TX shift register causing rubish on the first TX following an
uart_init.
The ADC_STATUS_SINGLEACT indicates that an operation is active, while
the ADC_STATUS_SINGLEDV indicates that data is valid.
This fixes ADC returning values of unfinished reads.
Without this change a RIOT application compiled with all-asan will
segfault as RIOT provides its own malloc by default. Add a define for
disabling custom malloc, calloc and realloc implementations and use it
when compiling with all-asan.
