The only peripheral that currently uses the FDPLL1 is SDHC. However, the SDHC IP can only be clocked at up to 150 MHz. Therefore, 100 MHz is currently used as the frequency of the FDPLL1. If another peripheral device requires 200 MHz in the future, this must be realized via different clock generators.
These functions can be used to set both FDPLL0 and FDPLL1 by using an extra argument 'idx' (index) and allow to set the ONDEMAND bit using the 'flags' argument
Signed-off-by: Dylan Laduranty <dylan.laduranty@mesotic.com>
Setting up a DMA transfer can take longer than sending out a buffer
byte by byte if the buffer is small.
DMA only shows advantages for large buffers, using it for every transfer
will cause a net slowdown.
Since we did not come up with a good way to determine the treshold based
on the SPI frequency, just use a fixed buffer for now so that DMA can be
used without slowing things down overall.
On samd5x only the RTC can wake the CPU from Deep Sleep (pm modes 0 & 1).
The external interrupt controller is disabled, but we can use the tamper
detection of the RTC.
If an gpio interrupt is configured on one of the five tamper detect pins,
those can be used to wake the CPU from Deep Sleep / Hibernate.
The sam0 MCUs all have a DAC peripheral.
The DAC has a resulution of 10 or 12 bits and can have one or two
output channels.
The output pins are always hard-wired to PA2 for DAC0 and PA5 for DAC1
if it exists.
On the same54-xpro I would only get a max value of ~1V when using the
internal reference, so I configured it to use an external voltage reference.
The external reference pin is hard-wired to PA3, so you'll have to connect
that to 3.3V to get results.
The DFLL on samd5x has a hardware bug that requires a special
re-enabling sequence when it is disabled and then re-enabled again.
When running the clock on-demand, the hardware handles the disabling
and re-enabling so that sequence does not get executed.
To reproduce, run `tests/periph_uart` on `same54-xpro`.
Without this patch the test will get seemingly stuck on `sleep_test()`.
(In fact it keeps running, but the DFLL has the wrong frequency so the
UART baudrate is wrong).
In this test, on `same54-xpro` only UART0 is sourced from DFLL.
So if the UART is disabled the DFLL will be turned off as well.
Also adapt the defines to the documentation
- CPUs define up to 4 power modes (from zero, the lowest power mode,
to PM_NUM_MODES-1, the highest)
- >> there is an implicit extra idle mode (which has the number PM_NUM_MODES) <<
Previously on saml21 this would always generate pm_set(3) which is an illegal state.
Now pm_layered will correctly generate pm_set(2) for IDLE modes.
Idle power consumption dropped from 750µA to 368µA and wake-up from standby is also
possible. (Before it would just enter STANDBY again as the mode register was never
written with the illegal value.)
When a previously disabled DFLL gets enabled again, the frequency will
be incorrect. Follow the procedure outlined in the errata sheet, section 2.8.3
to work around the issue.
This fixes wake from standby.
