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cpu/sam0_common: implement periph_rtc_mem
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@ -25,6 +25,7 @@
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*/
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#include <stdint.h>
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#include <string.h>
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#include "periph/rtc.h"
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#include "periph/rtt.h"
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#include "periph_conf.h"
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@ -215,10 +216,70 @@ static void _rtt_clock_setup(void)
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#endif /* MODULE_PERIPH_RTT */
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#endif /* !CPU_COMMON_SAMD21 - Clock Setup */
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#ifdef MODULE_PERIPH_RTC_MEM
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/* first two GP registers are shared with COMP[0] / ALARM[0] */
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#ifdef RTC_MODE2_CTRLB_GP2EN
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#define RTC_GPR_START (2)
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#else
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#define RTC_GPR_START (0)
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#endif
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#define RTC_GPR_NUM_AVAIL (RTC_GPR_NUM - RTC_GPR_START)
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#define RTC_MEM_SIZE (RTC_GPR_NUM_AVAIL * sizeof(uint32_t))
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size_t rtc_mem_size(void)
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{
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return RTC_MEM_SIZE;
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}
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static void _read_gp(uint32_t *dst)
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{
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for (unsigned i = RTC_GPR_START; i < RTC_GPR_NUM; ++i) {
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dst[i - RTC_GPR_START] = RTC->MODE0.GP[i].reg;
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}
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}
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static void _write_gp(const uint32_t *src)
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{
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for (unsigned i = RTC_GPR_START; i < RTC_GPR_NUM; ++i) {
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_wait_syncbusy();
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RTC->MODE0.GP[i].reg = src[i - RTC_GPR_START];
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}
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}
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void rtc_mem_read(unsigned offset, void *data, size_t len)
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{
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uint32_t tmp[RTC_GPR_NUM_AVAIL];
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if (offset + len > RTC_MEM_SIZE) {
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assert(0);
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return;
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}
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_read_gp(tmp);
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memcpy(data, ((uint8_t *)tmp) + offset, len);
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}
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void rtc_mem_write(unsigned offset, void *data, size_t len)
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{
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uint32_t tmp[RTC_GPR_NUM_AVAIL];
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if (offset + len > RTC_MEM_SIZE) {
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assert(0);
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return;
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}
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_read_gp(tmp);
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memcpy(((uint8_t *)tmp) + offset, data, len);
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_write_gp(tmp);
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}
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#endif /* MODULE_PERIPH_RTC_MEM */
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#ifdef MODULE_PERIPH_RTC
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static void _rtc_init(void)
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{
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#ifdef REG_RTC_MODE2_CTRLA
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/* skip reset if already in RTC mode */
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if (RTC->MODE2.CTRLA.bit.MODE == RTC_MODE2_CTRLA_MODE_CLOCK_Val) {
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return;
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}
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@ -229,6 +290,11 @@ static void _rtc_init(void)
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RTC->MODE2.CTRLA.reg = RTC_MODE2_CTRLA_PRESCALER_DIV1024 /* CLK_RTC_CNT = 1KHz / 1024 -> 1Hz */
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| RTC_MODE2_CTRLA_CLOCKSYNC /* Clock Read Synchronization Enable */
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| RTC_MODE2_CTRLA_MODE_CLOCK;
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#ifdef RTC_MODE2_CTRLB_GP2EN
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/* RTC driver does not use COMP[1] or ALARM[1] */
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/* Use second set of Compare registers as general purpose register */
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RTC->MODE2.CTRLB.reg = RTC_MODE2_CTRLB_GP2EN;
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#endif
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#else
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if (RTC->MODE2.CTRL.bit.MODE == RTC_MODE2_CTRL_MODE_CLOCK_Val) {
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return;
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@ -268,10 +334,26 @@ void rtc_init(void)
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#ifdef MODULE_PERIPH_RTT
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void rtt_init(void)
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{
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_rtt_clock_setup();
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_poweron();
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#ifdef MODULE_PERIPH_RTC_MEM
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uint32_t backup[RTC_GPR_NUM_AVAIL];
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_read_gp(backup);
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#endif
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_rtt_reset();
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#ifdef MODULE_PERIPH_RTC_MEM
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#ifdef RTC_MODE2_CTRLB_GP2EN
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/* RTC driver does not use COMP[1] or ALARM[1] */
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/* Use second set of Compare registers as general purpose register */
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RTC->MODE2.CTRLB.reg = RTC_MODE2_CTRLB_GP2EN;
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#endif
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_write_gp(backup);
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#endif /* MODULE_PERIPH_RTC_MEM */
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/* set 32bit counting mode & enable the RTC */
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#ifdef REG_RTC_MODE0_CTRLA
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RTC->MODE0.CTRLA.reg = RTC_MODE0_CTRLA_MODE(0)
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@ -15,6 +15,7 @@ config CPU_COMMON_SAMD5X
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select HAS_PERIPH_DMA
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select HAS_PERIPH_GPIO_TAMPER_WAKE
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select HAS_PERIPH_HWRNG
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select HAS_PERIPH_RTC_MEM
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select HAS_PERIPH_SPI_ON_QSPI
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config CPU_FAM_SAMD51
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@ -4,6 +4,7 @@ FEATURES_PROVIDED += periph_hwrng
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FEATURES_PROVIDED += backup_ram
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FEATURES_PROVIDED += cortexm_mpu
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FEATURES_PROVIDED += periph_gpio_tamper_wake
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FEATURES_PROVIDED += periph_rtc_mem
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FEATURES_PROVIDED += periph_spi_on_qspi
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include $(RIOTCPU)/sam0_common/Makefile.features
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@ -13,6 +13,7 @@ config CPU_COMMON_SAML21
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select HAS_CPU_SAML21
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select HAS_PERIPH_DMA
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select HAS_PERIPH_GPIO_FAST_READ
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select HAS_PERIPH_RTC_MEM
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config CPU_FAM_SAML21
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bool
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@ -10,6 +10,7 @@ FEATURES_PROVIDED += periph_gpio_fast_read
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# It can still be used in normal and standby mode, but code that relies on it
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# being availiable during deep sleep / backup mode will not be portable here.
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FEATURES_PROVIDED += backup_ram
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FEATURES_PROVIDED += periph_rtc_mem
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ifeq (,$(filter $(CPU_MODELS_WITHOUT_HWRNG),$(CPU_MODEL)))
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FEATURES_PROVIDED += periph_hwrng
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