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cpu/samd5x: change FDPLL1 frequency to 100 MHz

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The only peripheral that currently uses the FDPLL1 is SDHC. However, the SDHC IP can only be clocked at up to 150 MHz. Therefore, 100 MHz is currently used as the frequency of the FDPLL1. If another peripheral device requires 200 MHz in the future, this must be realized via different clock generators.
This commit is contained in:
Gunar Schorcht 2023-06-15 14:48:07 +02:00 committed by Benjamin Valentin
parent 1bed7dde15
commit b859da8495
2 changed files with 6 additions and 6 deletions
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10
cpu/samd5x/cpu.c
View File

@ -255,9 +255,9 @@ void sam0_gclk_enable(uint8_t id)
gclk_connect(SAM0_GCLK_PERIPH, GCLK_SOURCE_ACTIVE_XOSC, 0);
}
break;
case SAM0_GCLK_200MHZ:
fdpll_init_nolock(1, MHZ(200), OSCCTRL_DPLLCTRLA_ONDEMAND);
gclk_connect(SAM0_GCLK_200MHZ, GCLK_SOURCE_DPLL1, 0);
case SAM0_GCLK_100MHZ:
fdpll_init_nolock(1, MHZ(100), 0 /* OSCCTRL_DPLLCTRLA_ONDEMAND */);
gclk_connect(SAM0_GCLK_100MHZ, GCLK_SOURCE_DPLL1, 0);
fdpll_lock(1);
break;
}
@ -281,8 +281,8 @@ uint32_t sam0_gclk_freq(uint8_t id)
assert(0);
return 0;
}
case SAM0_GCLK_200MHZ:
return MHZ(200);
case SAM0_GCLK_100MHZ:
return MHZ(100);
default:
return 0;
}

2
cpu/samd5x/include/periph_cpu.h
View File

@ -65,7 +65,7 @@ enum {
SAM0_GCLK_32KHZ, /**< 32 kHz clock */
SAM0_GCLK_TIMER, /**< 4-8 MHz clock for xTimer */
SAM0_GCLK_PERIPH, /**< 12-48 MHz (DFLL) clock */
SAM0_GCLK_200MHZ, /**< 200MHz FDPLL clock */
SAM0_GCLK_100MHZ, /**< 100MHz FDPLL clock */
};
/** @} */