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Commit Graph

42 Commits

Author SHA1 Message Date
Marian Buschsieweke
525751c33b
cpu/riscv_common/periph_timer: Fix timer_clear()
Previously, timer_clear() was a no-op, resulting in spurious IRQs from
already canceled timeouts. This fixes the issue.
2023-01-09 00:08:59 +01:00
Joakim Nohlgård
b3d04d8270 riscv: Reduce reset trampoline code size by 2 bytes
`addi` with 20 bit immediate does not have a compressed representation,
so using `jalr` with immediate offset uncompressed is smaller than using
`addi`+`c.jr`
2022-12-08 13:26:07 +01:00
Benjamin Valentin
ea917f4b07 cpu: cpu_print_last_instruction() -> cpu_get_caller_pc() 2022-09-15 10:49:56 +02:00
Ollrogge
b21640f1e0 cpu/riscv_common: fix undeclared memory region linker error 2022-04-04 13:18:01 +02:00
chrysn
facb5e633f
Merge pull request #17436 from Ollrogge/reserve_flash
cpu: add flash_writable section to linker script
2022-03-17 21:44:32 +01:00
Ollrogge
74d086cdd6 cpu/riscv_common: add flash_writable section to linker script 2022-03-07 11:25:38 +01:00
PeterKietzmann
6215b7e630 cpu/riscv_common: add puf_sram feature 2022-02-16 15:18:37 +01:00
PeterKietzmann
992e09b07b cpu/riscv_common: add bss end to clear memory 2022-02-16 10:52:09 +01:00
PeterKietzmann
dd4fe70a62 cpu/riscv_common: add noinit section to ld script 2022-02-16 10:48:31 +01:00
Sören Tempel
e41063d40e cpu/riscv_common: fix undeclared memory region linker error
Since commit 3a11b1fbd2 (#16972)
building RIOT applications with `BOARD=hifive1` causes the following
linker error to be emitted on my system:

	/opt/rv32imc/lib/gcc/riscv32-unknown-elf/10.2.0/../../../../riscv32-unknown-elf/bin/ld:riscv_base.ld:220: warning: memory region `rom' not declared

This is due to the fact that the RISC-V linker script doesn't have a rom
memory region. While many other ARM-based boards have a rom memory
region defined in the linker script, the corresponding region name in
the RISC-V linker script is flash and rom is not declared as a memory
region hence the warning.

I think this was accidentally overlooked in
3a11b1fbd2. It is fixed in this commit by
replacing the rom region with the flash region. The linker script
identifiers (e.g. _srom and _erom) are not renamed.
2022-01-27 15:02:50 +01:00
chrysn
d391b1c5f4 cpu/riscv_common: Enable Rust applications
This contains a workaround for
https://github.com/rust-lang/rust-bindgen/issues/1555 (withouot which
bindgen would fail, with little information helping remedy the cause)
2022-01-14 13:42:32 +01:00
8272e4fbd2
Merge pull request #17359 from benpicco/irq_is_in-bool
core: change return type of irq_is_in(), irq_is_enabled() to bool
2022-01-06 18:13:20 +01:00
chrysn
a2e1b92e1d makefiles: Define RUST_TARGET for use with Cargo / Rust
For RISC-V and Cortex-M-not-3, triples are known and have worked in some
configuration, but do not work at the moment and stay disabled until the
reference platforms (native, M3) have been established well.
2021-12-14 12:55:13 +01:00
Benjamin Valentin
41a5b7ef7a core: change return type of irq_is_in(), irq_is_enabled() to bool
This only cleans up the API, no change in behavior or users of the API
is expected.
2021-12-08 15:53:15 +01:00
Erik Ekman
7825512d18 cpu/riscv_common: Suppress cppcheck error
cpu/riscv_common/thread_arch.c:188: error (comparePointers): Subtracting pointers that point to different objects
2021-11-25 13:08:51 +01:00
Jan Romann
3056b89252
cpu/riscv_common: uncrustify 2021-11-19 00:20:12 +01:00
Ollrogge
37403c09eb periph/flashpage: fix wrong doxygen group 2021-11-15 17:25:59 +01:00
Francisco
7f3344870d
Merge pull request #16972 from Ollrogge/flashpage_pr
periph/flashpage: extend API
2021-10-26 12:51:05 +02:00
Ollrogge
3a11b1fbd2 cpu/riscv_common: extend flashpage API 2021-10-25 15:07:37 +02:00
Benjamin Valentin
3e20e939c6 cpu: drop cpu_init() from public headers
Boards are no longer supposed fo call the function, so drop it from
public header files.
2021-10-18 17:31:26 +02:00
Benjamin Valentin
0f625eaebd cpu/riscv_common: call cpu_init() 2021-10-13 23:21:56 +02:00
Leandro Lanzieri
cf753c6790
cpu/riscv_common: model Kconfig 2021-10-01 11:26:15 +02:00
Karl Fessel
fe03c4c059 cpu/riscv,gd32: match Kconfig to Makefile changes 2021-09-22 15:50:28 +02:00
Karl Fessel
645cb04c4d cpu/riscv,gd32v: add CPU_ARCH, CPU_CORE information
adds CPU_ARCH to riscv_common preparing to handle it like cortex-m does
adds CPU_CORE to gd32v
2021-09-22 14:39:44 +02:00
Joakim Nohlgård
b70a4b7694 riscv: Simplify reset trampoline
By loading the absolute address of _start_real we can unconditionally
jump to it regardless if the PC is somewhere at 0x0 or at ROM_START_ADDR
2021-09-22 10:37:23 +02:00
Jean-Pierre De Jesus DIAZ
22a7e1af03 cpu/riscv_common: fix doxygen grouping warnings
Signed-off-by: Jean-Pierre De Jesus DIAZ <me@jeandudey.tech>
2021-09-11 12:45:15 +02:00
Francisco
3db378e015
Merge pull request #11117 from haukepetersen/add_core_irqisen
core: add irq_is_enabled() function to irq interface
2021-08-26 18:41:02 +02:00
Benjamin Valentin
a75ae3c938 cpu/riscv_common: move C lib selection to common place 2021-08-25 10:53:00 +02:00
Benjamin Valentin
a9c83017ee cpu/riscv_common: only select PLIC for fe310
Not every RISC-V implements that interrupt controller, gd32v uses
CLIC instead.
2021-08-25 10:49:47 +02:00
Hauke Petersen
9a5edcf839 cpu/riscv: implement irq_is_enabled() 2021-08-25 08:01:05 +02:00
benpicco
025770968b
Merge pull request #16036 from bergzand/pr/gd32vf103/initial
gd32v/seeedstudio-gd32: Initial support
2021-08-25 00:38:00 +02:00
f2787448e1 cpu/riscv_common: Move MCAUSE defines to riscv_common 2021-08-24 14:30:23 +02:00
48aa533639
cpu/riscv_common: Add CLIC peripheral driver
The CLIC is a next generation interrupt controller for the RISC-V
architecture.

Co-authored-by:
2021-08-24 10:30:18 +02:00
9239c2fe14
cpu/riscv_common: Add bit set and clear functions 2021-08-24 10:30:15 +02:00
c1d81cfb56
cpu/riscv_common: Jump to rom start on boot
With this the riscv start code jumps to the ROM start on boot when the
ROM area doesn't start at address 0x0.
2021-08-24 10:30:12 +02:00
Jan Romann
4384795cb9
treewide: Remove excessive newlines 2021-08-13 19:50:38 +02:00
Sören Tempel
628c199f51 riscv_common: explicitly mark handle_trap as used
The handle_trap function is used internally by the trap_entry
implementation from the same file. However, the trap_entry
implementation calls handle_trap from inline assembly. This makes it
difficult for the compiler to infer that the handle_trap function is
used at all. This causes issues when LTO is enabled.

Without this patch compiling any RISC-V RIOT code with `LTO=1` causes
the following linker error:

	/home/soeren/src/RIOT/cpu/riscv_common/irq_arch.c:134: undefined reference to `handle_trap'
	/tmp/hello-world.elf.Nngidp.ltrans0.ltrans.o:cpu/riscv_common/irq_arch.c:134:(.text.trap_entry+0x34):
	  relocation truncated to fit: R_RISCV_GPREL_I against undefined symbol `handle_trap'

This commit fixes LTO support for RISC-V.

While at it, also mark the function as static as it is only used by the
trap_entry function from the same compilation unit.
2021-05-05 15:03:12 +02:00
b3b04faadb cpu/fe310: add XFA support 2021-02-18 10:46:08 +01:00
Sören Tempel
5b15dc8932 fe310: Fix debug format strings
read_csr() returns an unsigned long, not a uint32_t. This causes a
-Wformat warning to be emitted when compiling with clang. This commit
fixes the warning by changing the format string.
2020-10-07 19:07:23 +00:00
Sören Tempel
125e4b54c1 fe310: Support the LLVM toolchain (i.e. compilation with clang)
This requires -nostartfiles to be only passed to the linker, not the
compiler, as it is a linker flag and passing it to the compiler causes a
clang warning to be emitted.

Additionally, clang does not seem to support `-mcmodel=medlow` and
`-msmall-data-limit=8` but these options do not seem strictly necessary
to me anyhow thus they are deactivated conditionally when using clang.
2020-10-07 07:37:52 +00:00
0b2810a856
riscv_common: make thread_yield_higher IRQ compatible 2021-02-08 11:04:18 +01:00
2692957c0e
riscv_common: Refactor common fe310 code to riscv_common 2021-02-05 09:32:19 +01:00