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RIOT/cpu/riscv_common
Sören Tempel 628c199f51 riscv_common: explicitly mark handle_trap as used
The handle_trap function is used internally by the trap_entry
implementation from the same file. However, the trap_entry
implementation calls handle_trap from inline assembly. This makes it
difficult for the compiler to infer that the handle_trap function is
used at all. This causes issues when LTO is enabled.

Without this patch compiling any RISC-V RIOT code with `LTO=1` causes
the following linker error:

	/home/soeren/src/RIOT/cpu/riscv_common/irq_arch.c:134: undefined reference to `handle_trap'
	/tmp/hello-world.elf.Nngidp.ltrans0.ltrans.o:cpu/riscv_common/irq_arch.c:134:(.text.trap_entry+0x34):
	  relocation truncated to fit: R_RISCV_GPREL_I against undefined symbol `handle_trap'

This commit fixes LTO support for RISC-V.

While at it, also mark the function as static as it is only used by the
trap_entry function from the same compilation unit.
2021-05-05 15:03:12 +02:00
..
include riscv_common: make thread_yield_higher IRQ compatible 2021-02-08 11:04:18 +01:00
ldscripts cpu/fe310: add XFA support 2021-02-18 10:46:08 +01:00
periph riscv_common: Refactor common fe310 code to riscv_common 2021-02-05 09:32:19 +01:00
context_frame.c riscv_common: Refactor common fe310 code to riscv_common 2021-02-05 09:32:19 +01:00
irq_arch.c riscv_common: explicitly mark handle_trap as used 2021-05-05 15:03:12 +02:00
Kconfig riscv_common: Refactor common fe310 code to riscv_common 2021-02-05 09:32:19 +01:00
Makefile riscv_common: Refactor common fe310 code to riscv_common 2021-02-05 09:32:19 +01:00
Makefile.dep riscv_common: Refactor common fe310 code to riscv_common 2021-02-05 09:32:19 +01:00
Makefile.features riscv_common: Refactor common fe310 code to riscv_common 2021-02-05 09:32:19 +01:00
Makefile.include riscv_common: Refactor common fe310 code to riscv_common 2021-02-05 09:32:19 +01:00
panic.c riscv_common: Refactor common fe310 code to riscv_common 2021-02-05 09:32:19 +01:00
riscv_init.c riscv_common: Refactor common fe310 code to riscv_common 2021-02-05 09:32:19 +01:00
start.S riscv_common: Refactor common fe310 code to riscv_common 2021-02-05 09:32:19 +01:00
thread_arch.c riscv_common: Refactor common fe310 code to riscv_common 2021-02-05 09:32:19 +01:00