Merge pull request #17359 from benpicco/irq_is_in-bool

core: change return type of irq_is_in(), irq_is_enabled() to bool

core/include/irq.h

@@ -78,16 +78,16 @@ MAYBE_INLINE void irq_restore(unsigned state);
  * @warning Use this function from thread context only. When used in interrupt
  *          context the returned state may be incorrect.
  *
- * @return  0 (false) if IRQs are currently disabled
- * @return  != 0 (true) if IRQs are currently enabled
+ * @return  false if IRQs are currently disabled
+ * @return  true if IRQs are currently enabled
  */
-MAYBE_INLINE int irq_is_enabled(void);
+MAYBE_INLINE bool irq_is_enabled(void);
 
 /**
  * @brief   Check whether called from interrupt service routine
  * @return  true, if in interrupt service routine, false if not
  */
-MAYBE_INLINE int irq_is_in(void);
+MAYBE_INLINE bool irq_is_in(void);
 
 #ifdef IRQ_API_INLINED
 #include "irq_arch.h"

cpu/arm7_common/include/irq_arch.h

@@ -40,7 +40,7 @@ static inline void __set_cpsr(unsigned val)
     __asm__ volatile(" msr  cpsr, %0" : /* no outputs */ : "r"(val) : "memory");
 }
 
-static inline int irq_is_in(void)
+static inline bool irq_is_in(void)
 {
     int retval;
     __asm__ volatile(" mrs  %0, cpsr" : "=r"(retval) : /* no inputs */ : "memory");
@@ -70,7 +70,7 @@ static inline __attribute__((always_inline)) unsigned irq_enable(void)
     return _cpsr;
 }
 
-static inline __attribute__((always_inline)) int irq_is_enabled(void)
+static inline __attribute__((always_inline)) bool irq_is_enabled(void)
 {
     return !(__get_cpsr() & IRQ_MASK);
 }

cpu/avr8_common/include/irq_arch.h

@@ -27,6 +27,7 @@
 #ifndef IRQ_ARCH_H
 #define IRQ_ARCH_H
 
+#include <stdbool.h>
 #include <stdint.h>
 #include <stdio.h>
 #include <stdint.h>
@@ -97,7 +98,7 @@ __attribute__((always_inline)) static inline void irq_restore(unsigned int _stat
 /**
  * @brief See if the current context is inside an ISR
  */
-__attribute__((always_inline)) static inline int irq_is_in(void)
+__attribute__((always_inline)) static inline bool irq_is_in(void)
 {
     uint8_t state = avr8_get_state();
     return (state & AVR8_STATE_FLAG_ISR);
@@ -106,7 +107,7 @@ __attribute__((always_inline)) static inline int irq_is_in(void)
 /**
  * @brief Test if interrupts are currently enabled
  */
-__attribute__((always_inline)) static inline int irq_is_enabled(void)
+__attribute__((always_inline)) static inline bool irq_is_enabled(void)
 {
     uint8_t mask;
     __asm__ volatile(

cpu/cortexm_common/include/irq_arch.h

@@ -19,6 +19,7 @@
 #ifndef IRQ_ARCH_H
 #define IRQ_ARCH_H
 
+#include <stdbool.h>
 #include <stdint.h>
 #include "cpu_conf.h"
 
@@ -61,7 +62,7 @@ static inline __attribute__((always_inline)) void irq_restore(
 /**
  * @brief See if IRQs are currently enabled
  */
-static inline __attribute__((always_inline)) int irq_is_enabled(void)
+static inline __attribute__((always_inline)) bool irq_is_enabled(void)
 {
     /* so far, all existing Cortex-M are only using the least significant bit
      * in the PRIMARK register. If ever any other bit is used for different
@@ -72,7 +73,7 @@ static inline __attribute__((always_inline)) int irq_is_enabled(void)
 /**
  * @brief See if the current context is inside an ISR
  */
-static inline __attribute__((always_inline)) int irq_is_in(void)
+static inline __attribute__((always_inline)) bool irq_is_in(void)
 {
     return (__get_IPSR() & 0xFF);
 }

cpu/esp_common/irq_arch.c

@@ -94,7 +94,7 @@ void IRAM irq_restore(unsigned int state)
 /**
  * @brief See if the current context is inside an ISR
  */
-int IRAM irq_is_in(void)
+bool IRAM irq_is_in(void)
 {
     DEBUG("irq_interrupt_nesting = %d\n", irq_interrupt_nesting);
     return irq_interrupt_nesting;
@@ -103,7 +103,7 @@ int IRAM irq_is_in(void)
 /**
  * @brief Test if IRQs are currently enabled
  */
-int IRAM irq_is_enabled(void)
+bool IRAM irq_is_enabled(void)
 {
     uint32_t reg;
 

cpu/mips32r2_common/irq_arch.c

@@ -35,11 +35,12 @@ void irq_restore(unsigned int state)
     }
 }
 
-int irq_is_in(void)
+bool irq_is_in(void)
 {
-    return (mips32_get_c0(C0_STATUS) & SR_EXL) != 0;
+    return mips32_get_c0(C0_STATUS) & SR_EXL;
 }
 
-int irq_is_enabled(void) {
+bool irq_is_enabled(void)
+{
     return mips32_get_c0(C0_STATUS) & SR_IE;
 }

cpu/msp430_common/include/irq_arch.h

@@ -23,6 +23,7 @@
 #ifndef IRQ_ARCH_H
 #define IRQ_ARCH_H
 
+#include <stdbool.h>
 #include <msp430.h>
 #include "irq.h"
 
@@ -83,12 +84,12 @@ __attribute__((always_inline)) static inline void irq_restore(unsigned int state
     );
 }
 
-__attribute__((always_inline)) static inline int irq_is_in(void)
+__attribute__((always_inline)) static inline bool irq_is_in(void)
 {
     return __irq_is_in;
 }
 
-__attribute__((always_inline)) static inline int irq_is_enabled(void)
+__attribute__((always_inline)) static inline bool irq_is_enabled(void)
 {
     unsigned int state;
     __asm__ volatile(

cpu/native/irq_cpu.c

@@ -227,12 +227,12 @@ void irq_restore(unsigned state)
     return;
 }
 
-int irq_is_enabled(void)
+bool irq_is_enabled(void)
 {
     return native_interrupts_enabled;
 }
 
-int irq_is_in(void)
+bool irq_is_in(void)
 {
     DEBUG("irq_is_in: %i\n", _native_in_isr);
     return _native_in_isr;

cpu/riscv_common/include/irq_arch.h

@@ -92,12 +92,12 @@ static inline __attribute__((always_inline)) void irq_restore(
 /**
  * @brief See if the current context is inside an ISR
  */
-static inline __attribute__((always_inline)) int irq_is_in(void)
+static inline __attribute__((always_inline)) bool irq_is_in(void)
 {
     return riscv_in_isr;
 }
 
-static inline __attribute__((always_inline)) int irq_is_enabled(void)
+static inline __attribute__((always_inline)) bool irq_is_enabled(void)
 {
     unsigned state;