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cpu/riscv_common: only select PLIC for fe310

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Not every RISC-V implements that interrupt controller, gd32v uses
CLIC instead.
This commit is contained in:
Benjamin Valentin 2021-08-25 10:49:47 +02:00
parent e92a4b9628
commit a9c83017ee
4 changed files with 2 additions and 2 deletions
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1
cpu/fe310/Kconfig
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@ -13,6 +13,7 @@ config CPU_FAM_FE310
select HAS_PERIPH_GPIO
select HAS_PERIPH_GPIO_IRQ
select HAS_PERIPH_PM
select HAS_PERIPH_PLIC
select HAS_PERIPH_RTT_OVERFLOW
select HAS_PERIPH_RTT_SET_COUNTER
select HAS_PERIPH_WDT

1
cpu/fe310/Makefile.features
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@ -1,6 +1,7 @@
FEATURES_PROVIDED += periph_cpuid
FEATURES_PROVIDED += periph_gpio periph_gpio_irq
FEATURES_PROVIDED += periph_pm
FEATURES_PROVIDED += periph_plic
FEATURES_PROVIDED += periph_rtt_overflow
FEATURES_PROVIDED += periph_rtt_set_counter
FEATURES_PROVIDED += periph_wdt

1
cpu/riscv_common/Kconfig
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@ -11,7 +11,6 @@ config CPU_ARCH_RISCV
select HAS_LIBSTDCPP
select HAS_NEWLIB
select HAS_PERIPH_CORETIMER
select HAS_PERIPH_PLIC
select HAS_PICOLIBC if '$(RIOT_CI_BUILD)' != '1'
select MODULE_MALLOC_THREAD_SAFE if TEST_KCONFIG
select HAS_SSP

1
cpu/riscv_common/Makefile.features
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@ -4,7 +4,6 @@ FEATURES_PROVIDED += cpp
FEATURES_PROVIDED += libstdcpp
FEATURES_PROVIDED += newlib
FEATURES_PROVIDED += periph_coretimer
FEATURES_PROVIDED += periph_plic
FEATURES_PROVIDED += ssp
# RISC-V toolchain on CI does not work properly with picolibc yet