cpu/riscv_common: uncrustify

cpu/riscv_common/include/atomic_utils_arch.h

@@ -18,7 +18,6 @@
 
 #ifndef ATOMIC_UTILS_ARCH_H
 #define ATOMIC_UTILS_ARCH_H
-#ifndef DOXYGEN
 
 #include "periph_cpu.h"
 
@@ -26,6 +25,8 @@
 extern "C" {
 #endif
 
+#ifndef DOXYGEN
+
 /* clang provides no built-in atomic access to regular variables */
 #ifndef __clang__
 
@@ -65,12 +66,13 @@ static inline void atomic_store_u32(volatile uint32_t *dest, uint32_t val)
     __atomic_store_4(dest, val, __ATOMIC_SEQ_CST);
 }
 
-#endif /* __clang__ */
+#endif  /* __clang__ */
+
+#endif  /* DOXYGEN */
 
 #ifdef __cplusplus
 }
 #endif
 
-#endif /* DOXYGEN */
 #endif /* ATOMIC_UTILS_ARCH_H */
 /** @} */

cpu/riscv_common/include/clic.h

@@ -38,10 +38,10 @@ typedef void (*clic_isr_cb_t)(unsigned irq);
  * @brief RISC-V CLIC per interrupt configuration registers
  */
 typedef struct __attribute((packed)) {
-    volatile uint8_t ip;     /**< Interrupt pending */
-    volatile uint8_t ie;     /**< Interrupt enable */
-    volatile uint8_t attr;   /**< Interrupt attributes */
-    volatile uint8_t ctl;    /**< Interrupt control */
+    volatile uint8_t ip;        /**< Interrupt pending */
+    volatile uint8_t ie;        /**< Interrupt enable */
+    volatile uint8_t attr;      /**< Interrupt attributes */
+    volatile uint8_t ctl;       /**< Interrupt control */
 } clic_clicint_t;
 
 /**

cpu/riscv_common/include/irq_arch.h

@@ -33,8 +33,8 @@ extern "C" {
 #endif
 
 /**
- * @brief   Bit mask for the MCAUSE register
- */
+ * @brief   Bit mask for the MCAUSE register
+ */
 #define CPU_CSR_MCAUSE_CAUSE_MSK        (0x0fffu)
 
 extern volatile int riscv_in_isr;
@@ -100,6 +100,7 @@ static inline __attribute__((always_inline)) int irq_is_in(void)
 static inline __attribute__((always_inline)) int irq_is_enabled(void)
 {
     unsigned state;
+
     __asm__ volatile (
         "csrr %[dest], mstatus"
         :[dest]    "=r" (state)

cpu/riscv_common/include/thread_arch.h

@@ -38,7 +38,7 @@ static inline void _ecall_dispatch(uint32_t num, void *ctx)
         "add a1, x0, %[ctx] \n"
         "ECALL\n"
         : /* No outputs */
-        : [num] "r" (num), [ctx] "r" (ctx)
+        :[num] "r" (num), [ctx] "r" (ctx)
         : "memory", "a0", "a1"
         );
 }

cpu/riscv_common/irq_arch.c

@@ -82,13 +82,15 @@ void riscv_irq_init(void)
 /**
  * @brief Global trap and interrupt handler
  */
-static void __attribute((used)) handle_trap(uint32_t mcause)
+__attribute((used))
+static void handle_trap(uint32_t mcause)
 {
     /*  Tell RIOT to set sched_context_switch_request instead of
      *  calling thread_yield(). */
     riscv_in_isr = 1;
 
     uint32_t trap = mcause & CPU_CSR_MCAUSE_CAUSE_MSK;
+
     /* Check for INT or TRAP */
     if ((mcause & MCAUSE_INT) == MCAUSE_INT) {
         /* Cause is an interrupt - determine type */
@@ -149,7 +151,8 @@ static void __attribute((used)) handle_trap(uint32_t mcause)
 /* Marking this as interrupt to ensure an mret at the end, provided by the
  * compiler. Aligned to 64-byte boundary as per RISC-V spec and required by some
  * of the supported platforms (gd32)*/
-static void __attribute((aligned(64))) __attribute__((interrupt)) trap_entry(void)
+__attribute((aligned(64)))
+static void __attribute__((interrupt)) trap_entry(void)
 {
     __asm__ volatile (
         "addi sp, sp, -"XTSTR (CONTEXT_FRAME_SIZE)"          \n"

cpu/riscv_common/periph/plic.c

@@ -30,8 +30,12 @@
 #include "plic.h"
 
 /* Local macros to calculate register offsets */
-#define _REG32(p, i) 			(*(volatile uint32_t *) ((p) + (i)))
-#define PLIC_REG(offset) 		_REG32(PLIC_CTRL_ADDR, offset)
+#ifndef _REG32
+#define _REG32(p, i)            (*(volatile uint32_t *)((p) + (i)))
+#endif
+#ifndef PLIC_REG
+#define PLIC_REG(offset)        _REG32(PLIC_CTRL_ADDR, offset)
+#endif
 
 /* PLIC external ISR function list */
 static plic_isr_cb_t _ext_isrs[PLIC_NUM_INTERRUPTS];