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Commit Graph

32 Commits

Author SHA1 Message Date
Marian Buschsieweke
2ea8601b69
cpu/samd5x/periph_cph.h: drop non-UTF-8 chars
There were some bogus chars in a comment. Let's drop them.
2024-10-08 14:16:24 +02:00
Firas Hamdi
b35e60e720 cpu/samd5x: add CAN error codes 2024-05-16 15:00:28 +02:00
Benjamin Valentin
16cfaab235 cpu/samd5x: fix C++ build 2024-03-27 00:15:36 +01:00
Firas Hamdi
e4e5558694 cpu/samd5x: implement driver for samd5x CAN controller
cpu/samd5x: load RX mailbox
2024-03-26 15:17:48 +01:00
Urs Gompper
12acc8dec9 cpu/samd5x: make GCLK definitions overwritable 2023-11-23 21:00:16 +01:00
Urs Gompper
b1e31fbf61 cpu/samd5x: define GCLK pins 2023-11-23 21:00:15 +01:00
Gunar Schorcht
33d1e82b73 cpu/samd5x: define power modes 2023-09-23 19:26:30 +02:00
Gunar Schorcht
b859da8495 cpu/samd5x: change FDPLL1 frequency to 100 MHz
The only peripheral that currently uses the FDPLL1 is SDHC. However, the SDHC IP can only be clocked at up to 150 MHz. Therefore, 100 MHz is currently used as the frequency of the FDPLL1. If another peripheral device requires 200 MHz in the future, this must be realized via different clock generators.
2023-06-20 12:48:54 +02:00
Dylan Laduranty
6607ed10f6 cpu/samd5x: add support for FDPLL1 running at 200MHz
Signed-off-by: Dylan Laduranty <dylan.laduranty@mesotic.com>
2023-05-16 16:04:17 +02:00
Dylan Laduranty
ba83e13d10 cpu/samd5x: fix SAM0_DPLL_FREQ_MAX_HZ value
Signed-off-by: Dylan Laduranty <dylan.laduranty@mesotic.com>
2023-05-16 15:53:20 +02:00
Benjamin Valentin
9dcb3991d2 cpu/sam0_common: move adc_res_t to common code 2023-01-17 17:18:07 +01:00
benpicco
baf1687951
Merge pull request #18146 from benpicco/cpu/sam0_common/adc-diffmode
cpu/sam0_common: adc: add support for differential mode
2022-09-27 17:34:07 +02:00
Benjamin Valentin
361a94460a cpu/sam0_common: add ADC pin aliases 2022-08-31 18:23:44 +02:00
Benjamin Valentin
babee877ce cpu/sam0_common: add SD Host Controller implementation 2022-05-31 11:07:20 +02:00
Benjamin Valentin
75ee373b01 cpu/samd5x: define ADC pins
rg define\ PIN_.*_AIN | grep ADC | cut -d' ' -f2 | sort | uniq | sed -E "s/PIN_(P[A-F])([0-9][0-9])B_ADC0_AIN([0-9]*)/\3 GPIO_PIN(\1, \2),/" | sort -n | grep GPIO | cut -d ' ' -f2- | sed -E "s/0([0-9])/\1/"
rg define\ PIN_.*_AIN | grep ADC | cut -d' ' -f2 | sort | uniq | sed -E "s/PIN_(P[A-F])([0-9][0-9])B_ADC1_AIN([0-9]*)/\3 GPIO_PIN(\1, \2),/" | sort -n | grep GPIO | cut -d ' ' -f2- | sed -E "s/0([0-9])/\1/"
2022-05-30 20:41:18 +02:00
Benjamin Valentin
11acdd0526 cpu/samd*: adjust PM_BLOCKER_INITIAL to the new API
For saml1x and samd5x this becomes now obsolete as the default provides
this behavior.
2022-04-06 12:29:25 +02:00
Benjamin Valentin
7c3bfb980e cpu/samd5x: allow to block IDLE mode
Make it possible to prevent the CPU clock from stopping.
2022-03-29 18:14:41 +02:00
Jean-Pierre De Jesus DIAZ
480e22be66 cpu/sam*: fix doxygen grouping warnings
Signed-off-by: Jean-Pierre De Jesus DIAZ <me@jeandudey.tech>
2021-09-11 12:45:15 +02:00
Benjamin Valentin
8f72212eb0 cpu/sam0_common: SPI: add support for QSPI in SPI mode
We can use the QSPI peripheral as an additional (non-Quad) SPI peripheral.
2020-12-11 22:33:08 +01:00
Benjamin Valentin
edbb5fe9d0 cpu/samd5x: add NVM User Page Mapping 2020-11-10 12:18:47 +01:00
Benjamin Valentin
310eb4970c cpu/sam0_common: GPIO: use tamper detection to wake from Deep Sleep
On samd5x only the RTC can wake the CPU from Deep Sleep (pm modes 0 & 1).
The external interrupt controller is disabled, but we can use the tamper
detection of the RTC.

If an gpio interrupt is configured on one of the five tamper detect pins,
those can be used to wake the CPU from Deep Sleep / Hibernate.
2020-09-17 18:46:25 +02:00
János Brodbeck
7a7f06a3e1
cpu/samd5x: add ADC resolution type 2020-08-19 17:48:37 +02:00
Benjamin Valentin
fba3aab2f3 cpu/samd5x: rename GCLK defines
Now that the GCLK defines are not always at a fixed frequency, rename
them to better reflect this.
2020-06-20 00:25:54 +02:00
Benjamin Valentin
17304d390c cpu/samd5x: use MHZ() macro 2020-06-20 00:25:53 +02:00
Benjamin Valentin
849c76578a cpu/samd5x: allow to use XOSC as clock source
Allow to run the main clock and all peripheral clocks off XOSC.
This is necessary if we want to use the buck voltage regulator.
2020-06-20 00:10:08 +02:00
Francisco Molina
36baec4512
cpu/samd5x: add unified rtt configuration 2020-06-19 09:16:23 +02:00
Benjamin Valentin
bfb3d52a63 cpu/sam0_common: implement periph/dac
The sam0 MCUs all have a DAC peripheral.
The DAC has a resulution of 10 or 12 bits and can have one or two
output channels.

The output pins are always hard-wired to PA2 for DAC0 and PA5 for DAC1
if it exists.

On the same54-xpro I would only get a max value of ~1V when using the
internal reference, so I configured it to use an external voltage reference.

The external reference pin is hard-wired to PA3, so you'll have to connect
that to 3.3V to get results.
2020-05-02 18:31:55 +02:00
Benjamin Valentin
5d123cbb22 cpu/sam0_common: distribute PM_NUM_MODES among siblings
Also adapt the defines to the documentation

 - CPUs define up to 4 power modes (from zero, the lowest power mode,
   to PM_NUM_MODES-1, the highest)
 - >> there is an implicit extra idle mode (which has the number PM_NUM_MODES) <<

Previously on saml21 this would always generate pm_set(3) which is an illegal state.
Now pm_layered will correctly generate pm_set(2) for IDLE modes.

Idle power consumption dropped from 750µA to 368µA and wake-up from standby is also
possible. (Before it would just enter STANDBY again as the mode register was never
written with the illegal value.)
2020-04-01 18:10:23 +02:00
Benjamin Valentin
fd9a247200 cpu/sam0_common: use generic exti_config
Creating an `exti_config` array for a new MCU manually is tedious and error prone.
Luckiely all information is already availiable in the vendor files.

Credit for this discovery & method goes to @Sizurka

The file was generated with

```C

int main(void) {
        puts("static const int8_t exti_config[PORT_GROUPS][32] = {");

        for (unsigned port = 1; port < 5; ++port) {
                printf("#if PORT_GROUPS >= %d\n{\n", port);
                for (unsigned pin = 0; pin < 32; ++pin) {
                        printf("#ifdef PIN_P%c%02uA_EIC_EXTINT_NUM\n", '@' + port, pin);
                        printf("    PIN_P%c%02uA_EIC_EXTINT_NUM,\n", '@' + port, pin);
                        printf("#else\n    -1,\n#endif\n");
                }
                printf("},\n#endif\n\n");
        }

        puts("};");

        return 0;
}
```

No changes in generated code are expected, but this makes adding new members
of the sam0 CPU families much easier.
2020-02-20 11:23:51 +01:00
Benjamin Valentin
38b6ee56f3 cpu/sam0: use defines for GCLK IDs
Give the clocks explicit names to better identify their meaning.
2020-02-04 21:16:54 +01:00
Benjamin Valentin
736e5e5a35 cpu/samd5x: allow more flexible selection of CLOCK_CORECLOCK
There are some constraints to the oscillators on the samd5x.

 - DFLL is fixed to run at 48 MHz
 - DPLL can run at 96 to 200 MHz

Always use DFLL for frequencies <= 48 MHz.
For frequencies >= 96 MHz, use DPLL directly.
For frequencies < 96 MHz, clock DPLL at twice the desired frequency
and use a divider.
2019-09-27 10:49:43 +02:00
Benjamin Valentin
f375b00ff3 cpu/samd5x: add support for samd5x/same5x MCUs
This adds supoprt for the Atmel SAMD51 & SAME54 SoC.
The SAME5x/SAMD5x is a line of Cortex-M4F MCUs that share peripherals
with the samd2x Cortex-M0+ and saml1x Cortex-M23 parts.
2019-06-06 16:47:11 +02:00