RIOT-OS/RIOT
RIOT-OS/RIOT
1
0
Fork 0
mirror of https://github.com/RIOT-OS/RIOT.git synced 2024-12-29 04:50:03 +01:00
Code Releases Activity
29,732 Commits 40 Branches 189 Tags 262 MiB
a73c03ed0c
Commit Graph

5623 Commits

Author SHA1 Message Date
Dylan Laduranty
57c1a49a82
Merge pull request #13957 from benpicco/cpu/samd21-pwm_flex 
cpu/samd21: PWM don't hard-code number of channels to 3
 2020-05-02 20:52:56 +02:00
Martine Lenders
ad89680c40
Merge pull request #14004 from gschorcht/cpu/esp32/fix_newlib_nano_printf_float 
cpu/esp32: fix printf for float with newlib-nano
 2020-05-02 20:43:00 +02:00
Dylan Laduranty
76870721fe
Merge pull request #13965 from benpicco/cpu/sam0_common/periph/dac 
cpu/sam0_common: implement periph/dac
 2020-05-02 20:34:40 +02:00
Jean Pierre Dudey
4bf6a4db04
cc26x2_cc13x2: separate arrays with newline 
Signed-off-by: Jean Pierre Dudey <jeandudey@hotmail.com>
 2020-05-02 13:25:41 -05:00
Jean Pierre Dudey
a66c693ad5
cc26x2_cc13x2: add oscillator switching functions 
Signed-off-by: Jean Pierre Dudey <jeandudey@hotmail.com>
 2020-05-02 13:25:41 -05:00
Jean Pierre Dudey
0aeed80eb0
cc26xx_cc13xx: add ROM Hard-API 
This is needed to switch the SCLK_HF source clock safely.

Note: these functions work on cc26x2_cc13x2 and cc26x0, but special care
needs to be taken when calling on cc26x0 some of these functions, as
ADDI_SEM needs to be taken.

Signed-off-by: Jean Pierre Dudey <jeandudey@hotmail.com>
 2020-05-02 13:25:41 -05:00
Francois Berder
8db01ab9a0 cpu: mips_pic32_common: Implement GPIO IRQ 
Signed-off-by: Francois Berder <18538310+francois-berder@users.noreply.github.com>
 2020-05-02 17:59:17 +01:00
Benjamin Valentin
bfb3d52a63 cpu/sam0_common: implement periph/dac 
The sam0 MCUs all have a DAC peripheral.
The DAC has a resulution of 10 or 12 bits and can have one or two
output channels.

The output pins are always hard-wired to PA2 for DAC0 and PA5 for DAC1
if it exists.

On the same54-xpro I would only get a max value of ~1V when using the
internal reference, so I configured it to use an external voltage reference.

The external reference pin is hard-wired to PA3, so you'll have to connect
that to 3.3V to get results.
 2020-05-02 18:31:55 +02:00
Gunar Schorcht
5fbf74b203 cpu/esp32: fix printf for float with newlib-nano 2020-05-02 16:56:29 +02:00
PeterKietzmann
dd2d6b174e cpu/nrf5x_common: enable bias correction in hwrng 2020-05-01 17:04:36 +02:00
Benjamin Valentin
c05984b341 cpu/sam0_common: timer: don't ignore frequency in timer_init() 
Now that we can query the GCLK frequency at run-time, there is no need
to implicitely hard-code the timer frequency in the config struct anymore.
 2020-05-01 16:44:06 +02:00
benpicco
99e8b04921
Merge pull request #13812 from gschorcht/cpu/esp32/fix_newlib_nano 
cpu/esp32: use module newlib_nano
 2020-05-01 14:40:02 +02:00
benpicco
4150afea00
Merge pull request #13749 from gschorcht/cpu/esp32/periph_rtt 
cpu/esp32: replace RTC implementation by RTT implementation
 2020-05-01 14:14:01 +02:00
benpicco
c95e4c3b9e
Merge pull request #13816 from btcven/2020_04_02-setup-trim-device 
cc26x2_cc13x2: trim device registers on `cpu_init`.
 2020-05-01 14:09:08 +02:00
Benjamin Valentin
89a145ab0c cpu/lpc2387: clocks: minor style fix 2020-04-30 20:43:41 +02:00
Benjamin Valentin
c262c91561 cpu/lpc2387: PM: enable SLEEP & POWERDOWN mode 
We have to re-init PLL (and Flash) after wake from those modes.
 2020-04-30 20:43:41 +02:00
Benjamin Valentin
3b257f9a5a cpu/lpc2387: export functions to init PLL & MAM 
Those functions are needed after wake from lower sleep modes.
 2020-04-30 20:43:41 +02:00
Jean Pierre Dudey
951a99dba3
cc26x2_cc13x2: add setup_trim_device function 
This function trims the necessary registers for the device to operate
normally.

Signed-off-by: Jean Pierre Dudey <jeandudey@hotmail.com>
 2020-04-29 18:32:58 -05:00
Jean Pierre Dudey
dc1d2ace42
cc26xx_cc13xx: add ADI3 and masked access 
- Added ADI instruction offsets
- Added register banks and address bases for masked access (writes).

Signed-off-by: Jean Pierre Dudey <jeandudey@hotmail.com>
 2020-04-29 18:32:58 -05:00
Jean Pierre Dudey
92589c2129
cc26x2_cc13x2: update AON_PMCTL register bank 
- Updated documentation.
- Fixed offset of JTAGUSERCODE.
- Added necessary register values to perform startup trims.

Signed-off-by: Jean Pierre Dudey <jeandudey@hotmail.com>
 2020-04-29 18:16:45 -05:00
Jean Pierre Dudey
e2489ced97
cc26xx_cc13xx: add register values 
Add some register values needed to trim registers.

Signed-off-by: Jean Pierre Dudey <jeandudey@hotmail.com>
 2020-04-29 18:16:45 -05:00
Jean Pierre Dudey
e514266186
cc26x2_cc13x2: add FCFG->DAC_BIAS_CNF values 
These are necessary to trim some registers at startup.

Signed-off-by: Jean Pierre Dudey <jeandudey@hotmail.com>
 2020-04-29 18:16:45 -05:00
Jean Pierre Dudey
6829dfdf1b
cc26xx_cc13xx: fix FLASH->CFG offset, update VIMS 
- Changed "meh" to "Reserved".
- Renamed CTL to CFG to match SDK/TRM name.
- Added constants for VIMS and FLASH necessary to trim registers.

Signed-off-by: Jean Pierre Dudey <jeandudey@hotmail.com>
 2020-04-29 18:16:45 -05:00
Jean Pierre Dudey
1733e62217
cc26xx_cc13xx: update AON_IOC register bank 
- Updated documentation
- Fixed register bank name
- Added missing field

Signed-off-by: Jean Pierre Dudey <jeandudey@hotmail.com>
 2020-04-29 18:16:45 -05:00
Jean Pierre Dudey
cdf2e88804
cc26x2_cc13x2: add 16-bit masked access to DDI_0_OSC 
Signed-off-by: Jean Pierre Dudey <jeandudey@hotmail.com>
 2020-04-29 18:16:45 -05:00
Jean Pierre Dudey
1586c89f1a
cc26x2_cc13x2: update DDI_0_OSC register bank 
- Fixes padding.
- Updates documentation.
- Removes documentation longer than 80-chars for the registers values.

Signed-off-by: Jean Pierre Dudey <jeandudey@hotmail.com>
 2020-04-29 10:17:20 -05:00
Jean Pierre Dudey
2921944c66
cc26x2_cc13x2: add function to change AUX opmode 
This function is needed to setup the AUX operational mode at startup,
also used for managing low-power states.

Signed-off-by: Jean Pierre Dudey <jeandudey@hotmail.com>
 2020-04-29 09:38:36 -05:00
Alexandre Abadie
5a9f01d91a
native: pass eeprom file path via command line 2020-04-29 08:56:33 +02:00
Alexandre Abadie
cbdda3c990
cpu/native: read/persist EEPROM data at startup/reboot/exit 2020-04-29 08:55:10 +02:00
Alexandre Abadie
4e1d7abddc
cpu/native: implement eeprom peripheral driver 
The driver simply manages an internal buffer in memory that can be filled/dumped from/to a file
 2020-04-29 08:55:08 +02:00
benpicco
4bb8fab1dc
Merge pull request #13971 from bergzand/pr/sam0_common/cpuid_clarify 
sam0_common: clarify memcpy in cpuid_get
 2020-04-28 18:31:27 +02:00
benpicco
96c638f2d1
Merge pull request #13949 from benpicco/MAKEFILEDIR-doc 
Makefile.include: update the documentation of $(MAKEFILEDIR)
 2020-04-28 18:30:44 +02:00
Benjamin Valentin
d5dce87e1b Makefile.include: rename MAKEFILEDIR to LAST_MAKEFILEDIR 
Rename the variable to make it clearer that it refers to the last Makefile
included.
Usually this is the current file, but when another Makefile is included this
changes.
 2020-04-28 15:45:27 +02:00
Koen Zandberg
fe299138aa
sam0_common: clarify memcpy in cpuid_get 2020-04-28 14:56:19 +02:00
Francisco Molina
b78e4efb56
cpu/stm32f1: dont provide periph_rtc at cpu level 
stm32f1 periph_rtc implementation gets a 1s resolution by dividing
CLOCK_LSx by 32768. This only make sense if CLOCK_LSE is set,
otherwise CLOCK_LSI=~40000, which will lead to an imprecise rtc.
 2020-04-27 08:59:21 +02:00
benpicco
4ceff67ca0
Merge pull request #13127 from francois-berder/remove-objcopy-warning 
cpu: mips_pic32*: Fix unused .gcc_except_table section warning
 2020-04-26 23:27:30 +02:00
Benjamin Valentin
da89f6ac5f cpu/samd21: don't hard-code number of channels 
Each TCC can have 8 PWM channels, so don't hard-code
3 channels/TCC.
 2020-04-26 22:26:01 +02:00
Marian Buschsieweke
70a558059e
Merge pull request #13955 from benpicco/cpu/lpc2387-pm_num_modes 
cpu/lpc2387: PM_NUM_MODES must only count non-idle modes
 2020-04-26 21:46:40 +02:00
benpicco
bbe1e723df
Merge pull request #13936 from btcven/2020_04_23-aux 
cc26x2_cc13x2: fix AUX_* register domain documentation
 2020-04-26 20:41:40 +02:00
Benjamin Valentin
c21b5d6f55 cpu/lpc2387: PM_NUM_MODES must only count non-idle modes 
lpc23xx has 3 sleep modes and one idle mode.
`PM_NUM_MODES` must only count the idle modes.

In practise, this makes no difference since `mode 3` (IDLE) is
the `default` case in `pm_set()` anyway.
 2020-04-26 19:45:43 +02:00
benpicco
5ca030b311
Merge pull request #13937 from btcven/2020_04_23-flash-aux 
cc26xx_cc13xx: update VIMS/FLASH documentation
 2020-04-26 17:23:51 +02:00
Jean Pierre Dudey
81d0d7c1f8
cc26x2_cc13x2: update AUX domain documentation 
The following registers were updated:

- AIO_AIODIOx documentation
- AUX_TDC documentation
- AUX_EVCTL documentation
- AUX_SYSIF documentation
  - Fixed a copy/paste error in AUX_SYSIF definition.
  - Registers now match original names.
- AUX_TIMER01 documentation
- AUX_TIMER2 documentation
- AUX_SMPH documentation
- AUX_ANAIF documentation
- update ADI_4_AUX documentation
  - Added missing LPMBIAS register
- ADDI_SEM documentation

Signed-off-by: Jean Pierre Dudey <jeandudey@hotmail.com>
 2020-04-26 09:35:26 -05:00
Francisco Molina
4d398ab09e
cpu/stm32f1: add unified rtt configuration 2020-04-24 08:57:04 +02:00
Jean Pierre Dudey
0aba7556d0
cc26xx_cc13xx: update VIMS/FLASH documentation 
Also i've fixed the register bank offsets, 0x4 was being added without
need.

Signed-off-by: Jean Pierre Dudey <jeandudey@hotmail.com>
 2020-04-23 17:10:18 -05:00
Marian Buschsieweke
fdf955cfb2
Merge pull request #13899 from Hoernchen20/stm32f1_adc 
boards/blxxxpill: improve adc
 2020-04-22 23:07:26 +02:00
Hoernchen20
11618d32c0 cpu/stm32f1/periph_adc: Reduce power consumption 2020-04-22 21:08:20 +02:00
Hoernchen20
4e87682ba1 boards/common/blxxxpill: Add internal ADC lines 2020-04-22 21:08:20 +02:00
Leandro Lanzieri
db316c14a7
Merge pull request #13919 from benpicco/cpu/lpc2387-fix_rtc 
cpu/lpc2387: fix RTC leap year calculation
 2020-04-22 11:10:37 +02:00
Benjamin Valentin
4ee8d3f4d2 cpu/lpc2387: enable full rtc_normalize() for RTC 
The RTC actually makes use of the day of year / day of week fields,
so enable the calculation of those fields in rtc_normalize().
 2020-04-22 10:39:33 +02:00
Koen Zandberg
3e922f878a
Merge pull request #13875 from fjmolinas/pr_core_macros 
core/includes: add common macros file
 2020-04-21 15:32:51 +02:00
Francisco Molina
da90407572
cpu/esp_common/include: include common xtstr header 2020-04-21 15:10:55 +02:00
Francisco
3d8f71768c
Merge pull request #13846 from benpicco/Makefile-THISDIR 
Makefile.include: add $(MAKEFILEDIR) helper and use it
 2020-04-21 11:00:52 +02:00
Matthew Bradbury
ba51e90228 cpu/cc2538: Flush the RX FIFO (if overflowed) after a receive 2020-04-20 18:19:23 +01:00
Matthew Bradbury
bcfb437746 cpu/cc2538: Do not check XREG_RSSISTATbits for RSSI_VALID 2020-04-20 18:18:56 +01:00
Matthew Bradbury
ecfe4a4e8f cpu/cc2538: Check CRC of received message after reading message contents 2020-04-20 18:18:56 +01:00
Matthew Bradbury
fc0581056a cpu/cc2538: Check for a minimum length to read from a received frame 2020-04-20 18:18:56 +01:00
Matthew Bradbury
f0e48f0741 cpu/cc2538: Prevent underflow of the RX FIFO 2020-04-20 18:18:53 +01:00
Benjamin Valentin
370fff90a8 cpu/lpc2387: timer: use lpc2387_pclk_scale() 2020-04-19 15:32:42 +02:00
Martine Lenders
55a7010a0a
Merge pull request #13157 from nmeum/pr/fuzzing_tcp_only 
Add AFL-based fuzzing setup for network modules
 2020-04-18 10:54:14 +02:00
Gunar Schorcht
bb51fbb7ec cpu/esp32: fix GPIO32 and GPIO 33 as I2C pins 
GPIO32 and GPIO33 are used during boot to start an 32.768 kHz XTAL if it is connected to these GPIOs. If the 32.768 kHz XTAL is not connected, these pins can be used digital IO. However, the 32.678 kHz XTAL has to be disabled explicitly in this case. Furthermore, the handling of GPIOs greater than GPIO31 had to be fixed in I2C software implementation.
 2020-04-17 18:46:15 +02:00
benpicco
91200aa6ea
Merge pull request #13867 from btcven/2020_04_14-ccfg-fcfg1 
cc26xx_cc13xx: fix CCFG/FCFG1 register offsets
 2020-04-15 17:33:12 +02:00
benpicco
7aa62006e7
Merge pull request #13840 from btcven/2020_04_06-uart1 
cc26xx_cc13xx: fix UART1 initialization
 2020-04-15 17:15:24 +02:00
Benjamin Valentin
c1d05f07a5 cpu/kinetis: use $(MAKEFILEDIR) 2020-04-15 11:51:11 +02:00
Jean Pierre Dudey
e944638d3d
cc26x2_cc13x2: fix FCFG1 register offsets 
Signed-off-by: Jean Pierre Dudey <jeandudey@hotmail.com>
 2020-04-14 17:22:02 -05:00
Jean Pierre Dudey
cbcd7d58e7
cc26xx_cc13xx: fix CCFG offset on x2 variants 
Signed-off-by: Jean Pierre Dudey <jeandudey@hotmail.com>
 2020-04-14 17:15:56 -05:00
benpicco
b9fda5630e
Merge pull request #13851 from iosabi/vectors_cortexm 
Allow to define reserved fields in CortexM vector table.
 2020-04-14 23:18:29 +02:00
Akshai M
642fe16807 cpu/nrf52/include/nrf802154.h : Add Group 
Add CT Params to netdev group in Config for Doxygen
 2020-04-14 20:52:16 +05:30
Benjamin Valentin
cfe606b601 cpu/lpc2387: gpio: Don't discriminate between rising & falling pins 
The `test_irq()` function does not discriminate between rising and
falling pins, so there is no need to handle them separately.
 2020-04-12 21:31:42 +02:00
Benjamin Valentin
6233175f16 cpu/lpc2387: gpio: Fix interrupts on PORT2 
The calculation of `_state_index` is broken for `port = 2`

    _gpio_isr_map[n + (port<<1)];

Will not yield the right result. As a consequence, IRQs on Port 2
are not working.
The right thing here would be

    _gpio_isr_map[n + (port ? 32 : 0)];

But we might just re-using the `_isr_map_entry()` function.
Also only iterate as many times as there are set interrupt bits.
 2020-04-12 21:31:42 +02:00
iosabi
7e7b6e1cfe Allow to define reserved fields in CortexM vector table. 
The ARM CortexM vector table has some reserved fields which are used by
some manufacturers to store their custom image information. In
particular, NXP QN908X stores the checksum, Code Read Protection, image
type and boot block pointer in this region.

This patch allows the cpu and board modules to define the value of these
fields at build time by defining a macro.
 2020-04-10 10:37:41 +00:00
Leandro Lanzieri
a06d9bbb66
Merge pull request #13315 from jia200x/pr/kconfig/ieee802154 
ieee802154: Expose configurations to Kconfig
 2020-04-08 19:34:55 +02:00
Jean Pierre Dudey
d4084d6df9
cc26xx_cc13xx: fix UART1 initialization 
Signed-off-by: Jean Pierre Dudey <jeandudey@hotmail.com>
 2020-04-08 12:24:02 -05:00
Jose Alamos
77325b4cde ieee802154: add CONFIG_ prefix to config macros 2020-04-08 19:08:25 +02:00
Leandro Lanzieri
c36f2ee077
cpu/Kconfig: Declare common CPU symbols 
The symbols used to define a CPU are:
- CPU
- CPU_MODEL
- CPU_FAMILY
- CPU_ARCH
 2020-04-08 17:37:06 +02:00
Dylan Laduranty
f9a4c509b1
Merge pull request #13797 from benpicco/cpu/samd21-pwm 
cpu/samd21: pwm: allow to use channels > 3
 2020-04-08 15:45:22 +02:00
Benjamin Valentin
4d90a9c6b5 cpu/samd21: pwm: fix GCLK_ID & APBCMASK calculation 
GCLK_ID and APBCMASK entries are not always uniform.
The previous hack would already break for TCC3.

Just explosively write down the cases, there are only 5 at most.
 2020-04-08 15:24:05 +02:00
Alexandre Abadie
ee3fc27e96
cpu/fe310: implement driver for watchdog 2020-04-07 14:37:55 +02:00
Sören Tempel
d7104e4992 makefiles/toolchain: add support for afl 2020-04-07 14:24:10 +02:00
Leandro Lanzieri
d60295db3c
Merge pull request #13720 from aabadie/pr/native_no_export 
native: only export NATIVEINCLUDES in vars.inc.mk
 2020-04-07 12:55:45 +02:00
Gunar Schorcht
ce431b2343 cpu/esp32: use RTT based RTC implementation 2020-04-07 09:12:44 +02:00
Gunar Schorcht
0e7eb48d6a cpu/esp32: use RTT instead of RTC in pm_layered 2020-04-07 09:12:44 +02:00
Gunar Schorcht
f67cb48f6d cpu/esp32: add RTT counter implementation 
fixup! cpu/esp32: add RTT counter implementation
 2020-04-07 09:12:44 +02:00
Benjamin Valentin
4451765952 cpu/lpc2387: fix check for max number of timers 
The CPU has 4 hardware timers.
Configuration for all 4 timers exists, but the compile-time range
check has an off-by-one error, causing the last timer to remain
inaccessible.
 2020-04-05 01:56:55 +02:00
Gunar Schorcht
f2e776bd3f cpu/esp32: use module newlib_nano 2020-04-04 13:37:22 +02:00
benpicco
b87be4bd6e
Merge pull request #13786 from benpicco/cpu/saml21/buck_converter 
cpu/saml21: enable buck voltage regulator when possible
 2020-04-03 18:12:05 +02:00
Gunar Schorcht
6cd9896ac0 cpu/esp: move BACKUP* attributes to esp_common 2020-04-03 18:07:12 +02:00
Gunar Schorcht
a0b77de3dc cpu/esp8266: move RTC_BSS_ATTR to cpu/esp_common 
Since the attribute is required by EPS8266 as well as ESP32, it is moved to cpu/esp_common.
 2020-04-03 18:07:12 +02:00
Pekka Nikander
4534e9b773
cpu/cortexm_common: add irq sub-priorities 
This commit enables Cortex-M CPU interrupt sub-priorities
and allows the PendSV interrupt to have a priority different
from the default one.  Together these two preprocessor
defines can be used to have PendSV always run as the last interrupt
before returning from the interrupt stack back to the user space.

Running PendSV as the last interrupt before returning to the
user space is recommended by ARM, as it increases efficiency.
Furthermore, that change enhances stability a lot with the
new nRF52 SoftDevice support, currently being worked in
PR #9473.

This commit merely enables sub-priorities and a separate
PendSV priority to be used without changing the default
RIOT behaviour.
 2020-04-03 17:49:31 +02:00
Benjamin Valentin
01c573c612 cpu/samd21: pwm: allow to use channels > 3 
Channels 4…7 are on the CCB register.
 2020-04-03 01:02:38 +02:00
Benjamin Valentin
49fda3e900 cpu/samd5x: don't run DFLL on-demand 
The DFLL on samd5x has a hardware bug that requires a special
re-enabling sequence when it is disabled and then re-enabled again.

When running the clock on-demand, the hardware handles the disabling
and re-enabling so that sequence does not get executed.

To reproduce, run `tests/periph_uart` on `same54-xpro`.

Without this patch the test will get seemingly stuck on `sleep_test()`.
(In fact it keeps running, but the DFLL has the wrong frequency so the
UART baudrate is wrong).

In this test, on `same54-xpro` only UART0 is sourced from DFLL.
So if the UART is disabled the DFLL will be turned off as well.
 2020-04-02 20:11:41 +02:00
Benjamin Valentin
f037e06b13 cpu/saml21: enable buck voltage regulator when possible 
Switch from the on-chip LDO to the on-chip buck voltage regulator
when not fast internal oscillators are used.

On `saml21-xpro` with `examples/default` this gives

**before:** 750 µA
** after:** 385 µA
 2020-04-02 17:25:16 +02:00
Benjamin Valentin
3f95d3d2e3 cpu/saml21: pm: set deep flag 
Set the deep flag for consistency with other family members.
 2020-04-02 17:25:13 +02:00
Benjamin Valentin
7e156dd2e5 cpu/saml1x, saml2x: PM_NUM_MODES is a valid mode 
The mode PM_NUM_MODES is the IDLE mode, so do not skip it.
 2020-04-01 18:10:23 +02:00
Benjamin Valentin
5d123cbb22 cpu/sam0_common: distribute PM_NUM_MODES among siblings 
Also adapt the defines to the documentation

 - CPUs define up to 4 power modes (from zero, the lowest power mode,
   to PM_NUM_MODES-1, the highest)
 - >> there is an implicit extra idle mode (which has the number PM_NUM_MODES) <<

Previously on saml21 this would always generate pm_set(3) which is an illegal state.
Now pm_layered will correctly generate pm_set(2) for IDLE modes.

Idle power consumption dropped from 750µA to 368µA and wake-up from standby is also
possible. (Before it would just enter STANDBY again as the mode register was never
written with the illegal value.)
 2020-04-01 18:10:23 +02:00
Benjamin Valentin
f6139ae346 cpu/samd5x: work around errata when (re-)initializing DFLL 
When a previously disabled DFLL gets enabled again, the frequency will
be incorrect. Follow the procedure outlined in the errata sheet, section 2.8.3
to work around the issue.

This fixes wake from standby.
 2020-04-01 15:41:20 +02:00
Dylan Laduranty
6bba4188fc
Merge pull request #13764 from benpicco/cpu/saml11/use_buck_converter 
cpu/saml1x: select buck voltage regulator when possible
 2020-04-01 14:47:47 +02:00
Leandro Lanzieri
ea2f963302
cpu/cortexm: Add 'cortexm_fpu' as a DEFAULT_MODULE if possible 
This adds cortexm_fpu to the DEFAULT_MODULE list when the feature
cortexm_fpu is provided by the architecture. It also moves the
dependency resolution of this module to the architecture-specific
Makefile.dep file.
 2020-04-01 09:46:29 +02:00
Leandro Lanzieri
64552a3b9a
cpu/cortexm_common: Move common modules to Makefile.dep 
This moves the following modules to a architecture-specific Makefile.dep
file:
- cortexm_common
- cortexm_common_periph
- newlib
- newlib_nano
- periph
 2020-04-01 09:46:21 +02:00
benpicco
e5562a89a3
Merge pull request #13765 from gschorcht/cpu/esp/fix_netopt_link_type 
cpu/esp: fix type for NETOPT_LINK for esp_wifi/esp_eth
 2020-03-31 21:51:08 +02:00
Gunar Schorcht
579de1a1e7 cpu/esp: deprecated NETOPT_LINK_CONNECTED renamed 2020-03-31 18:11:47 +02:00
Gunar Schorcht
aa3de05601 cpu/esp: fix netopt_enabled_t handling in esp_wifi/esp_eth 2020-03-31 18:11:36 +02:00
Dylan Laduranty
6a788b3c02
Merge pull request #13761 from RIOT-OS/cpu/samd5x/rtc_workaround 
cpu/samd5x: disable RTC on init to prevent undefined RTC state
 2020-03-31 17:25:25 +02:00
Benjamin Valentin
895eb943d8 cpu/sam0_common: add cpu_pm_cb_enter()/leave() 
This allows to implement needed work-arounds surrounding sleep on
a per-MCU basis.
 2020-03-31 17:18:58 +02:00
Benjamin Valentin
005de7024b cpu/saml1x: enable buck voltage regulator 
Switch from the on-chip LDO to the on-chip buck voltage regulator.
 2020-03-31 17:18:58 +02:00
Benjamin Valentin
9b90fd478a cpu/sam0_common: provide function to switch voltage regulator 
Add a fucntion to switch between LDO and Buck concerter to provide the
internal CPU voltage.
The Buck Converter is not compatible with internal fast oscillators (DFLL, DPLL)
and requires an inductivity to be present on the board.
 2020-03-31 17:18:20 +02:00
Francisco
1a8b35f54b
Merge pull request #13377 from leandrolanzieri/pr/kconfig_migrate/drivers/periph_wdt 
drivers/periph/wdt: Expose configurations to Kconfig
 2020-03-31 16:36:36 +02:00
Dylan Laduranty
783ffdc28a
Merge pull request #13607 from benpicco/cpu/sam0_common/generic_RAM_ROM 
cpu/sam0_common: derive ROM_LEN & RAM_LEN from part number
 2020-03-31 15:55:04 +02:00
Benjamin Valentin
d12abe6a2b cpu/samd5x: disable RTC on init to prevent undefined RTC state 
When changing the clock configuration while the RTC is running, the
RTC may end up in an undefined state that leaves it unresponsive.

The RTC is not reset to stay persistent across reboots/hibernate, so
it will not be reset on init.
Instead, disable the RTC while configuring the clocks, rtc_init() will
take care of re-enabling it.

@dylad introduced this workaround for saml21, samd5x needs it too.

To reproduce, set the CLOCK_CORECLOCK of a samd5x board (e.g. same54-xpro)
to 48 MHz.
Run any RTC application. The CPU will be stuck in _wait_syncbusy() after
a reboot.
This patch will fix this. (You will need to power-cycle the board if the
RTC has entered the stuck state as it will never be reset.)
 2020-03-31 15:34:55 +02:00
benpicco
97acdd94c5
Merge pull request #13677 from gschorcht/cpu/esp/esp_wifi/modem_sleep 
cpu/esp_common: allow WiFi modem sleep mode
 2020-03-31 14:15:06 +02:00
Leandro Lanzieri
f69427fcf7
cpu/saml1x: Add Kconfig file 2020-03-31 13:39:41 +02:00
Leandro Lanzieri
218f7bfe0c
cpu/saml21: Add Kconfig file 2020-03-31 13:39:41 +02:00
Leandro Lanzieri
daf38f2500
cpu/samd5x: Add Kconfig file 2020-03-31 13:39:40 +02:00
Leandro Lanzieri
c43543c21a
cpu/samd21: Add Kconfig file 2020-03-31 13:39:40 +02:00
Leandro Lanzieri
cf53a86308
cpu/sam0_common: Add CPU-specific WDT peripheral configuration 2020-03-31 13:39:39 +02:00
Leandro Lanzieri
00b71a2708
drivers/wdt: Move WDT_WARNING_PERIOD to 'CONFIG_' namespace 2020-03-31 13:39:37 +02:00
Gunar Schorcht
1505c105d2 cpu/esp32: allow WiFi modem sleep 
Due to stability reasons, the SoftAP interface of the WiFi module was always enabled in former versions even if only the station interface was used. Therefore the WiFi modem had to be always active and the SoC could not enter the modem sleep mode. Therefore, the SoftAP interface is only enabled when ESP-NOW is used.
 2020-03-31 13:17:23 +02:00
Alexandre Abadie
934f68ead8
Merge pull request #13094 from francois-berder/pic32-uart-3 
UART RX implementation on PIC32 devices
 2020-03-31 10:45:43 +02:00
benpicco
7e85081ddc
Merge pull request #13748 from gschorcht/cpu/esp32/fix_wake_up_sources 
cpu/esp32: fix wake-up sources for sleep modes
 2020-03-29 17:38:54 +02:00
Gunar Schorcht
85b18a1c10 cpu/esp32: fix wake-up sources for sleep modes 
When entering a sleep mode, all wake-up sources should first be disabled before the wake-up sources required for the sleep mode are then stepwise enabled again. Otherwise, an wake-up configuration of one sleep mode may affect the wake-up within another sleep mode.
 2020-03-29 12:55:50 +02:00
benpicco
ad81a88bf0
Merge pull request #13676 from gschorcht/cpu/esp/netopt_channel 
cpu/esp: add NETOPT_CHANNEL for esp_wifi and esp_now
 2020-03-27 16:37:41 +01:00
Alexandre Abadie
42a544bc6a
cpu/stm32l4/wb: ensure LPTIM clock source is correctly reset 2020-03-27 10:57:49 +01:00
Vincent Dupont
08286f7e41
cpu/stm32_common: enable EXTI interrupt for rtt 2020-03-27 10:57:49 +01:00
Alexandre Abadie
c86dcd4611
Merge pull request #10075 from dylad/saml21_dfll_support 
cpu/saml21: add DFLL support
 2020-03-27 10:24:59 +01:00
Gunar Schorcht
42ff700df5
Merge pull request #13728 from maribu/esp32_python3 
cpu/esp_common: Use python3 instead python
 2020-03-26 21:57:14 +01:00
dylad
f2afcd171b cpu/saml21: add DFLL48M support 2020-03-26 18:03:02 +01:00
Marian Buschsieweke
bcaacc8fa5
cpu/esp_common: Use python3 instead python 2020-03-26 15:10:28 +01:00
Gunar Schorcht
f90d230b00 cpu/esp: set NETOPT_CHANNEL for esp_wifi/esp_now 2020-03-26 14:47:41 +01:00
Gunar Schorcht
331313db4f cpu/esp: NETOPT_CHANNEL for esp_wifi and esp_now 2020-03-26 14:46:15 +01:00
Martine S. Lenders
62d48d5bf3
gnrc_netif: document new *_create() out parameter as such 2020-03-26 14:37:44 +01:00
Martine Lenders
061eb88c05
Merge pull request #12994 from jia200x/pr/gnrc_netif_desc_alloc 
gnrc_netif: implementation of dynamic GNRC_NETIF_NUMOF approach
 2020-03-26 14:30:44 +01:00
Jose Alamos
67ed9defbe gnrc_netif_xxx_create: use external netif allocation 2020-03-26 11:12:23 +01:00
Alexandre Abadie
0bb3304df3
native: don't export NATIVEINCLUDES 2020-03-26 10:25:49 +01:00
Leandro Lanzieri
11f4091b94
Merge pull request #13718 from gschorcht/cpu/esp32/dependency_cleanup 
cpu/esp32: use conditional expansion for INCLUDES and esp_eth
 2020-03-26 09:28:47 +01:00
Gunar Schorcht
9b342432c4 cpu/esp32: use conditional expansion for INCLUDES and esp_eth 2020-03-26 01:41:36 +01:00
Francisco Molina
dcd6b7f226
cpu/cc2538/timer: fix GPT enabling wait 2020-03-25 20:16:23 +01:00
Francois Berder
8f1c8298f3 cpu: mips_pic32_common: Use mips32r2_isr_end in timer interrupt handler 
Signed-off-by: Francois Berder <18538310+francois-berder@users.noreply.github.com>
 2020-03-25 19:10:01 +00:00
Francois Berder
7bbf21e2d3 cpu: mips32r2_common: Implement mips32r2_isr_end 
Signed-off-by: Francois Berder <18538310+francois-berder@users.noreply.github.com>
 2020-03-25 19:10:01 +00:00
Francois Berder
cbb0247f26 cpu: mips_pic32_common: Implement pm_reboot 
Signed-off-by: Francois Berder <18538310+francois-berder@users.noreply.github.com>
 2020-03-25 19:10:01 +00:00
Francois Berder
847fedc754 cpu: mips_pic32_common: Handle UHI read 
Signed-off-by: Francois Berder <18538310+francois-berder@users.noreply.github.com>
 2020-03-25 19:10:01 +00:00
Francois Berder
83beabe303 cpu: mips32r2_common: Add missing __isr_vec functions 
This file used to be part of the toolchain (at least in 2016.05-03
version) but is not part of the current MIPS toolchain (2018-09-03).

Signed-off-by: Francois Berder <18538310+francois-berder@users.noreply.github.com>
 2020-03-25 19:10:01 +00:00
Francois Berder
8775254755 cpu: mips_pic32_common: Refactor UART 
Signed-off-by: Francois Berder <18538310+francois-berder@users.noreply.github.com>
 2020-03-25 19:10:01 +00:00
Francois Berder
7979ce57f5 cpu: mips_pic32_common: Define uart_conf_t structure 
Signed-off-by: Francois Berder <18538310+francois-berder@users.noreply.github.com>
 2020-03-25 19:10:01 +00:00
Francois Berder
aeee8f8fba cpu: mips_pic32_common: Define gpio_af enum 
Signed-off-by: Francois Berder <18538310+francois-berder@users.noreply.github.com>
 2020-03-25 19:10:01 +00:00
Francois Berder
535fff26ae cpu: mips: Refactor EIC 
Signed-off-by: Francois Berder <18538310+francois-berder@users.noreply.github.com>
 2020-03-25 19:10:01 +00:00
Francois Berder
f816584213 cpu: mips_pic32_common: Add CPU_FAM macro to CFLAGS 
Signed-off-by: Francois Berder <18538310+francois-berder@users.noreply.github.com>
 2020-03-25 19:10:01 +00:00
Francois Berder
d8a3ac335a cpu: mips_pic32mz: Define CPU_ARCH and CPU_FAM 
Signed-off-by: Francois Berder <18538310+francois-berder@users.noreply.github.com>
 2020-03-25 19:10:01 +00:00
Francois Berder
a06b27ba16 cpu: mips_pic32mx: Define CPU_ARCH and CPU_FAM 
Signed-off-by: Francois Berder <18538310+francois-berder@users.noreply.github.com>
 2020-03-25 19:10:01 +00:00
Benjamin Valentin
77961106f9 cpu/sam0_common: derive ROM_LEN, RAM_LEN from part number & vendor file 
The ROM size is encoded in the part number of the Atmel SAM chips.
RAM size is not encoded directly, so get it by parsing the chip's vendor file.

The file remains in the page cache for the compiler to use, so the overhead
should be minimal:

on master:

  Benchmark #1: make BOARD=samr21-xpro -j
    Time (mean ± σ):     527.9 ms ±   4.9 ms    [User: 503.1 ms, System: 69.6 ms]
    Range (min … max):   519.7 ms … 537.2 ms    10 runs

with this patch:

  Benchmark #1: make BOARD=samr21-xpro -j
    Time (mean ± σ):     535.6 ms ±   4.0 ms    [User: 507.6 ms, System: 75.1 ms]
    Range (min … max):   530.6 ms … 542.0 ms    10 runs
 2020-03-25 15:07:50 +01:00
benpicco
e9b71254ff
Merge pull request #13694 from fjmolinas/pr_boards_common_cc2538 
boards: add common cc2538
 2020-03-25 11:11:50 +01:00
Francisco Molina
c6e0e7adcb
cpu/stm32_common: add common L4 and WB stmclk 2020-03-25 09:29:57 +01:00
Francisco Molina
9fa0099d62
cpu/stm32wb: add flashpage support 
- Since flash access is shared with CPU2 we resize ROM_LEN
  according to CPU2 secure flash memmory area.
- Add assert to prevent unauthorized reads from CPU2 secure
  flash area
 2020-03-25 09:29:56 +01:00
Francisco Molina
66a8922f8c
cpu: initial support for stm32wb 2020-03-25 09:29:56 +01:00
Francisco Molina
0ee04bd6d6
cpu/stm32wb: add stm32wb55xx.h vendor file 2020-03-25 09:28:26 +01:00
Francisco Molina
194af687a0
boards/common: add cc2538 2020-03-25 08:20:52 +01:00
Koos
575a9e9579 cpu/stm: Fix broken character encoding 2020-03-24 16:07:19 +01:00
Kaspar Schleiser
fc6b586919
Merge pull request #13586 from bergzand/pr/nrf/dcdc 
nrf5x: Add and enable configuration for the built-in DC/DC converter
 2020-03-24 11:56:40 +01:00
Gunar Schorcht
c8a2ff2406
Merge pull request #13685 from leandrolanzieri/pr/esp/cleanup_makefile_dep_include 
cpu/esp[32, 8266, _common]: Move dependency resolutions to Makefile.dep
 2020-03-24 11:22:08 +01:00
Leandro Lanzieri
58320c943e
cpu/esp8266: Move common modules fo Makefile.dep 2020-03-24 09:27:40 +01:00
Leandro Lanzieri
afc0ad4d57
cpu/esp_common: Set RIOT_TEST_TIMEOUT with conditional expansion 2020-03-24 09:27:40 +01:00
Leandro Lanzieri
56972af3b4
cpu/esp_common: Don't increase GNRC_NETIF_NUMOF on Makefile 2020-03-24 09:27:30 +01:00
Leandro Lanzieri
939a10813b
cpu/esp_common: Check for esp_spi_ram with conditional expansion 2020-03-24 09:21:23 +01:00
Leandro Lanzieri
fcfc15e199
cpu/esp: Move dependency resolution of esp_log_startup to Makefile.dep 2020-03-24 09:21:21 +01:00
Leandro Lanzieri
e61532efbe
cpu/esp: Move dependency resolution of esp_log_colored to Makefile.dep 2020-03-24 09:21:21 +01:00
Leandro Lanzieri
f918b97ec3
cpu/esp: Move dependency resolution of esp_gdb to Makefile.dep 2020-03-24 09:21:20 +01:00
Leandro Lanzieri
7a30795a8c
cpu/esp: Move esp_[wifi/now] dependency resolution to Makefile.dep 2020-03-24 09:21:20 +01:00
Leandro Lanzieri
ab1f88c69a
cpu/esp: Evaluate esp_[wifi/now] modules with conditional expansion 2020-03-24 09:21:20 +01:00
Leandro Lanzieri
48a62dcc8f
cpu/esp: Move common dependencies to Makefile.dep 2020-03-24 09:21:19 +01:00
Leandro Lanzieri
ea12a6b493
cpu/esp8266/Makefile.include: Check modules in conditional expansion 2020-03-24 09:21:18 +01:00
Leandro Lanzieri
881d245932
cpu/esp32: Evaluate esp_[now/wifi] modules with conditional expansion 2020-03-24 09:21:18 +01:00
Leandro Lanzieri
2f158d7d19
cpu/esp32: Evaluate cpp FEATURE with conditional expansion 2020-03-24 09:21:17 +01:00
benpicco
457c5245ce
Merge pull request #13507 from benpicco/cpu/cc2538-gpio-cycles 
cpu/cc2538: gpio: save a few cycles in handle_isr()
 2020-03-23 20:53:52 +01:00
Leandro Lanzieri
05c37edd42
cpu/esp32: Move default modules to Makefile.dep 2020-03-23 15:49:30 +01:00
Leandro Lanzieri
2b8976d935
cpu/esp32: Use periph_adc_ctrl as feature 2020-03-23 15:47:26 +01:00
Leandro Lanzieri
584d03aae0
cpu/esp32: Remove special module dependency resolution 2020-03-23 15:46:27 +01:00
Leandro Lanzieri
fa419ecf8e
cpu/esp32: Use cpp FEATURE in Makefile.include 2020-03-23 15:46:27 +01:00
Jean Pierre Dudey
ffa5005021
cc26xx_cc13xx: add API to manage peripheral clocks 
Signed-off-by: Jean Pierre Dudey <jeandudey@hotmail.com>
 2020-03-23 09:33:53 -05:00
Jean Pierre Dudey
c6e4768997
cc26xx_cc13xx: add PRCM_NONBUF register bank 
Signed-off-by: Jean Pierre Dudey <jeandudey@hotmail.com>
 2020-03-23 09:33:23 -05:00
Jean Pierre Dudey
7ac28c82b1
cc26x0: enable serial domain only once 
Signed-off-by: Jean Pierre Dudey <jeandudey@hotmail.com>
 2020-03-23 09:33:23 -05:00
Jean Pierre Dudey
4643ed5733
cc26xx_cc13xx: add power abstraction 
Signed-off-by: Jean Pierre Dudey <jeandudey@hotmail.com>
 2020-03-23 09:33:22 -05:00
benpicco
45b635f4c5
Merge pull request #13416 from gschorcht/cpu/esp32/pm_layered 
cpu/esp32: support for light/deep sleep and pm_layered
 2020-03-23 14:11:05 +01:00
benpicco
08afe95572
Merge pull request #13647 from btcven/2020_03_16-new-definitions 
cc26xx_cc13xx: add RF related registers definitions
 2020-03-23 12:48:38 +01:00
Gunar Schorcht
4f977316fe cpu/esp_common: stop WiFi interface before sleep/reboot 
The WiFi interface should be stopped before reboot or sleep. But stopping the WiFi interface disconnects an existing connection. Usually, esp_wifi_netdev tries to reconnect on an disconnect event. However, trying reconnect with a stopped WiFi interface may lead to a crash. Therefore, the stop event has to be handled.
 2020-03-23 12:38:36 +01:00
Gunar Schorcht
09899e4b8d cpu/esp32/periph_gpio: funcs for enter/exit sleep 2020-03-23 12:38:36 +01:00
Gunar Schorcht
f4aa253645 cpu/esp32/periph_rtc: funcs for enter/exit sleep 2020-03-23 12:38:36 +01:00
Gunar Schorcht
dff74a3278 cpu/esp32: add pm_layered support 2020-03-23 12:38:36 +01:00
Gunar Schorcht
5ec4113893 cpu/esp32: several small doc fixes 2020-03-23 12:25:47 +01:00
Gunar Schorcht
a7652df499 cpu/esp32: function to set gpio drive strength 2020-03-23 12:25:47 +01:00
Gunar Schorcht
15ea6feeaf cpu/esp32: use hibernate mode for pm_off 
Now, where the vendor files for light/deep sleep mode are added, function `pm_off` does not need to implement this mode by itself. Instead the existing deep sleep with disabled wakeup sources is used for pm_off.
 2020-03-23 12:25:47 +01:00
Gunar Schorcht
3faf99a894 cpu/esp32: add vendor files for light/deep sleep 2020-03-23 12:25:47 +01:00
Francisco Molina
0cc6a51ea8
cpu/cc2538/periph/timer: cleanup styling 2020-03-23 10:59:53 +01:00
Francisco Molina
7e913fe0d9
cpu/cc2538/periph/timer: set pending timer_set_absolute 
GPT timer needs to be gated to write to TnMATCHR register. If set
when timer is stopped save values and set on next timer_start()
 2020-03-23 10:59:30 +01:00
Francisco Molina
ce696c6caa
cpu/cc2538/timer: enable GPT clock in active, sleep and PM0 2020-03-23 10:58:56 +01:00
Benjamin Valentin
345827ce7b cpu/cc2538: gpio: save a few cycles in handle_isr() 
If only one it is set in state (one GPIO pin caused an interrupt),
don't loop over all 8 bits.

Use clz to get the position of the first interrupt bit and clear it,
looping only as many times as there are actual interrupts.
 2020-03-23 09:21:14 +01:00
Francisco
5ef0cb9c18
Merge pull request #13534 from Ciusss89/stm32l4_can_dev_MASTER 
Add CAN support for nucleo-l476rg
 2020-03-23 09:10:56 +01:00
Gunar Schorcht
2cbf90d9fe cpu/esp32: small fix of rtc_init for light sleep 
`rtc_init` is used after light sleep to update the system time from RTC timer. The fix corrects a small difference of about 230 ms which would sum up with each wakeup from light sleep.
 2020-03-22 23:53:02 +01:00
Gunar Schorcht
825b01e8e1 cpu/esp32: remove gpio_config_sleep_mode func 
The function were used to set the GPIO pads in sleep mode. This function isn't required for deep or light sleep.
 2020-03-22 23:53:02 +01:00
benpicco
921a6a663e
Merge pull request #12024 from gschorcht/cpu/esp32/esp_wifi/wpa2_enterprise 
cpu/esp32/esp wifi: add WPA2 enterprise mode with IEEE 802.1x/EAP authentication
 2020-03-22 17:10:31 +01:00
Giuseppe Tipaldi
7e6ce086b8 cpu: stm32_common: add CAN support for nucleo-l476rg 
STM32L4 CAN implementation:
 - STM32L47x/L48x has single CAN
 - STM32L49x/4Ax has dual CAN
 2020-03-22 16:53:48 +01:00
Gunar Schorcht
c1e6e70015 cpu/esp32/esp_wifi: doc for WPA2 Enterprise mode 2020-03-22 15:47:06 +01:00
benpicco
1e38a3da63
Merge pull request #13673 from fjmolinas/pr_cc2538_cleanups 
cpu/cc2538: clock cleanups
 2020-03-21 22:24:48 +01:00
Francisco Molina
9a2190cd24
cpu/cc2538/periph/pm: unset OSC_PD when running on 32Mhz 
Setting OSC_PD before WFI allows for faster wakeup from sleep.

Wait for cc2538_sys_ctrl_clk_sta and not cc2538_sys_ctrl_clk_ctrl
to be set.
 2020-03-21 19:32:24 +01:00
Francisco Molina
8c35335668
cpu/cc2538/cpu: cleanup clock intialization 2020-03-21 19:32:22 +01:00
benpicco
5aff374f3d
Merge pull request #13670 from gschorcht/cpu/esp8266/add_rtt_based_rtc 
cpu/esp8266: add RTT based RTC
 2020-03-21 13:29:48 +01:00
Gunar Schorcht
b7781c77d6 cpu/esp8266: add RTT based RTC 
fixup! cpu/esp8266: add RTT based RTC
 2020-03-21 08:49:51 +01:00
Marius
aae86e860f
cpu/stm32l4: add support for STM32L412KB 2020-03-20 18:48:31 +01:00
Francisco
b98e4bf0d1
Merge pull request #13658 from fjmolinas/pr_periph_timer_cc2538 
cpu/cc2538: fix GPT3 IRQ definition
 2020-03-20 14:31:05 +01:00
benpicco
829671d504
Merge pull request #13640 from gschorcht/cpu/esp8266/periph_rtt 
cpu/esp8266: add RTT implementation
 2020-03-19 17:42:20 +01:00
Gunar Schorcht
df19c6d1b4
Merge pull request #13519 from benpicco/rtt_rtc 
drivers/rtt_rtc: add RTT based RTC implementation, enable it for cpu/cc2538, nrf5x_common
 2020-03-19 17:18:43 +01:00
Francisco Molina
226e1b5daf
cpu/cc2538: fix GPT3 timer IRQ definition 2020-03-19 16:31:57 +01:00
Benjamin Valentin
f8d61edba0 cpu/nrf5x_common: use RTT based RTC implementation 2020-03-19 15:25:14 +01:00
Benjamin Valentin
f9346e1e2b cpu/cc2538: use RTT based RTC implementation 2020-03-19 15:25:14 +01:00
Gunar Schorcht
4ac8f8df4c
Merge pull request #13646 from benpicco/BACKUP_RAM 
cpu: add BACKUP_RAM attribute
 2020-03-19 15:09:30 +01:00
Gunar Schorcht
464e3a8741 cpu/esp8266: add RTT implementation 2020-03-19 13:59:58 +01:00
Benjamin Valentin
69551d4a74 cpu/lpc2387: define BACKUP_RAM attribute 2020-03-19 13:38:50 +01:00
Benjamin Valentin
b8e18d521f cpu/esp32: define BACKUP_RAM attribute 2020-03-19 13:37:58 +01:00
Benjamin Valentin
a11bcdcd5c cpu/cortexm_common: define BACKUP_RAM attribute 2020-03-19 13:37:58 +01:00
Gunar Schorcht
920d54b226 cpu/esp32/esp_wifi: integrate WPA2 Enterprise mode 2020-03-17 17:51:29 +01:00
Gunar Schorcht
ae647ed95f cpu/esp32/esp_wifi: Makefile integration for WPA2 Enterprise mode 2020-03-17 17:51:29 +01:00
Francisco
d77ecc1cde
Merge pull request #13598 from benpicco/cpu/cc2538-spi-fix 
cpu/cc2538: fix spi_transfer_bytes()
 2020-03-17 17:29:49 +01:00
Jean Pierre Dudey
f1af3ae043
cc26x0: add AON_RTC definitions 
Signed-off-by: Jean Pierre Dudey <jeandudey@hotmail.com>
 2020-03-16 19:36:54 -05:00
Jean Pierre Dudey
1bb689ff45
cc26x2_cc13x2: add AON_RTC definitions 
Signed-off-by: Jean Pierre Dudey <jeandudey@hotmail.com>
 2020-03-16 19:36:54 -05:00
Jean Pierre Dudey
20439cc3cc
cc26xx_cc13xx: add RFC_DBELL/RFC_PWR definitions 
This definition is compatible with `cc26x0` and `cc26x2_cc13x2`.

The only difference is (cc26x0 -> cc26x2_cc13x2):

- IRQ13 -> FG_COMMAND_STARTED
- IRQ12 -> COMMAND_STARTED

Those IRQs aren't used on cc26x0 radio so it shouldn't affect anything.
 2020-03-16 19:36:54 -05:00
Jean Pierre Dudey
ec4fccb3f7
cc26xx_cc13xx: add PERIPH_BASE_NONBUF 
Signed-off-by: Jean Pierre Dudey <jeandudey@hotmail.com>
 2020-03-16 19:30:31 -05:00
Kaspar Schleiser
7be303f12f
Merge pull request #7583 from haukepetersen/add_sam3_rtt 
cpu/sam3: added RTT driver
 2020-03-12 21:30:05 +01:00
Martine Lenders
5defa1ae34
Merge pull request #13466 from gschorcht/fix_compilation_with_ndebug 
tests: fix compilation problems with NDEBUG
 2020-03-12 19:34:33 +01:00
Gunar Schorcht
b7b244b6d9 cpu/stm32_common: fix NDEBUG compile problem 2020-03-12 18:04:42 +01:00
Gunar Schorcht
b2356d29c5 cpu/nrf51: fix NDEBUG compile problem 2020-03-12 18:04:42 +01:00
benpicco
d5c7d28b38
Merge pull request #10745 from kaspar030/make_idle_stacksize_configurable 
cpu: make default idle/main stacksizes configurable on all archs
 2020-03-12 14:38:32 +01:00
Kaspar Schleiser
b0e7d6abd6 cpu/atmega32u4: make THREAD_STACKSIZE_IDLE configurable 2020-03-12 13:35:43 +01:00
Kaspar Schleiser
c86ccfcf67 cpu: esp32: make THREAD_STACKSIZE_IDLE/DEFAULT configurable 2020-03-12 13:01:13 +01:00
Kaspar Schleiser
84745365fd cpu: atmega_common: make THREAD_STACKSIZE_IDLE configurable 2020-03-12 13:01:13 +01:00
Kaspar Schleiser
14ed03074e cpu: lpc2387: make THREAD_STACKSIZE_IDLE configurable 2020-03-12 13:01:13 +01:00
benpicco
5d038a24bf
Merge pull request #13510 from benpicco/cpu/cc2538-pm 
cpu/cc2538: implement periph/pm
 2020-03-12 12:18:18 +01:00
benpicco
52cc02c9a9
Merge pull request #13387 from nmeum/mpu_noexec_ram_ng 
Add optional support for executable space protections
 2020-03-11 20:00:44 +01:00
Hauke Petersen
ea2910e2f4 cpu/sam3: add periph_rtt driver implementation 2020-03-11 12:53:20 +01:00
Hauke Petersen
e5d940fce8 cpu/sam3: add opt to use external 32khz oscillator 2020-03-11 12:53:04 +01:00
Alexandre Abadie
79431878ac
Merge pull request #13051 from dylad/pr/uart_hw_fc 
cpu/uart: create common uart hw fc module
 2020-03-10 16:41:36 +01:00
Dylan Laduranty
0b15db3694 cpu/nrf5x: use generic hw fc module 2020-03-10 14:47:19 +01:00
Dylan Laduranty
3c47911189 cpu/stm32: use generic hw fc module 2020-03-10 14:34:11 +01:00
Dylan Laduranty
8e2227b18b cpu/cc26xx_cc13xx: use generic hw fc module 2020-03-10 14:22:34 +01:00
Dylan Laduranty
077a15f254 cpu/cc2538: use generic hw fc module 2020-03-10 14:22:34 +01:00
Dylan Laduranty
7a095a80d7 cpu/sam0: use generic hw fc module 2020-03-10 14:22:34 +01:00
benpicco
741b9d3b2d
Merge pull request #13603 from ML-PA-Consulting-GmbH/samd21j17d_add 
cpu/sam0_common: add samd21j17d
 2020-03-10 12:00:25 +01:00
Sören Tempel
59676a1f5e Make sure the mpu_noexec_ram regions has the lowest priority 
From the ARMv7-M ARM section B3.5.3:

	Where there is an overlap between two regions, the register with
	the highest region number takes priority.

We want to make sure the mpu_noexec_ram region has the lowest
priority to allow the mpu_stack_guard region to overwrite the first N
bytes of it.

This change fixes using mpu_noexec_ram and mpu_stack_guard together.
 2020-03-10 11:16:22 +01:00
Benjamin Valentin
5d8c00e302 cpu/cc2538: implement periph/pm 
cc2538 implements 4 sleep modes.
In the lightest mode (3) any interrupt source can wake up the CPU.
In mode 2, only RTT, GPIO or USB may wake the CPU.
In mode 1 only RTT and GPIO can wake the CPU.
In mode 0 only GPIO can wake the CPU.

In mode 0 and 1 the lower 16k RAM are lost. This is a problem since those
are usually used by RIOT.

The linkerscripts in cc2538/ldscripts take different approaches towards that.
Some only use the upper 16k and leave the other half to be managed by the
application.

`cc2538sf53.ld` which is used by `openmote-b` uses the entire RAM starting
at the lower half, so it will not be able to wake up from those modes.

A quick fix to test those modes with `tests/periph_pm` would be

--- a/cpu/cc2538/ldscripts/cc2538sf53.ld
+++ b/cpu/cc2538/ldscripts/cc2538sf53.ld
@@ -21,7 +21,7 @@ MEMORY
 {
     rom (rx)    : ORIGIN = 0x00200000, LENGTH = 512K - 44
     cca         : ORIGIN = 0x0027ffd4, LENGTH = 44
-    ram (w!rx)  : ORIGIN = 0x20000000, LENGTH = 32K
+    ram (w!rx)  : ORIGIN = 0x20004000, LENGTH = 16K
 }
 2020-03-10 10:35:46 +01:00
Benjamin Valentin
eb3f515f55 cpu/sam0_common: gpio: Make use of dedicated GPIO interrupts 
saml1x and samd5x have dedicated interrupts per GPIO line.
Use those instead of iterating over the GPIO status bits
to serve IRQs even faster.
 2020-03-10 10:33:31 +01:00
Alexandre Moguilevski
648a5b9c58 cpu/sam0_common: add samd21j17d 2020-03-10 10:26:45 +01:00
Francisco
1b5f22ec2e
Merge pull request #8410 from OTAkeys/pr/fix_stm32f1_boards 
boards: fix CLOCK_PLL_PREDIV on stm32f1-based boards
 2020-03-10 09:35:48 +01:00
Benjamin Valentin
5c4c45fd3f cpu/sam0_common: gpio: add gpio_disable_mux() function 
Inverse to gpio_init_mux()
 2020-03-09 19:23:33 +01:00
Benjamin Valentin
6540609c35 cpu/sam0_common: gpio: save a few cycles in isr_eic() 
Don't iterate over all bits in the GPIO status register, instead
just loop as many times as there are set bits.
 2020-03-09 18:34:06 +01:00
Vincent Dupont
21bbfbed1d stm32_common/stmclk: check if CLOCK_PLL_PREDIV is valid 2020-03-09 18:00:47 +01:00
Benjamin Valentin
80392dc644 cpu/cc2538: spi: unify spi_transfer_bytes() 
Use a common helper function to read/write the data register.
 2020-03-09 16:37:07 +01:00
Benjamin Valentin
68b2c57d2d cpu/cc2538: spi: fix spi_transfer_bytes() with in_buf = NULL 
We have to read the DR for every byte that we write.
Just reading DR while SPI is busy in a loop can lead to bytes being
left in the fifo, corrupting subsequent reads.
 2020-03-09 16:22:37 +01:00
Marian Buschsieweke
e326acfc78
cpu/{stm32r1,stm32_common}: Allow exposing JTAG pins as GPIOs 
- cpu/stm32f1: Removed previous code in gpio_init() to provide PB4 on the
  Nucleo-F103RB only
- cpu/stm32_common: Introduced STM32F1_DISABLE_JTAG which, if defined in
  board.h, exposes the JTAG only pins as GPIOs. This keeps the SWD pins, so that
  SWD debugging remains possible
 2020-03-08 13:05:35 +01:00
Koen Zandberg
64f04e4da9
nrf5x: Add built-in DC/DC converter enable function 
The internal DC/DC converter is more efficient compared to the LDO
regulator.  The downside of the DC/DC converter is that it requires an
external inductor to be present on the board. Enabling the DC/DC
converter is guarded with NRF5X_ENABLE_DCDC, this macro must be defined
if the DC/DC converter is to be enabled.
 2020-03-07 17:37:40 +01:00
Sören Tempel
2c1a627118 Add mpu_noexec_ram pseudomodule 2020-03-07 13:09:55 +01:00
benpicco
7396d05605
Merge pull request #13575 from fjmolinas/pr_cc2538_rf_deps 
cpu/cc2538: handle cc2538_rf deps in Makefile.dep
 2020-03-06 18:00:51 +01:00
Francisco Molina
ff6f6618fb
cpu/cc2538: handle cc2538_rf deps in Makefile.dep 2020-03-06 14:17:19 +01:00
Jose Alamos
3ad574a822 drivers/netdev: use netdev_trigger_event_isr function 2020-03-06 14:03:43 +01:00
Yegor Yefremov
41db161162 doxygen/I2C: don't include overridden typedefs 
Add missing #ifndefs to overridden I2C typedefs for lpc2387 CPU.

Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
 2020-03-05 15:31:06 +01:00
benpicco
681678e3f3
Merge pull request #13537 from jue89/feature/sam0-spi-frequency 
cpu/sam0_common: mitigate rounding errors of SPI baud rate calculation
 2020-03-04 16:50:46 +01:00
Koos
67dfb9d39e cpu/esp8266: Fixed small typo in code example 2020-03-04 09:54:36 +01:00
Alexandre Abadie
68ec8b2c2b
Merge pull request #13391 from kaspar030/mpu_feature 
cpu/cortex-m: turn MPU support into a feature
 2020-03-04 07:09:40 +01:00
benpicco
8e8cfbfe9c
Merge pull request #13516 from gschorcht/cpu/esp/fix_common_cpu_conf 
cpu/esp_common: fixes common CPU configurations
 2020-03-04 00:26:36 +01:00
Kaspar Schleiser
a3c527fdbc cpu/*: add cortex_mpu to known-to-support CPU families 2020-03-03 22:59:41 +01:00
Martine Lenders
e4f27b415e
Merge pull request #13394 from benpicco/atmega-rtc 
cpu/atmega_common: implement emulated RTC support
 2020-03-03 19:03:47 +01:00
benpicco
17659018bf
Merge pull request #13520 from benpicco/rtc_mktime-convert 
cpu/stm32f1: make RTC Y2038 safe
 2020-03-03 17:23:04 +01:00
Benjamin Valentin
93d2068a9e cpu/atmega_common: Implement RTC based on TIM2 
This implements a basic Real Time Clock based on TIM2.

As the timer is too fast and wraps around after just 8 bits, it is
not used directly. Instead TIM2 is responsible for providing a 1 Hz
tick by generating an alarm every second.

The current time data is kept in the `.noinit` section, so it will survive
a reboot, but the clock will not be updated while the bootloader runs, so
expect inaccuracies.
 2020-03-03 16:26:26 +01:00
Gunar Schorcht
9e372104f0
Merge pull request #13284 from benpicco/rtc_mktime 
periph_common/rtc: add rtc_mktime() & rtc_localtime() helper functions for RTC implementations
 2020-03-03 14:12:50 +01:00
Francisco
3f062a78b2
Merge pull request #13045 from aabadie/pr/boards/remote_factorize 
boards/remote*: cleanup and factorize code in peripheral configuration headers
 2020-03-03 13:21:04 +01:00
Juergen Fitschen
0032d35fe8 cpu/sam0_common: mitigate rounding errors of baud rate calculation 
Instead of always rounding up, the driver now rounds to the nearest integer. This reduces the absolut rounding error when setting SPI baud rates.
 2020-03-03 12:32:42 +01:00
benpicco
c6d5cd8872
Merge pull request #13521 from gschorcht/cpu/esp32/add_noinit_section 
cpu/esp32: add .noinit section in linker script
 2020-03-03 11:38:55 +01:00
Benjamin Valentin
1ca26adde8 cpu/esp32: rtc: use rtc_mktime() for Y2038k 
By using a custom EPOCH for the RTC implementation, we can extend the
range of the 32 bit counter based RTC by 118 years.

It also reduces the code size compared to the stdlib based POSIX functions.
 2020-03-03 11:01:02 +01:00
Thomas Stilwell
048fca998b cpu/kinetis: add mkw41z256vht4 to no-hwrng list 2020-03-01 16:56:34 +01:00
Gunar Schorcht
8b61c40fc8 cpu/esp32: add .noinit section to linker script 2020-03-01 11:04:18 +01:00
Gunar Schorcht
b89b4e2259 cpu/esp32: place libc functions in IRAM 2020-03-01 10:55:52 +01:00
Gunar Schorcht
085eb3f40c cpu/esp32: place common CPU functions to IRAM 2020-03-01 10:55:52 +01:00
Gunar Schorcht
0d451969c3 cpu/esp32: place newlib syscalls in IRAM 2020-03-01 10:01:34 +01:00
Benjamin Valentin
33d03e7b3f cpu/stm32f1: make RTC Y2038 safe 
Use rtc_* functions with custom EPOCH.
This buys us about 118 years.
 2020-02-29 17:45:16 +01:00
Gunar Schorcht
33fd259115 cpu/esp: platform heap_stats only used with esp_idf_heap 2020-02-29 12:21:09 +01:00
Gunar Schorcht
ef248b392d cpu/esp_comomon: rename cpu_conf.h to cpu_conf_common.h 
To be able to define common configurations for all ESP CPUs, the CPU specific configuration cpu_conf.h has to include a common configuration. For that purpose cpu_conf.h in cpu/esp_common is renamed to cpu_conf_common.h and included in CPU specific configurations.
 2020-02-29 12:07:12 +01:00
Benjamin Valentin
51fa5afef7 cpu/samd21: default 1kHz clock to same source as 32kHz clock 
The split between GEN2_ULP32K and GEN3_ULP32K was introduced to fix
a failure in tests/periph_wdt when the external oscillator was used.

By not running the external oscillator on demand, the failure can no
longer be observed, so default GEN3_ULP32K to GEN2_ULP32K.
 2020-02-27 16:01:44 +01:00
Benjamin Valentin
2d7bc9e467 cpu/samd21: don't run XOSC32K on demand 
This significantly reduces start-up time.
The XOSC32K is only configured when needed anyway.
 2020-02-27 15:59:10 +01:00
Benjamin Valentin
937c954d92 cpu/lpc2387: implement periph/i2c 
The lpc23xx MCU has up to three I2C interfaces.
This adds a driver for it.
The peripheral works in interrupt mode, each change of the state machine
will generate an interrupt.
The response to the states are laid out in the data sheet.

This replaces the old driver that was removed in c560e28eb6
 2020-02-26 23:41:38 +01:00
Peter Kietzmann
c78962a594
Merge pull request #13487 from JannesVolkens/stm32_eth_mac_filter_fix 
cpu/stm32_common/periph: Fix multicast filtering
 2020-02-26 17:16:08 +01:00
Jannes
1848b0a5c2 cpu/stm32_common/periph: Fix multicast filtering 2020-02-26 15:57:59 +01:00
benpicco
98405fe151
Merge pull request #12380 from benemorius/pr/efm32-uart-init-tx-idle 
cpu/efm32/uart: uart_init(): begin with TX pin at idle level
 2020-02-26 10:23:12 +01:00
benpicco
0edfd13df0
Merge pull request #13310 from benpicco/sam0-exti-common 
cpu/sam0_common: use generic exti_config
 2020-02-26 08:40:49 +01:00
benpicco
99f3f67e67
Merge pull request #13317 from benpicco/arm7-event_thread 
tests/event_threads: remove arch_arm7 from blacklist
 2020-02-26 08:39:00 +01:00
Benjamin Valentin
a0ac2384ac cpu/sam0_common: samr30: add integer literal macros 
All the more recent vendor files have them, so include them for samr30 too.
It is expected for this to become obsolete with the next vendor file update.
 2020-02-25 21:52:24 +01:00
Gunar Schorcht
f688f84a15
Merge pull request #12928 from benpicco/newlib-multiheap 
sys/newlib: enable multiple heaps in _sbrk_r()
 2020-02-25 19:16:42 +01:00
Peter Kietzmann
00d4d365ce
Merge pull request #13383 from JannesVolkens/stm32_eth_mac_filter_fix 
cpu/stm32_common/periph: Fix addr filtering
 2020-02-25 18:03:19 +01:00
benpicco
2b4a8e694a
Merge pull request #13465 from gschorcht/cpu/atmega_common/fix_ndebug_problem 
cpu/atmega_common: fix of compilation problem with NDEBUG
 2020-02-25 11:56:58 +01:00
Alexandre Abadie
ed101a6b92
cpu: remove useless export of TARGET_ARCH 2020-02-25 09:42:11 +01:00
Gunar Schorcht
da244ffcaa cpu/atmega_common: fix compile problem with NDEBUG 2020-02-25 09:41:24 +01:00
Alexandre Abadie
92f2b820cd
cpu: remove exports of UNDEF vars 2020-02-25 09:40:34 +01:00
Benjamin Valentin
442ddc1346 cpu/samd21: Switch EIC clock to slow speed on STANDBY mode 2020-02-24 12:02:27 +01:00
Juergen Fitschen
43ff72ad56 cpu/sam0*: Switch EIC clock to slow speed on STANDBY mode 2020-02-24 12:02:25 +01:00
Juergen Fitschen
1265efc785 cpu/sam0*: Wrap cortexm_sleep call 2020-02-24 11:48:13 +01:00
Juergen Fitschen
ac8a81b8f3 cpu/saml21: disable fast clock if it is not requested 2020-02-24 11:48:13 +01:00