When the SPI peripheral is disabled, the output lines will become HIGH-Z.
If the clk pin is not pulled HIGH or LOW, connected SPI slaves will start drawing current expectedly.
This commit removes a number of assert statements that should already
have been hit before. This is the reason that the assert in the
acquire function is left.
The FCR register content might change during mem-to-mem DMA transfers,
Forcing it back in the acquire should be sufficient to ensure proper
operations.
Since the "EXTI->PR" is an "rc_w1" type of register, we need to be
careful when clearing our interrupt flag in the register. When there
are multiple interrupt flags set in the register, the "|=" operation
will mistakenly clear all pending interrupts instead of just ours.
- On pwm_poweron, the PWM resolution was not restored. (A custom resolution was
only usable if, PWM channel 0 is not used. That configuration is not common,
so this bug was likely never triggered)
- Disabled a work around to prevent flickering:
- Previously, PWM was disconnected on level 0% and 100%
- This increases the run time of `pwm_set()`
- It prevents using the PWM for wave form generation via DDS, as the wave
noticeably jumps when reaching 0% or 100%
- Slightly reduces memory requirements: 2 Bytes of RAM, 112 Bytes of ROM
- Tested with avr-gcc 9.2.0 and LTO enabled
Drop `#include "irq.h"` in `cpu.h`, which was there for a legacy work around.
A bunch of missing includes of `irq.h` materialized due to this and were
fixed.
- Drop duplicated `cpu.c` and `cpu_conf.h`: Those are already provided by
`cpu/atmega_common`.
- The higher values for default stack size of `cpu_conf.h` in
`cpu/atmega_common` results in three tests no longer fitting the available RAM
==> Updated the Makefile.ci to skip linking of those tests for the Arduino
Leonardo
We don't need to define FLASHPAGE_SIZE and FLASHPAGE_NUMOF ourself if
the BPROT peripheral is present.
Now why nrf52840 doesn't have it, I don't know, but for nrf52832 and
nrf23811 the values in BPROT_REGIONS_SIZE and BPROT_REGIONS_NUM match
the values manually provided here before.
__set_PRIMASK(state) had been directly inlined to avoid a hardfault that
occured when branching after waking up from sleep with DBG_STANDBY,
DBG_STOP or DBG_SLEEP set in DBG_CR.
The hardfault occured when returning from the branch to irq_restore,
since the function is now inlined the branch does not happen either.
Refer to #14015 for more details.
irq_% are not inlined by the compiler which leads to it branching
to a function that actually implement a single machine instruction.
Inlining these functions makes the call more efficient as well as
saving some bytes in ROM.
Flashing an ESP board first requires the creation of a flash image from the ELF file. This is realized in the `preflash` target. However, the `preflash` target only depends on the variable `BUILD_BEFORE_FLASH` but on the ELF file. Therefore, the variable `BUILD_BEFORE_FLASH` must be set to the ELF file to ensure that when using multiple make processes, the compilation of the ELF file is completed before the flash image is created.
In #12955 optimization was switched to O2 because with the '-Os'
option, the ESP32 hangs sporadically in 'tests/bench*' if
interrupts where disabled too early by benchmark tests.
Since it hasn't been reproduced since and in #13196 O2 was causing
un-explained hardfaults, since the aforementioned issue could not
be reproduced we switch back to Os by removing O2, as Os will be
used by default.
Writing a 1 bit clears the interrupt flag, writing with |= is thus
uneccecary (and actually an error as this would clear *all* flags).
This cleanup was already done for rtt.c, but rtc.c missed out.
This is needed to switch the SCLK_HF source clock safely.
Note: these functions work on cc26x2_cc13x2 and cc26x0, but special care
needs to be taken when calling on cc26x0 some of these functions, as
ADDI_SEM needs to be taken.
Signed-off-by: Jean Pierre Dudey <jeandudey@hotmail.com>
The sam0 MCUs all have a DAC peripheral.
The DAC has a resulution of 10 or 12 bits and can have one or two
output channels.
The output pins are always hard-wired to PA2 for DAC0 and PA5 for DAC1
if it exists.
On the same54-xpro I would only get a max value of ~1V when using the
internal reference, so I configured it to use an external voltage reference.
The external reference pin is hard-wired to PA3, so you'll have to connect
that to 3.3V to get results.
- Added ADI instruction offsets
- Added register banks and address bases for masked access (writes).
Signed-off-by: Jean Pierre Dudey <jeandudey@hotmail.com>
- Changed "meh" to "Reserved".
- Renamed CTL to CFG to match SDK/TRM name.
- Added constants for VIMS and FLASH necessary to trim registers.
Signed-off-by: Jean Pierre Dudey <jeandudey@hotmail.com>
- Fixes padding.
- Updates documentation.
- Removes documentation longer than 80-chars for the registers values.
Signed-off-by: Jean Pierre Dudey <jeandudey@hotmail.com>
This function is needed to setup the AUX operational mode at startup,
also used for managing low-power states.
Signed-off-by: Jean Pierre Dudey <jeandudey@hotmail.com>
Rename the variable to make it clearer that it refers to the last Makefile
included.
Usually this is the current file, but when another Makefile is included this
changes.
stm32f1 periph_rtc implementation gets a 1s resolution by dividing
CLOCK_LSx by 32768. This only make sense if CLOCK_LSE is set,
otherwise CLOCK_LSI=~40000, which will lead to an imprecise rtc.
lpc23xx has 3 sleep modes and one idle mode.
`PM_NUM_MODES` must only count the idle modes.
In practise, this makes no difference since `mode 3` (IDLE) is
the `default` case in `pm_set()` anyway.
GPIO32 and GPIO33 are used during boot to start an 32.768 kHz XTAL if it is connected to these GPIOs. If the 32.768 kHz XTAL is not connected, these pins can be used digital IO. However, the 32.678 kHz XTAL has to be disabled explicitly in this case. Furthermore, the handling of GPIOs greater than GPIO31 had to be fixed in I2C software implementation.
The calculation of `_state_index` is broken for `port = 2`
_gpio_isr_map[n + (port<<1)];
Will not yield the right result. As a consequence, IRQs on Port 2
are not working.
The right thing here would be
_gpio_isr_map[n + (port ? 32 : 0)];
But we might just re-using the `_isr_map_entry()` function.
Also only iterate as many times as there are set interrupt bits.
The ARM CortexM vector table has some reserved fields which are used by
some manufacturers to store their custom image information. In
particular, NXP QN908X stores the checksum, Code Read Protection, image
type and boot block pointer in this region.
This patch allows the cpu and board modules to define the value of these
fields at build time by defining a macro.
GCLK_ID and APBCMASK entries are not always uniform.
The previous hack would already break for TCC3.
Just explosively write down the cases, there are only 5 at most.
The CPU has 4 hardware timers.
Configuration for all 4 timers exists, but the compile-time range
check has an off-by-one error, causing the last timer to remain
inaccessible.
This commit enables Cortex-M CPU interrupt sub-priorities
and allows the PendSV interrupt to have a priority different
from the default one. Together these two preprocessor
defines can be used to have PendSV always run as the last interrupt
before returning from the interrupt stack back to the user space.
Running PendSV as the last interrupt before returning to the
user space is recommended by ARM, as it increases efficiency.
Furthermore, that change enhances stability a lot with the
new nRF52 SoftDevice support, currently being worked in
PR #9473.
This commit merely enables sub-priorities and a separate
PendSV priority to be used without changing the default
RIOT behaviour.
The DFLL on samd5x has a hardware bug that requires a special
re-enabling sequence when it is disabled and then re-enabled again.
When running the clock on-demand, the hardware handles the disabling
and re-enabling so that sequence does not get executed.
To reproduce, run `tests/periph_uart` on `same54-xpro`.
Without this patch the test will get seemingly stuck on `sleep_test()`.
(In fact it keeps running, but the DFLL has the wrong frequency so the
UART baudrate is wrong).
In this test, on `same54-xpro` only UART0 is sourced from DFLL.
So if the UART is disabled the DFLL will be turned off as well.
Switch from the on-chip LDO to the on-chip buck voltage regulator
when not fast internal oscillators are used.
On `saml21-xpro` with `examples/default` this gives
**before:** 750 µA
** after:** 385 µA
Also adapt the defines to the documentation
- CPUs define up to 4 power modes (from zero, the lowest power mode,
to PM_NUM_MODES-1, the highest)
- >> there is an implicit extra idle mode (which has the number PM_NUM_MODES) <<
Previously on saml21 this would always generate pm_set(3) which is an illegal state.
Now pm_layered will correctly generate pm_set(2) for IDLE modes.
Idle power consumption dropped from 750µA to 368µA and wake-up from standby is also
possible. (Before it would just enter STANDBY again as the mode register was never
written with the illegal value.)
When a previously disabled DFLL gets enabled again, the frequency will
be incorrect. Follow the procedure outlined in the errata sheet, section 2.8.3
to work around the issue.
This fixes wake from standby.
This adds cortexm_fpu to the DEFAULT_MODULE list when the feature
cortexm_fpu is provided by the architecture. It also moves the
dependency resolution of this module to the architecture-specific
Makefile.dep file.
This moves the following modules to a architecture-specific Makefile.dep
file:
- cortexm_common
- cortexm_common_periph
- newlib
- newlib_nano
- periph
Add a fucntion to switch between LDO and Buck concerter to provide the
internal CPU voltage.
The Buck Converter is not compatible with internal fast oscillators (DFLL, DPLL)
and requires an inductivity to be present on the board.
When changing the clock configuration while the RTC is running, the
RTC may end up in an undefined state that leaves it unresponsive.
The RTC is not reset to stay persistent across reboots/hibernate, so
it will not be reset on init.
Instead, disable the RTC while configuring the clocks, rtc_init() will
take care of re-enabling it.
@dylad introduced this workaround for saml21, samd5x needs it too.
To reproduce, set the CLOCK_CORECLOCK of a samd5x board (e.g. same54-xpro)
to 48 MHz.
Run any RTC application. The CPU will be stuck in _wait_syncbusy() after
a reboot.
This patch will fix this. (You will need to power-cycle the board if the
RTC has entered the stuck state as it will never be reset.)
Due to stability reasons, the SoftAP interface of the WiFi module was always enabled in former versions even if only the station interface was used. Therefore the WiFi modem had to be always active and the SoC could not enter the modem sleep mode. Therefore, the SoftAP interface is only enabled when ESP-NOW is used.
When entering a sleep mode, all wake-up sources should first be disabled before the wake-up sources required for the sleep mode are then stepwise enabled again. Otherwise, an wake-up configuration of one sleep mode may affect the wake-up within another sleep mode.
