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Merge pull request #14021 from aabadie/pr/cpu/stm32_unique
cpu/stm32: refactor to use a single directory
This commit is contained in:
GitHub
commit
767329ef25
@ -1,4 +1,4 @@
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CPU = stm32l0
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CPU = stm32
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CPU_MODEL = stm32l072cz
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# Put defined MCU peripherals here (in alphabetical order)
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@ -1,4 +1,4 @@
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CPU = stm32l4
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CPU = stm32
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CPU_MODEL = stm32l475vg
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# Put defined MCU peripherals here (in alphabetical order)
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@ -1,4 +1,4 @@
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CPU = stm32f1
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CPU = stm32
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# Put defined MCU peripherals here (in alphabetical order)
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FEATURES_PROVIDED += periph_adc
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@ -1,4 +1,4 @@
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CPU = stm32f1
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CPU = stm32
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CPU_MODEL = stm32f103re
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# Put defined MCU peripherals here (in alphabetical order)
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@ -1,4 +1,4 @@
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CPU = stm32f4
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CPU = stm32
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CPU_MODEL = stm32f415rg
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@ -1,4 +1,4 @@
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CPU = stm32f1
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CPU = stm32
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CPU_MODEL = stm32f103re
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# Put defined MCU peripherals here (in alphabetical order)
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@ -1,4 +1,4 @@
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CPU = stm32l0
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CPU = stm32
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CPU_MODEL = stm32l052t8
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# Put defined MCU peripherals here (in alphabetical order)
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@ -1,5 +1,5 @@
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## the cpu to build for
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CPU = stm32l1
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CPU = stm32
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CPU_MODEL = stm32l151cb
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# Put defined MCU peripherals here (in alphabetical order)
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@ -1,4 +1,4 @@
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CPU = stm32l1
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CPU = stm32
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CPU_MODEL = stm32l151rc
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# Put defined MCU peripherals here (in alphabetical order)
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@ -1,4 +1,4 @@
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CPU = stm32l1
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CPU = stm32
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CPU_MODEL = stm32l151cb_a
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# Put defined MCU peripherals here (in alphabetical order)
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@ -1,4 +1,4 @@
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CPU = stm32l0
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CPU = stm32
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CPU_MODEL = stm32l072cz
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# Put defined MCU peripherals here (in alphabetical order)
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@ -1,4 +1,4 @@
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CPU = stm32f1
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CPU = stm32
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CPU_MODEL = stm32f103cb
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# Put defined MCU peripherals here (in alphabetical order)
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@ -1,4 +1,4 @@
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CPU = stm32f4
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CPU = stm32
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CPU_MODEL = stm32f415rg
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# Put defined MCU peripherals here (in alphabetical order)
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@ -1,4 +1,4 @@
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CPU = stm32f0
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CPU = stm32
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CPU_MODEL = stm32f030r8
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# Put defined MCU peripherals here (in alphabetical order)
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@ -1,4 +1,4 @@
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CPU = stm32f0
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CPU = stm32
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CPU_MODEL = stm32f031k6
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# Put defined MCU peripherals here (in alphabetical order)
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@ -1,4 +1,4 @@
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CPU = stm32f0
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CPU = stm32
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CPU_MODEL = stm32f042k6
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# Put defined MCU peripherals here (in alphabetical order)
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@ -1,4 +1,4 @@
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CPU = stm32f0
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CPU = stm32
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CPU_MODEL = stm32f070rb
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# Put defined MCU peripherals here (in alphabetical order)
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@ -1,4 +1,4 @@
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CPU = stm32f0
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CPU = stm32
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CPU_MODEL = stm32f072rb
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# Put defined MCU peripherals here (in alphabetical order)
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@ -1,4 +1,4 @@
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CPU = stm32f0
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CPU = stm32
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CPU_MODEL = stm32f091rc
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# Put defined MCU peripherals here (in alphabetical order)
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@ -1,4 +1,4 @@
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CPU = stm32f1
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CPU = stm32
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CPU_MODEL = stm32f103rb
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# Put defined MCU peripherals here (in alphabetical order)
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@ -1,4 +1,4 @@
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CPU = stm32f2
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CPU = stm32
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CPU_MODEL = stm32f207zg
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# Put defined MCU peripherals here (in alphabetical order)
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@ -1,4 +1,4 @@
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CPU = stm32f3
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CPU = stm32
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CPU_MODEL = stm32f302r8
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# Put defined MCU peripherals here (in alphabetical order)
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@ -1,4 +1,4 @@
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CPU = stm32f3
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CPU = stm32
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CPU_MODEL = stm32f303k8
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# Put defined MCU peripherals here (in alphabetical order)
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@ -1,4 +1,4 @@
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CPU = stm32f3
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CPU = stm32
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CPU_MODEL = stm32f303re
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# Put defined MCU peripherals here (in alphabetical order)
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@ -1,4 +1,4 @@
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CPU = stm32f3
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CPU = stm32
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CPU_MODEL = stm32f303ze
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# Put defined MCU peripherals here (in alphabetical order)
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@ -1,4 +1,4 @@
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CPU = stm32f3
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CPU = stm32
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CPU_MODEL = stm32f334r8
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# Put defined MCU peripherals here (in alphabetical order)
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@ -1,4 +1,4 @@
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CPU = stm32f4
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CPU = stm32
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CPU_MODEL = stm32f401re
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# Put defined MCU peripherals here (in alphabetical order)
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@ -1,4 +1,4 @@
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CPU = stm32f4
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CPU = stm32
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CPU_MODEL = stm32f410rb
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# Put defined MCU peripherals here (in alphabetical order)
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@ -1,4 +1,4 @@
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CPU = stm32f4
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CPU = stm32
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CPU_MODEL = stm32f411re
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# Put defined MCU peripherals here (in alphabetical order)
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@ -1,4 +1,4 @@
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CPU = stm32f4
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CPU = stm32
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CPU_MODEL = stm32f412zg
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# Put defined MCU peripherals here (in alphabetical order)
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@ -1,4 +1,4 @@
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CPU = stm32f4
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CPU = stm32
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CPU_MODEL = stm32f413zh
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# Put defined MCU peripherals here (in alphabetical order)
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@ -1,4 +1,4 @@
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CPU = stm32f4
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CPU = stm32
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CPU_MODEL = stm32f429zi
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# Put defined MCU peripherals here (in alphabetical order)
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@ -1,4 +1,4 @@
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CPU = stm32f4
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CPU = stm32
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CPU_MODEL = stm32f446re
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# Put defined MCU peripherals here (in alphabetical order)
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@ -1,4 +1,4 @@
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CPU = stm32f4
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CPU = stm32
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CPU_MODEL = stm32f446ze
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# Put defined MCU peripherals here (in alphabetical order)
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@ -1,4 +1,4 @@
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CPU = stm32f7
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CPU = stm32
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CPU_MODEL = stm32f722ze
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# Put defined MCU peripherals here (in alphabetical order)
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@ -1,4 +1,4 @@
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CPU = stm32f7
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CPU = stm32
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CPU_MODEL = stm32f746zg
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# Put defined MCU peripherals here (in alphabetical order)
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@ -1,4 +1,4 @@
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CPU = stm32f7
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CPU = stm32
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CPU_MODEL = stm32f767zi
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# Put defined MCU peripherals here (in alphabetical order)
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@ -1,4 +1,4 @@
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CPU = stm32l0
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CPU = stm32
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CPU_MODEL = stm32l031k6
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# Put defined MCU peripherals here (in alphabetical order)
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@ -1,4 +1,4 @@
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CPU = stm32l0
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CPU = stm32
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CPU_MODEL = stm32l053r8
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# Put defined MCU peripherals here (in alphabetical order)
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@ -1,4 +1,4 @@
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CPU = stm32l0
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CPU = stm32
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CPU_MODEL = stm32l073rz
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# Put defined MCU peripherals here (in alphabetical order)
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@ -1,4 +1,4 @@
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CPU = stm32l1
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CPU = stm32
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CPU_MODEL = stm32l152re
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# Put defined MCU peripherals here (in alphabetical order)
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@ -1,4 +1,4 @@
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CPU = stm32l4
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CPU = stm32
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CPU_MODEL = stm32l412kb
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# Put defined MCU peripherals here (in alphabetical order)
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@ -1,4 +1,4 @@
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CPU = stm32l4
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CPU = stm32
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CPU_MODEL = stm32l432kc
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# Put defined MCU peripherals here (in alphabetical order)
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@ -1,4 +1,4 @@
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CPU = stm32l4
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CPU = stm32
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CPU_MODEL = stm32l433rc
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# Put defined MCU peripherals here (in alphabetical order)
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@ -1,4 +1,4 @@
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CPU = stm32l4
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CPU = stm32
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CPU_MODEL = stm32l452re
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# Put defined MCU peripherals here (in alphabetical order)
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@ -1,4 +1,4 @@
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CPU = stm32l4
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CPU = stm32
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CPU_MODEL = stm32l476rg
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# Put defined MCU peripherals here (in alphabetical order)
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@ -1,4 +1,4 @@
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CPU = stm32l4
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CPU = stm32
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CPU_MODEL = stm32l496zg
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# Put defined MCU peripherals here (in alphabetical order)
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@ -1,4 +1,4 @@
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CPU = stm32l4
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CPU = stm32
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CPU_MODEL = stm32l4r5zi
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# Put defined MCU peripherals here (in alphabetical order)
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@ -1,4 +1,4 @@
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CPU = stm32l1
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CPU = stm32
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CPU_MODEL = stm32l151rc
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# Put defined MCU peripherals here (in alphabetical order)
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@ -1,4 +1,4 @@
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CPU = stm32f1
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CPU = stm32
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CPU_MODEL = stm32f103rb
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|
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# Put defined MCU peripherals here (in alphabetical order)
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|
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@ -1,4 +1,4 @@
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CPU = stm32f1
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CPU = stm32
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CPU_MODEL = stm32f103cb
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# Put defined MCU peripherals here (in alphabetical order)
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|
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@ -1,5 +1,5 @@
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# the cpu to build for
|
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CPU = stm32l4
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CPU = stm32
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CPU_MODEL = stm32l496ag
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|
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# Put defined MCU peripherals here (in alphabetical order)
|
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|
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@ -1,5 +1,5 @@
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## the cpu to build for
|
||||
CPU = stm32wb
|
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CPU = stm32
|
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CPU_MODEL = stm32wb55rg
|
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|
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# Put defined MCU peripherals here (in alphabetical order)
|
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|
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@ -1,4 +1,4 @@
|
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CPU = stm32f4
|
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CPU = stm32
|
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CPU_MODEL = stm32f405rg
|
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|
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# Put defined MCU peripherals here (in alphabetical order)
|
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|
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@ -1,4 +1,4 @@
|
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CPU = stm32f1
|
||||
CPU = stm32
|
||||
CPU_MODEL = stm32f103cb
|
||||
|
||||
# Put defined MCU peripherals here (in alphabetical order)
|
||||
|
||||
@ -1,4 +1,4 @@
|
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CPU = stm32f0
|
||||
CPU = stm32
|
||||
CPU_MODEL = stm32f030f4
|
||||
|
||||
# Put defined MCU peripherals here (in alphabetical order)
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
CPU = stm32f0
|
||||
CPU = stm32
|
||||
CPU_MODEL = stm32f051r8
|
||||
|
||||
# Put defined MCU peripherals here (in alphabetical order)
|
||||
|
||||
@ -1,4 +1,4 @@
|
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CPU = stm32f3
|
||||
CPU = stm32
|
||||
CPU_MODEL = stm32f303vc
|
||||
|
||||
# Put defined MCU peripherals here (in alphabetical order)
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
CPU = stm32f4
|
||||
CPU = stm32
|
||||
CPU_MODEL = stm32f429zi
|
||||
|
||||
# Put defined MCU peripherals here (in alphabetical order)
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
CPU = stm32f4
|
||||
CPU = stm32
|
||||
CPU_MODEL = stm32f407vg
|
||||
|
||||
# Put defined MCU peripherals here (in alphabetical order)
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
# define the cpu used by the stm32f723e-disco board
|
||||
CPU = stm32f7
|
||||
CPU = stm32
|
||||
CPU_MODEL = stm32f723ie
|
||||
|
||||
# Put defined MCU peripherals here (in alphabetical order)
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
CPU = stm32f7
|
||||
CPU = stm32
|
||||
CPU_MODEL = stm32f769ni
|
||||
|
||||
# Put defined MCU peripherals here (in alphabetical order)
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
CPU = stm32l0
|
||||
CPU = stm32
|
||||
CPU_MODEL = stm32l053c8
|
||||
|
||||
# Put defined MCU peripherals here (in alphabetical order)
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
CPU = stm32l4
|
||||
CPU = stm32
|
||||
CPU_MODEL = stm32l476vg
|
||||
|
||||
# Put defined MCU peripherals here (in alphabetical order)
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
CPU = stm32f4
|
||||
CPU = stm32
|
||||
CPU_MODEL = stm32f437vg
|
||||
|
||||
# Put defined MCU peripherals here (in alphabetical order)
|
||||
|
||||
5
cpu/stm32/Makefile
Normal file
5
cpu/stm32/Makefile
Normal file
@ -0,0 +1,5 @@
|
||||
MODULE = cpu
|
||||
|
||||
DIRS = $(RIOTCPU)/cortexm_common periph vectors
|
||||
|
||||
include $(RIOTBASE)/Makefile.base
|
||||
@ -1,8 +1,8 @@
|
||||
# All stm32 families provide pm support
|
||||
USEMODULE += pm_layered
|
||||
|
||||
# include stm32 common functions and stm32 common periph drivers
|
||||
USEMODULE += stm32_common stm32_common_periph
|
||||
# include stm32 common periph drivers
|
||||
USEMODULE += periph stm32_vectors
|
||||
|
||||
ifneq (,$(filter periph_usbdev,$(FEATURES_USED)))
|
||||
USEMODULE += xtimer
|
||||
55
cpu/stm32/Makefile.features
Normal file
55
cpu/stm32/Makefile.features
Normal file
@ -0,0 +1,55 @@
|
||||
include $(RIOTCPU)/stm32/stm32_info.mk
|
||||
|
||||
FEATURES_PROVIDED += cpu_$(CPU_FAM)
|
||||
FEATURES_PROVIDED += periph_cpuid
|
||||
FEATURES_PROVIDED += periph_gpio periph_gpio_irq
|
||||
FEATURES_PROVIDED += puf_sram
|
||||
FEATURES_PROVIDED += periph_uart_modecfg
|
||||
FEATURES_PROVIDED += periph_wdt
|
||||
|
||||
ifneq (,$(filter $(CPU_FAM),stm32f0 stm32f1 stm32f3 stm32l0 stm32l1 stm32l4 stm32wb))
|
||||
ifeq (,$(filter nucleo-f031k6,$(BOARD)))
|
||||
FEATURES_PROVIDED += periph_flashpage
|
||||
FEATURES_PROVIDED += periph_flashpage_raw
|
||||
endif
|
||||
endif
|
||||
|
||||
ifneq (,$(filter $(CPU_FAM),stm32l0 stm32l1))
|
||||
FEATURES_PROVIDED += periph_eeprom
|
||||
endif
|
||||
|
||||
ifeq (stm32f1,$(CPU_FAM))
|
||||
FEATURES_CONFLICT += periph_rtc:periph_rtt
|
||||
FEATURES_CONFLICT_MSG += "On the STM32F1, the RTC and RTT map to the same hardware peripheral."
|
||||
endif
|
||||
|
||||
ifneq (,$(filter $(CPU_FAM),stm32f2 stm32f4 stm32f7 stm32l0 stm32l4 stm32wb))
|
||||
FEATURES_PROVIDED += periph_hwrng
|
||||
endif
|
||||
|
||||
# the granularity of provided feature definition for STMs is currently by CPU
|
||||
# sub-family (e.g., stm32f[1234]). Unfortunately, only some of e.g., the
|
||||
# stm32f4 have an RNG peripheral. As during evaluation of the features , no
|
||||
# CPU variable is available, we need to filter by board.
|
||||
#
|
||||
BOARDS_WITHOUT_HWRNG += nucleo-f401re
|
||||
BOARDS_WITHOUT_HWRNG += nucleo-f411re
|
||||
BOARDS_WITHOUT_HWRNG += nucleo-f446re
|
||||
BOARDS_WITHOUT_HWRNG += nucleo-f446ze
|
||||
BOARDS_WITHOUT_HWRNG += nucleo-l031k6
|
||||
|
||||
ifneq (,$(filter $(BOARDS_WITHOUT_HWRNG),$(BOARD)))
|
||||
FEATURES_PROVIDED := $(filter-out periph_hwrng,$(FEATURES_PROVIDED))
|
||||
endif
|
||||
|
||||
ifneq (,$(filter $(CPU_FAM),stm32f2 stm32f4 stm32f7 stm32l1 stm32l4))
|
||||
FEATURES_PROVIDED += cortexm_mpu
|
||||
endif
|
||||
|
||||
# only some stm32f3 and stm32l0 have an MPU
|
||||
STM32_WITH_MPU += stm32f303re stm32f303vc stm32f303ze stm32l052t8
|
||||
ifneq (,$(filter $(CPU_MODEL),$(STM32_WITH_MPU)))
|
||||
FEATURES_PROVIDED += cortexm_mpu
|
||||
endif
|
||||
|
||||
include $(RIOTCPU)/cortexm_common/Makefile.features
|
||||
@ -1,13 +1,13 @@
|
||||
CFLAGS += -DCPU_FAM_$(call uppercase_and_underscore,$(CPU_FAM))
|
||||
|
||||
# For stm32 cpu's we use the stm32_common.ld linker script
|
||||
LINKFLAGS += -L$(RIOTCPU)/stm32_common/ldscripts
|
||||
LINKER_SCRIPT ?= stm32_common.ld
|
||||
# For stm32 cpu's we use the generic stm32.ld linker script
|
||||
LINKER_SCRIPT ?= stm32.ld
|
||||
|
||||
INCLUDES += -I$(RIOTCPU)/stm32_common/include
|
||||
# Include riotboot specific variables
|
||||
include $(RIOTCPU)/stm32/stm32_riotboot.mk
|
||||
|
||||
# Compute ROM_LEN and RAM_LEN
|
||||
include $(RIOTCPU)/stm32_common/stm32_mem_lengths.mk
|
||||
include $(RIOTCPU)/stm32/stm32_mem_lengths.mk
|
||||
KB := 1024
|
||||
ROM_LEN_K := $(shell echo $(ROM_LEN) | sed 's/K//')
|
||||
|
||||
@ -25,7 +25,7 @@ else
|
||||
endif
|
||||
|
||||
# Get CPU_LINE_ variable
|
||||
-include $(RIOTCPU)/$(CPU)/stm32_line.mk
|
||||
include $(RIOTCPU)/stm32/stm32_line.mk
|
||||
CPU_LINE ?= $(shell echo $(CPU_MODEL) | cut -c -9 | tr 'a-z-' 'A-Z_')xx
|
||||
|
||||
# Set CFLAGS
|
||||
@ -35,10 +35,14 @@ CFLAGS += -DSTM32_FLASHSIZE=$(FLASHSIZE)U
|
||||
info-stm32:
|
||||
@$(COLOR_ECHO) "CPU: $(CPU_MODEL)"
|
||||
@$(COLOR_ECHO) "\tLine: $(CPU_LINE)"
|
||||
@$(COLOR_ECHO) "\tPin count:\t$(STM32_PINCOUNT)"
|
||||
@$(COLOR_ECHO) "\tPin count:\t$(STM32_PINS)"
|
||||
@$(COLOR_ECHO) "\tROM size:\t$(ROM_LEN) ($(FLASHSIZE) Bytes)"
|
||||
@$(COLOR_ECHO) "\tRAM size:\t$(RAM_LEN)"
|
||||
|
||||
ifneq (,$(CCMRAM_LEN))
|
||||
LINKFLAGS += $(LINKFLAGPREFIX)--defsym=_ccmram_length=$(CCMRAM_LEN)
|
||||
endif
|
||||
|
||||
VECTORS_O ?= $(BINDIR)/stm32_vectors/vectors_$(subst stm32,,$(CPU_FAM)).o
|
||||
|
||||
include $(RIOTMAKE)/arch/cortexm.inc.mk
|
||||
@ -7,7 +7,7 @@
|
||||
*/
|
||||
|
||||
/**
|
||||
* @ingroup cpu_cortexm_common
|
||||
* @ingroup cpu_stm32
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
@ -19,7 +19,7 @@
|
||||
*/
|
||||
|
||||
#include "periph_conf.h"
|
||||
#include "periph_cpu_common.h"
|
||||
#include "periph_cpu.h"
|
||||
|
||||
#define ENABLE_DEBUG (0)
|
||||
#include "debug.h"
|
||||
@ -12,7 +12,7 @@
|
||||
*/
|
||||
|
||||
/**
|
||||
* @ingroup cpu_stm32_common
|
||||
* @ingroup cpu_stm32
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
2
cpu/stm32/dist/.gitignore
vendored
Normal file
2
cpu/stm32/dist/.gitignore
vendored
Normal file
@ -0,0 +1,2 @@
|
||||
clk_conf/clk_conf
|
||||
spi_divtable/spi_divtable
|
||||
@ -22,6 +22,7 @@
|
||||
#include <stdlib.h>
|
||||
#include <stdio.h>
|
||||
|
||||
#define ARRAY_SIZE(a) (sizeof((a)) / sizeof((a)[0]))
|
||||
|
||||
static int targets[] = { 100000, 400000, 1000000, 5000000, 10000000 };
|
||||
|
||||
@ -1,15 +1,13 @@
|
||||
/**
|
||||
* @defgroup cpu_stm32_common STM32 common
|
||||
* @defgroup cpu_stm32 STM32
|
||||
* @ingroup cpu
|
||||
* @brief STM32 common code and definitions
|
||||
* @brief All STM32 families code and definitions
|
||||
*
|
||||
* This module contains all common code and definition to all STM32 cpu
|
||||
* families supported by RIOT: @ref cpu_stm32f0, @ref cpu_stm32l0,
|
||||
* @ref cpu_stm32f1, @ref cpu_stm32f2, @ref cpu_stm32f3, @ref cpu_stm32f4,
|
||||
* @ref cpu_stm32l4, @ref cpu_stm32f7.
|
||||
* This module contains all code and definition to all STM32 cpu
|
||||
* families supported by RIOT: F0, F1, F2, F3, F4, F7, L0, L4 and WB.
|
||||
*
|
||||
* STM32Fx Clock configuration
|
||||
* =================================
|
||||
* ===========================
|
||||
*
|
||||
* stm32fx cpus share clock configuration code and macro.
|
||||
* It can be configured as described here.
|
||||
@ -7,7 +7,7 @@
|
||||
*/
|
||||
|
||||
/**
|
||||
* @ingroup cpu_stm32_common
|
||||
* @ingroup cpu_stm32
|
||||
* @ingroup drivers_can
|
||||
* @defgroup candev_stm32 STM32 CAN controller
|
||||
* @brief STM32 CAN controller driver (bxCAN)
|
||||
169
cpu/stm32/include/cpu_conf.h
Normal file
169
cpu/stm32/include/cpu_conf.h
Normal file
@ -0,0 +1,169 @@
|
||||
/*
|
||||
* Copyright (C) 2016 Freie Universität Berlin
|
||||
* 2016 Inria
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser General
|
||||
* Public License v2.1. See the file LICENSE in the top level directory for more
|
||||
* details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @ingroup cpu_stm32
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief Implementation specific CPU configuration options
|
||||
*
|
||||
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
|
||||
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
|
||||
*/
|
||||
|
||||
#ifndef CPU_CONF_H
|
||||
#define CPU_CONF_H
|
||||
|
||||
#include "cpu_conf_common.h"
|
||||
|
||||
#if CPU_FAM_STM32F0
|
||||
#include "vendor/stm32f0xx.h"
|
||||
#elif CPU_FAM_STM32F1
|
||||
#include "vendor/stm32f1xx.h"
|
||||
#elif CPU_FAM_STM32F2
|
||||
#include "vendor/stm32f2xx.h"
|
||||
#elif CPU_FAM_STM32F3
|
||||
#include "vendor/stm32f3xx.h"
|
||||
#elif CPU_FAM_STM32F4
|
||||
#include "vendor/stm32f4xx.h"
|
||||
#elif CPU_FAM_STM32F7
|
||||
#include "vendor/stm32f7xx.h"
|
||||
#elif CPU_FAM_STM32L0
|
||||
#include "vendor/stm32l0xx.h"
|
||||
#elif CPU_FAM_STM32L1
|
||||
#include "vendor/stm32l1xx.h"
|
||||
#elif CPU_FAM_STM32L4
|
||||
#include "vendor/stm32l4xx.h"
|
||||
#elif CPU_FAM_STM32WB
|
||||
#include "vendor/stm32wbxx.h"
|
||||
#else
|
||||
#error Not supported CPU family
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief ARM Cortex-M specific CPU configuration
|
||||
* @{
|
||||
*/
|
||||
#define CPU_DEFAULT_IRQ_PRIO (1U)
|
||||
#if defined(CPU_LINE_STM32F030x8)
|
||||
#define CPU_IRQ_NUMOF (29U)
|
||||
#elif defined(CPU_LINE_STM32F031x6) || defined(CPU_LINE_STM32F030x4)
|
||||
#define CPU_IRQ_NUMOF (28U)
|
||||
#elif defined(CPU_LINE_STM32F051x8) || defined(CPU_LINE_STM32F091xC)
|
||||
#define CPU_IRQ_NUMOF (31U)
|
||||
#elif defined (CPU_FAM_STM32F0)
|
||||
#define CPU_IRQ_NUMOF (32U)
|
||||
#elif defined(CPU_LINE_STM32F103xE)
|
||||
#define CPU_IRQ_NUMOF (60U)
|
||||
#elif defined (CPU_FAM_STM32F1)
|
||||
#define CPU_IRQ_NUMOF (43U)
|
||||
#elif defined (CPU_FAM_STM32F2)
|
||||
#define CPU_IRQ_NUMOF (81U)
|
||||
#elif defined(CPU_LINE_STM32F303xE)
|
||||
#define CPU_IRQ_NUMOF (85U)
|
||||
#elif defined(CPU_FAM_STM32F3)
|
||||
#define CPU_IRQ_NUMOF (82U)
|
||||
#elif defined(CPU_LINE_STM32F401xE)
|
||||
#define CPU_IRQ_NUMOF (85U)
|
||||
#elif defined(CPU_LINE_STM32F405xx) || defined(CPU_LINE_STM32F407xx) \
|
||||
|| defined(CPU_LINE_STM32F415xx)
|
||||
#define CPU_IRQ_NUMOF (82U)
|
||||
#elif defined(CPU_LINE_STM32F410Rx)
|
||||
#define CPU_IRQ_NUMOF (98U)
|
||||
#elif defined(CPU_LINE_STM32F411xE)
|
||||
#define CPU_IRQ_NUMOF (86U)
|
||||
#elif defined(CPU_LINE_STM32F412Zx) || defined(CPU_LINE_STM32F446xx)
|
||||
#define CPU_IRQ_NUMOF (97U)
|
||||
#elif defined(CPU_LINE_STM32F413xx) || defined(CPU_LINE_STM32F423xx)
|
||||
#define CPU_IRQ_NUMOF (102U)
|
||||
#elif defined(CPU_LINE_STM32F429xx) || defined(CPU_LINE_STM32F437xx)
|
||||
#define CPU_IRQ_NUMOF (91U)
|
||||
#elif defined(CPU_LINE_STM32F746xx)
|
||||
#define CPU_IRQ_NUMOF (98U)
|
||||
#elif defined(CPU_LINE_STM32F767xx) || defined(CPU_LINE_STM32F769xx)
|
||||
#define CPU_IRQ_NUMOF (110U)
|
||||
#elif defined(CPU_LINE_STM32F722xx) || defined(CPU_LINE_STM32F723xx)
|
||||
#define CPU_IRQ_NUMOF (104U)
|
||||
#elif defined(CPU_LINE_STM32L031xx)
|
||||
#define CPU_IRQ_NUMOF (30U)
|
||||
#elif defined(CPU_FAM_STM32L0)
|
||||
#define CPU_IRQ_NUMOF (32U)
|
||||
#elif defined(CPU_MODEL_STM32L151RB_A) || defined(CPU_MODEL_STM32L151CB) || \
|
||||
defined(CPU_MODEL_STM32L151CB_A)
|
||||
#define CPU_IRQ_NUMOF (45U)
|
||||
#elif defined(CPU_FAM_STM32L1)
|
||||
#define CPU_IRQ_NUMOF (57U)
|
||||
#elif defined(CPU_MODEL_STM32L432KC) || defined(CPU_MODEL_STM32L433RC)
|
||||
#define CPU_IRQ_NUMOF (83U)
|
||||
#elif defined(CPU_MODEL_STM32L496ZG) || defined(CPU_MODEL_STM32L496AG)
|
||||
#define CPU_IRQ_NUMOF (91U)
|
||||
#elif defined(CPU_MODEL_STM32L4R5ZI)
|
||||
#define CPU_IRQ_NUMOF (95U)
|
||||
#elif defined(CPU_FAM_STM32L4)
|
||||
#define CPU_IRQ_NUMOF (82U)
|
||||
#elif defined(CPU_MODEL_STM32WB55RG)
|
||||
#define CPU_IRQ_NUMOF (63U)
|
||||
#else
|
||||
#error Number of IRQs not configured for this CPU
|
||||
#endif
|
||||
#define CPU_FLASH_BASE FLASH_BASE
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @brief Flash page configuration
|
||||
* @{
|
||||
*/
|
||||
#if defined(CPU_FAM_STM32WB)
|
||||
#define FLASHPAGE_SIZE (4096U)
|
||||
#elif defined(CPU_LINE_STM32F091xC) || defined(CPU_LINE_STM32F072xB) \
|
||||
|| defined(CPU_LINE_STM32F030xC) || defined(CPU_LINE_STM32F103xE) \
|
||||
|| defined(CPU_FAM_STM32F3) || defined(CPU_FAM_STM32L4)
|
||||
#define FLASHPAGE_SIZE (2048U)
|
||||
#elif defined(CPU_LINE_STM32F051x8) || defined(CPU_LINE_STM32F042x6) \
|
||||
|| defined(CPU_LINE_STM32F070xB) || defined(CPU_LINE_STM32F030x8) \
|
||||
|| defined(CPU_LINE_STM32F030x4) || defined(CPU_LINE_STM32F103xB)
|
||||
#define FLASHPAGE_SIZE (1024U)
|
||||
#elif defined(CPU_FAM_STM32L1)
|
||||
#define FLASHPAGE_SIZE (256U)
|
||||
#elif defined(CPU_FAM_STM32L0)
|
||||
#define FLASHPAGE_SIZE (128U)
|
||||
#endif
|
||||
|
||||
#define FLASHPAGE_NUMOF (STM32_FLASHSIZE / FLASHPAGE_SIZE)
|
||||
|
||||
/* The minimum block size which can be written depends on the family.
|
||||
* However, the erase block is always FLASHPAGE_SIZE.
|
||||
*/
|
||||
#if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB)
|
||||
#define FLASHPAGE_RAW_BLOCKSIZE (8U)
|
||||
#elif defined(CPU_FAM_STM32L0) || defined(CPU_FAM_STM32L1)
|
||||
#define FLASHPAGE_RAW_BLOCKSIZE (4U)
|
||||
#else
|
||||
#define FLASHPAGE_RAW_BLOCKSIZE (2U)
|
||||
#endif
|
||||
|
||||
#if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB)
|
||||
#define FLASHPAGE_RAW_ALIGNMENT (8U)
|
||||
#else
|
||||
/* Writing should be always 4 bytes aligned */
|
||||
#define FLASHPAGE_RAW_ALIGNMENT (4U)
|
||||
#endif
|
||||
/** @} */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* CPU_CONF_H */
|
||||
/** @} */
|
||||
@ -7,7 +7,7 @@
|
||||
*/
|
||||
|
||||
/**
|
||||
* @ingroup cpu_stm32_common
|
||||
* @ingroup cpu_stm32
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
@ -7,19 +7,17 @@
|
||||
*/
|
||||
|
||||
/**
|
||||
* @ingroup cpu_stm32f0
|
||||
* @ingroup cpu_stm32
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief CPU specific definitions for internal peripheral handling
|
||||
* @brief STM32F0 CPU specific definitions for internal peripheral handling
|
||||
*
|
||||
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
|
||||
*/
|
||||
|
||||
#ifndef PERIPH_CPU_H
|
||||
#define PERIPH_CPU_H
|
||||
|
||||
#include "periph_cpu_common.h"
|
||||
#ifndef PERIPH_F0_PERIPH_CPU_H
|
||||
#define PERIPH_F0_PERIPH_CPU_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
@ -30,18 +28,6 @@ extern "C" {
|
||||
*/
|
||||
#define CPUID_ADDR (0x1ffff7ac)
|
||||
|
||||
/**
|
||||
* @brief Available ports on the STM32F0 family
|
||||
*/
|
||||
enum {
|
||||
PORT_A = 0, /**< port A */
|
||||
PORT_B = 1, /**< port B */
|
||||
PORT_C = 2, /**< port C */
|
||||
PORT_D = 3, /**< port D */
|
||||
PORT_E = 4, /**< port E */
|
||||
PORT_F = 5, /**< port F */
|
||||
};
|
||||
|
||||
#ifndef DOXYGEN
|
||||
/**
|
||||
* @brief Override ADC resolution values
|
||||
@ -59,17 +45,9 @@ typedef enum {
|
||||
/** @} */
|
||||
#endif /* ndef DOXYGEN */
|
||||
|
||||
/**
|
||||
* @brief ADC line configuration values
|
||||
*/
|
||||
typedef struct {
|
||||
gpio_t pin; /**< pin to use */
|
||||
uint8_t chan; /**< internal channel the pin is connected to */
|
||||
} adc_conf_t;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* PERIPH_CPU_H */
|
||||
#endif /* PERIPH_F0_PERIPH_CPU_H */
|
||||
/** @} */
|
||||
53
cpu/stm32/include/periph/f1/periph_cpu.h
Normal file
53
cpu/stm32/include/periph/f1/periph_cpu.h
Normal file
@ -0,0 +1,53 @@
|
||||
/*
|
||||
* Copyright (C) 2015-2016 Freie Universität Berlin
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser
|
||||
* General Public License v2.1. See the file LICENSE in the top level
|
||||
* directory for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @ingroup cpu_stm32
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief STM32F1 CPU specific definitions for internal peripheral handling
|
||||
*
|
||||
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
|
||||
*/
|
||||
|
||||
#ifndef PERIPH_F1_PERIPH_CPU_H
|
||||
#define PERIPH_F1_PERIPH_CPU_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Starting address of the CPU ID
|
||||
*/
|
||||
#define CPUID_ADDR (0x1ffff7e8)
|
||||
|
||||
/**
|
||||
* @name Real time counter configuration
|
||||
* @{
|
||||
*/
|
||||
#define RTT_IRQ_PRIO 1
|
||||
|
||||
#define RTT_DEV RTC
|
||||
#define RTT_IRQ RTC_IRQn
|
||||
#define RTT_ISR isr_rtc
|
||||
|
||||
#define RTT_MAX_VALUE (0xffffffff)
|
||||
#define RTT_CLOCK_FREQUENCY (32768U) /* in Hz */
|
||||
#define RTT_MIN_FREQUENCY (1U) /* in Hz */
|
||||
/* RTC frequency of 32kHz is not recommended, see RM0008 Rev 20, p490 */
|
||||
#define RTT_MAX_FREQUENCY (RTT_CLOCK_FREQUENCY / 2) /* in Hz */
|
||||
/** @} */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* PERIPH_F1_PERIPH_CPU_H */
|
||||
/** @} */
|
||||
@ -8,20 +8,18 @@
|
||||
*/
|
||||
|
||||
/**
|
||||
* @ingroup cpu_stm32f2
|
||||
* @ingroup cpu_stm32
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief CPU specific definitions for internal peripheral handling
|
||||
* @brief STM32F2 CPU specific definitions for internal peripheral handling
|
||||
*
|
||||
* @author Nick v. IJzendoorn <nijzendoorn@engineering-spirit.nl>
|
||||
* @author Aurelien Gonce <aurelien.gonce@altran.fr>
|
||||
*/
|
||||
|
||||
#ifndef PERIPH_CPU_H
|
||||
#define PERIPH_CPU_H
|
||||
|
||||
#include "periph_cpu_common.h"
|
||||
#ifndef PERIPH_F2_PERIPH_CPU_H
|
||||
#define PERIPH_F2_PERIPH_CPU_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
@ -32,35 +30,11 @@ extern "C" {
|
||||
*/
|
||||
#define CPUID_ADDR (0x1fff7a10)
|
||||
|
||||
/**
|
||||
* @brief Available ports on the STM32F2 family
|
||||
*/
|
||||
enum {
|
||||
PORT_A = 0, /**< port A */
|
||||
PORT_B = 1, /**< port B */
|
||||
PORT_C = 2, /**< port C */
|
||||
PORT_D = 3, /**< port D */
|
||||
PORT_E = 4, /**< port E */
|
||||
PORT_F = 5, /**< port F */
|
||||
PORT_G = 6, /**< port G */
|
||||
PORT_H = 7, /**< port H */
|
||||
PORT_I = 8 /**< port I */
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief Available number of ADC devices
|
||||
*/
|
||||
#define ADC_DEVS (2U)
|
||||
|
||||
/**
|
||||
* @brief ADC channel configuration data
|
||||
*/
|
||||
typedef struct {
|
||||
gpio_t pin; /**< pin connected to the channel */
|
||||
uint8_t dev; /**< ADCx - 1 device used for the channel */
|
||||
uint8_t chan; /**< CPU ADC channel connected to the pin */
|
||||
} adc_conf_t;
|
||||
|
||||
#ifndef DOXYGEN
|
||||
/**
|
||||
* @brief Override the ADC resolution configuration
|
||||
@ -82,5 +56,5 @@ typedef enum {
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* PERIPH_CPU_H */
|
||||
#endif /* PERIPH_F2_PERIPH_CPU_H */
|
||||
/** @} */
|
||||
36
cpu/stm32/include/periph/f3/periph_cpu.h
Normal file
36
cpu/stm32/include/periph/f3/periph_cpu.h
Normal file
@ -0,0 +1,36 @@
|
||||
/*
|
||||
* Copyright (C) 2015-2016 Freie Universität Berlin
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser
|
||||
* General Public License v2.1. See the file LICENSE in the top level
|
||||
* directory for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @ingroup cpu_stm32
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief STM32F3 CPU specific definitions for internal peripheral handling
|
||||
*
|
||||
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
|
||||
*/
|
||||
|
||||
#ifndef PERIPH_F3_PERIPH_CPU_H
|
||||
#define PERIPH_F3_PERIPH_CPU_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Starting address of the CPU ID
|
||||
*/
|
||||
#define CPUID_ADDR (0x1ffff7ac)
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* PERIPH_F3_PERIPH_CPU_H */
|
||||
/** @} */
|
||||
@ -7,19 +7,17 @@
|
||||
*/
|
||||
|
||||
/**
|
||||
* @ingroup cpu_stm32f4
|
||||
* @ingroup cpu_stm32
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief CPU specific definitions for internal peripheral handling
|
||||
* @brief STM32F4 CPU specific definitions for internal peripheral handling
|
||||
*
|
||||
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
|
||||
*/
|
||||
|
||||
#ifndef PERIPH_CPU_H
|
||||
#define PERIPH_CPU_H
|
||||
|
||||
#include "periph_cpu_common.h"
|
||||
#ifndef PERIPH_F4_PERIPH_CPU_H
|
||||
#define PERIPH_F4_PERIPH_CPU_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
@ -30,21 +28,6 @@ extern "C" {
|
||||
*/
|
||||
#define CPUID_ADDR (0x1fff7a10)
|
||||
|
||||
/**
|
||||
* @brief Available ports on the STM32F4 family
|
||||
*/
|
||||
enum {
|
||||
PORT_A = 0, /**< port A */
|
||||
PORT_B = 1, /**< port B */
|
||||
PORT_C = 2, /**< port C */
|
||||
PORT_D = 3, /**< port D */
|
||||
PORT_E = 4, /**< port E */
|
||||
PORT_F = 5, /**< port F */
|
||||
PORT_G = 6, /**< port G */
|
||||
PORT_H = 7, /**< port H */
|
||||
PORT_I = 8 /**< port I */
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief Available number of ADC devices
|
||||
*/
|
||||
@ -75,18 +58,9 @@ typedef enum {
|
||||
/** @} */
|
||||
#endif /* ndef DOXYGEN */
|
||||
|
||||
/**
|
||||
* @brief ADC channel configuration data
|
||||
*/
|
||||
typedef struct {
|
||||
gpio_t pin; /**< pin connected to the channel */
|
||||
uint8_t dev; /**< ADCx - 1 device used for the channel */
|
||||
uint8_t chan; /**< CPU ADC channel connected to the pin */
|
||||
} adc_conf_t;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* PERIPH_CPU_H */
|
||||
#endif /* PERIPH_F4_PERIPH_CPU_H */
|
||||
/** @} */
|
||||
41
cpu/stm32/include/periph/f7/periph_cpu.h
Normal file
41
cpu/stm32/include/periph/f7/periph_cpu.h
Normal file
@ -0,0 +1,41 @@
|
||||
/*
|
||||
* Copyright (C) 2017 Freie Universität Berlin
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser
|
||||
* General Public License v2.1. See the file LICENSE in the top level
|
||||
* directory for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @ingroup cpu_stm32
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief STM32F7 CPU specific definitions for internal peripheral handling
|
||||
*
|
||||
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef PERIPH_F7_PERIPH_CPU_H
|
||||
#define PERIPH_F7_PERIPH_CPU_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @name Starting address of the CPU ID
|
||||
*/
|
||||
#if defined(CPU_LINE_STM32F722xx) || defined(CPU_LINE_STM32F723xx)
|
||||
#define CPUID_ADDR (0x1ff07a10)
|
||||
#else
|
||||
#define CPUID_ADDR (0x1ff0f420)
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* PERIPH_F7_PERIPH_CPU_H */
|
||||
/** @} */
|
||||
@ -8,21 +8,19 @@
|
||||
*/
|
||||
|
||||
/**
|
||||
* @ingroup cpu_stm32l0
|
||||
* @ingroup cpu_stm32
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief CPU specific definitions for internal peripheral handling
|
||||
* @brief STM32L0 CPU specific definitions for internal peripheral handling
|
||||
*
|
||||
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
|
||||
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef PERIPH_CPU_H
|
||||
#define PERIPH_CPU_H
|
||||
|
||||
#include "periph_cpu_common.h"
|
||||
#ifndef PERIPH_L0_PERIPH_CPU_H
|
||||
#define PERIPH_L0_PERIPH_CPU_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
@ -33,18 +31,6 @@ extern "C" {
|
||||
*/
|
||||
#define CPUID_ADDR (0x1ff80050)
|
||||
|
||||
/**
|
||||
* @brief Available ports on the STM32L0 family
|
||||
*/
|
||||
enum {
|
||||
PORT_A = 0, /**< port A */
|
||||
PORT_B = 1, /**< port B */
|
||||
PORT_C = 2, /**< port C */
|
||||
PORT_D = 3, /**< port D */
|
||||
PORT_E = 4, /**< port E */
|
||||
PORT_H = 7, /**< port H */
|
||||
};
|
||||
|
||||
#ifndef DOXYGEN
|
||||
/**
|
||||
* @brief Override ADC resolution values
|
||||
@ -62,14 +48,6 @@ typedef enum {
|
||||
/** @} */
|
||||
#endif /* ndef DOXYGEN */
|
||||
|
||||
/**
|
||||
* @brief ADC line configuration values
|
||||
*/
|
||||
typedef struct {
|
||||
gpio_t pin; /**< pin to use */
|
||||
uint8_t chan; /**< internal channel the pin is connected to */
|
||||
} adc_conf_t;
|
||||
|
||||
/**
|
||||
* @name EEPROM configuration
|
||||
* https://www.st.com/en/microcontrollers-microprocessors/stm32l0-series.html#products
|
||||
@ -95,5 +73,5 @@ typedef struct {
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* PERIPH_CPU_H */
|
||||
#endif /* PERIPH_L0_PERIPH_CPU_H */
|
||||
/** @} */
|
||||
@ -8,20 +8,18 @@
|
||||
*/
|
||||
|
||||
/**
|
||||
* @ingroup cpu_stm32l1
|
||||
* @ingroup cpu_stm32
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief CPU specific definitions for internal peripheral handling
|
||||
* @brief STM32L1 CPU specific definitions for internal peripheral handling
|
||||
*
|
||||
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
|
||||
* @author Katja Kirstein <katja.kirstein@haw-hamburg.de>
|
||||
*/
|
||||
|
||||
#ifndef PERIPH_CPU_H
|
||||
#define PERIPH_CPU_H
|
||||
|
||||
#include "periph_cpu_common.h"
|
||||
#ifndef PERIPH_L1_PERIPH_CPU_H
|
||||
#define PERIPH_L1_PERIPH_CPU_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
@ -37,28 +35,6 @@ extern "C" {
|
||||
#define CPUID_ADDR (0x1ff800d0)
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Available ports on the STM32L1 family
|
||||
*/
|
||||
enum {
|
||||
PORT_A = 0, /**< port A */
|
||||
PORT_B = 1, /**< port B */
|
||||
PORT_C = 2, /**< port C */
|
||||
PORT_D = 3, /**< port D */
|
||||
PORT_E = 4, /**< port E */
|
||||
PORT_F = 6, /**< port F */
|
||||
PORT_G = 7, /**< port G */
|
||||
PORT_H = 5, /**< port H */
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief ADC channel configuration data
|
||||
*/
|
||||
typedef struct {
|
||||
gpio_t pin; /**< pin connected to the channel */
|
||||
uint8_t chan; /**< CPU ADC channel connected to the pin */
|
||||
} adc_conf_t;
|
||||
|
||||
#ifndef DOXYGEN
|
||||
/**
|
||||
* @brief Override the ADC resolution configuration
|
||||
@ -94,5 +70,5 @@ typedef enum {
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* PERIPH_CPU_H */
|
||||
#endif /* PERIPH_L1_PERIPH_CPU_H */
|
||||
/** @} */
|
||||
@ -7,20 +7,18 @@
|
||||
*/
|
||||
|
||||
/**
|
||||
* @ingroup cpu_stm32l4
|
||||
* @ingroup cpu_stm32
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief CPU specific definitions for internal peripheral handling
|
||||
* @brief STM32L4 CPU specific definitions for internal peripheral handling
|
||||
*
|
||||
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef PERIPH_CPU_H
|
||||
#define PERIPH_CPU_H
|
||||
|
||||
#include "periph_cpu_common.h"
|
||||
#ifndef PERIPH_L4_PERIPH_CPU_H
|
||||
#define PERIPH_L4_PERIPH_CPU_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
@ -31,21 +29,6 @@ extern "C" {
|
||||
*/
|
||||
#define CPUID_ADDR (0x1fff7590)
|
||||
|
||||
/**
|
||||
* @brief Available ports
|
||||
*/
|
||||
enum {
|
||||
PORT_A = 0, /**< port A */
|
||||
PORT_B = 1, /**< port B */
|
||||
PORT_C = 2, /**< port C */
|
||||
PORT_D = 3, /**< port D */
|
||||
PORT_E = 4, /**< port E */
|
||||
PORT_F = 5, /**< port F */
|
||||
PORT_G = 6, /**< port G */
|
||||
PORT_H = 7, /**< port H */
|
||||
PORT_I = 8, /**< port I */
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief Available number of ADC devices
|
||||
*/
|
||||
@ -80,18 +63,9 @@ typedef enum {
|
||||
/** @} */
|
||||
#endif /* ndef DOXYGEN */
|
||||
|
||||
/**
|
||||
* @brief ADC channel configuration data
|
||||
*/
|
||||
typedef struct {
|
||||
gpio_t pin; /**< pin connected to the channel */
|
||||
uint8_t dev; /**< ADCx - 1 device used for the channel */
|
||||
uint8_t chan; /**< CPU ADC channel connected to the pin */
|
||||
} adc_conf_t;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* PERIPH_CPU_H */
|
||||
#endif /* PERIPH_L4_PERIPH_CPU_H */
|
||||
/** @} */
|
||||
37
cpu/stm32/include/periph/wb/periph_cpu.h
Normal file
37
cpu/stm32/include/periph/wb/periph_cpu.h
Normal file
@ -0,0 +1,37 @@
|
||||
/*
|
||||
* Copyright (C) 2019 Inria
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser
|
||||
* General Public License v2.1. See the file LICENSE in the top level
|
||||
* directory for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @ingroup cpu_stm32
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief STM32WB CPU specific definitions for internal peripheral handling
|
||||
*
|
||||
* @author Francisco Molina <francois-xavier.molina@inria.fr>
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef PERIPH_WB_PERIPH_CPU_H
|
||||
#define PERIPH_WB_PERIPH_CPU_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Starting address of the CPU ID
|
||||
*/
|
||||
#define CPUID_ADDR (0x1fff7580)
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* PERIPH_WB_PERIPH_CPU_H */
|
||||
/** @} */
|
||||
@ -8,7 +8,7 @@
|
||||
*/
|
||||
|
||||
/**
|
||||
* @ingroup cpu_stm32_common
|
||||
* @ingroup cpu_stm32
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
@ -18,11 +18,35 @@
|
||||
* @author Vincent Dupont <vincent@otakeys.com>
|
||||
*/
|
||||
|
||||
#ifndef PERIPH_CPU_COMMON_H
|
||||
#define PERIPH_CPU_COMMON_H
|
||||
#ifndef PERIPH_CPU_H
|
||||
#define PERIPH_CPU_H
|
||||
|
||||
#include "cpu.h"
|
||||
|
||||
#if defined(CPU_FAM_STM32F0)
|
||||
#include "periph/f0/periph_cpu.h"
|
||||
#elif defined(CPU_FAM_STM32F1)
|
||||
#include "periph/f1/periph_cpu.h"
|
||||
#elif defined(CPU_FAM_STM32F2)
|
||||
#include "periph/f2/periph_cpu.h"
|
||||
#elif defined(CPU_FAM_STM32F3)
|
||||
#include "periph/f3/periph_cpu.h"
|
||||
#elif defined(CPU_FAM_STM32F4)
|
||||
#include "periph/f4/periph_cpu.h"
|
||||
#elif defined(CPU_FAM_STM32F7)
|
||||
#include "periph/f7/periph_cpu.h"
|
||||
#elif defined(CPU_FAM_STM32L0)
|
||||
#include "periph/l0/periph_cpu.h"
|
||||
#elif defined(CPU_FAM_STM32L1)
|
||||
#include "periph/l1/periph_cpu.h"
|
||||
#elif defined(CPU_FAM_STM32L4)
|
||||
#include "periph/l4/periph_cpu.h"
|
||||
#elif defined(CPU_FAM_STM32WB)
|
||||
#include "periph/wb/periph_cpu.h"
|
||||
#else
|
||||
#error Unsupported STM32 CPU family
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
@ -165,6 +189,38 @@ typedef uint32_t gpio_t;
|
||||
*/
|
||||
#define GPIO_PIN(x, y) ((GPIOA_BASE + (x << 10)) | y)
|
||||
|
||||
/**
|
||||
* @brief Available GPIO ports
|
||||
*/
|
||||
enum {
|
||||
PORT_A = 0, /**< port A */
|
||||
PORT_B = 1, /**< port B */
|
||||
PORT_C = 2, /**< port C */
|
||||
PORT_D = 3, /**< port D */
|
||||
PORT_E = 4, /**< port E */
|
||||
PORT_F = 5, /**< port F */
|
||||
#if defined(CPU_FAM_STM32F1) || defined(CPU_FAM_STM32F2) || \
|
||||
defined(CPU_FAM_STM32F3) || defined(CPU_FAM_STM32F4) || \
|
||||
defined(CPU_FAM_STM32F7) || defined(CPU_FAM_STM32L1) || \
|
||||
defined(CPU_FAM_STM32L4)
|
||||
PORT_G = 6, /**< port G */
|
||||
#endif
|
||||
#if defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F3) || \
|
||||
defined(CPU_FAM_STM32F4) || defined(CPU_FAM_STM32F7) || \
|
||||
defined(CPU_FAM_STM32L0) || defined(CPU_FAM_STM32L1) || \
|
||||
defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB)
|
||||
PORT_H = 7, /**< port H */
|
||||
#endif
|
||||
#if defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4) || \
|
||||
defined(CPU_FAM_STM32F7) || defined(CPU_FAM_STM32L4)
|
||||
PORT_I = 8, /**< port I */
|
||||
#endif
|
||||
#if defined(CPU_FAM_STM32F7)
|
||||
PORT_J = 9, /**< port J */
|
||||
PORT_K = 10, /**< port K */
|
||||
#endif
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief Define a magic number that tells us to use hardware chip select
|
||||
*
|
||||
@ -225,7 +281,49 @@ typedef enum {
|
||||
#endif
|
||||
} gpio_af_t;
|
||||
|
||||
#ifndef CPU_FAM_STM32F1
|
||||
#ifdef CPU_FAM_STM32F1
|
||||
#ifndef DOXYGEN
|
||||
/**
|
||||
* @brief Generate GPIO mode bitfields
|
||||
*
|
||||
* We use 4 bit to determine the pin functions:
|
||||
* - bit 4: ODR value
|
||||
* - bit 2+3: in/out
|
||||
* - bit 1: PU enable
|
||||
* - bit 2: OD enable
|
||||
*/
|
||||
#define GPIO_MODE(mode, cnf, odr) (mode | (cnf << 2) | (odr << 4))
|
||||
|
||||
/**
|
||||
* @brief Override GPIO mode options
|
||||
*
|
||||
* We use 4 bit to encode CNF and MODE.
|
||||
* @{
|
||||
*/
|
||||
#define HAVE_GPIO_MODE_T
|
||||
typedef enum {
|
||||
GPIO_IN = GPIO_MODE(0, 1, 0), /**< input w/o pull R */
|
||||
GPIO_IN_PD = GPIO_MODE(0, 2, 0), /**< input with pull-down */
|
||||
GPIO_IN_PU = GPIO_MODE(0, 2, 1), /**< input with pull-up */
|
||||
GPIO_OUT = GPIO_MODE(3, 0, 0), /**< push-pull output */
|
||||
GPIO_OD = GPIO_MODE(3, 1, 0), /**< open-drain w/o pull R */
|
||||
GPIO_OD_PU = (0xff) /**< not supported by HW */
|
||||
} gpio_mode_t;
|
||||
/** @} */
|
||||
#endif /* ndef DOXYGEN */
|
||||
|
||||
/**
|
||||
* @brief Override values for pull register configuration
|
||||
* @{
|
||||
*/
|
||||
#define HAVE_GPIO_PP_T
|
||||
typedef enum {
|
||||
GPIO_NOPULL = 4, /**< do not use internal pull resistors */
|
||||
GPIO_PULLUP = 9, /**< enable internal pull-up resistor */
|
||||
GPIO_PULLDOWN = 8 /**< enable internal pull-down resistor */
|
||||
} gpio_pp_t;
|
||||
/** @} */
|
||||
#else /* CPU_FAM_STM32F1 */
|
||||
/**
|
||||
* @brief Generate GPIO mode bitfields
|
||||
*
|
||||
@ -251,7 +349,10 @@ typedef enum {
|
||||
GPIO_OD_PU = GPIO_MODE(1, 1, 1) /**< open-drain with pull-up */
|
||||
} gpio_mode_t;
|
||||
/** @} */
|
||||
#endif /* ndef DOXYGEN */
|
||||
#endif /* ndef CPU_FAM_STM32F1 */
|
||||
|
||||
#ifndef DOXYGEN
|
||||
/**
|
||||
* @brief Override flank configuration values
|
||||
* @{
|
||||
@ -264,7 +365,6 @@ typedef enum {
|
||||
} gpio_flank_t;
|
||||
/** @} */
|
||||
#endif /* ndef DOXYGEN */
|
||||
#endif /* ndef CPU_FAM_STM32F1 */
|
||||
|
||||
#ifdef MODULE_PERIPH_DMA
|
||||
/**
|
||||
@ -331,6 +431,35 @@ typedef enum {
|
||||
/** @} */
|
||||
#endif /* MODULE_PERIPH_DMA */
|
||||
|
||||
/**
|
||||
* @brief Available number of ADC devices
|
||||
*/
|
||||
#if defined(CPU_FAM_STM32F1) || defined(CPU_FAM_STM32F2)
|
||||
#define ADC_DEVS (2U)
|
||||
#elif defined(CPU_LINE_STM32F401xE) || defined(CPU_LINE_STM32F410Rx) \
|
||||
|| defined(CPU_LINE_STM32F411xE) || defined(CPU_LINE_STM32F412Zx) \
|
||||
|| defined(CPU_LINE_STM32F413xx) || defined(CPU_LINE_STM32F423xx) \
|
||||
|| defined(CPU_MODEL_STM32L452RE) || defined(CPU_MODEL_STM32L432KC)
|
||||
#define ADC_DEVS (1U)
|
||||
#elif defined(CPU_LINE_STM32F405xx) || defined(CPU_LINE_STM32F407xx) \
|
||||
|| defined(CPU_LINE_STM32F415xx) || defined(CPU_LINE_STM32F429xx) \
|
||||
|| defined(CPU_LINE_STM32F437xx) || defined(CPU_LINE_STM32F446xx) \
|
||||
|| defined(CPU_MODEL_STM32L476RG) || defined(CPU_MODEL_STM32L475VG)
|
||||
#define ADC_DEVS (3U)
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief ADC channel configuration data
|
||||
*/
|
||||
typedef struct {
|
||||
gpio_t pin; /**< pin connected to the channel */
|
||||
#if !defined(CPU_FAM_STM32F0) && !defined(CPU_FAM_STM32L0) && \
|
||||
!defined(CPU_FAM_STM32L1)
|
||||
uint8_t dev; /**< ADCx - 1 device used for the channel */
|
||||
#endif
|
||||
uint8_t chan; /**< CPU ADC channel connected to the pin */
|
||||
} adc_conf_t;
|
||||
|
||||
/**
|
||||
* @brief DAC line configuration data
|
||||
*/
|
||||
@ -970,5 +1099,5 @@ int32_t stm32_eth_phy_write(uint16_t addr, uint8_t reg, uint16_t value);
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* PERIPH_CPU_COMMON_H */
|
||||
#endif /* PERIPH_CPU_H */
|
||||
/** @} */
|
||||
@ -7,7 +7,7 @@
|
||||
*/
|
||||
|
||||
/**
|
||||
* @ingroup cpu_stm32_common
|
||||
* @ingroup cpu_stm32
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
@ -7,8 +7,8 @@
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup cpu_stm32_common_usbdev stm32 USB OTG FS/HS peripheral
|
||||
* @ingroup cpu_stm32_common
|
||||
* @defgroup cpu_stm32_usbdev stm32 USB OTG FS/HS peripheral
|
||||
* @ingroup cpu_stm32
|
||||
* @brief USB interface functions for the stm32 class devices
|
||||
*
|
||||
* @{
|
||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue
Block a user