This adds support for the gd32v class devices from Gigadevice. The
gd32vf103 contains an 108 MHz RISC-V core with similar peripherals as
the stm32f1 devices
Co-authored-by: Benjamin Valentin <benjamin.valentin@ml-pa.com>
Introduce XMEGA EBI driver. This enable EBI for use with all memory
supported by the device and peripherals. It include support to SRAM,
SDRAM, LCDs or any other external bus access.
Note: This feature only works for A1/A1U series, which are, the series
with EBI hardware.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Fixes this error with binutils 2.37:
```
/usr/lib/gcc/arm-none-eabi/11.2.0/../../../../arm-none-eabi/bin/ld:cortexm_base.ld:217: warning: memory region `bkup' not declared
/usr/lib/gcc/arm-none-eabi/11.2.0/../../../../arm-none-eabi/bin/ld:cortexm_base.ld:217: syntax error
```
Update features definitions and configurations. Now atxmega define
features that only are full available on all variations and do not
require any definition at periph_conf.h file.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Add a minimal implementation of `strerror()`.
All other targets use either newlib or picolibc and provide this
function, add it to AVR so we can rely on it in common code.
SERCOM5 on SAM L21 does not support fractional baud rate mode.
Instead of special-casing it, just use arithmetic baud rate mode
in general on this CPU, as I'm not sure what the advantages of fractional
baud rate mode are.
fixes#16692
In case of network heavy traffic on the Ethernet, interrupts
fire faster than the netdev thread can process them and we
run out of buffers. With this commit, we now check if we
don't have buffers available, so we can flush everything and
restart reception properly even if we did drop a few in the
operation
When using the I2C_NOSTOP flag the bus should remain in control.
The current check assumes it must go to idle when reading.
This adds a condition checks if the nostop flag is active
and expects the bus status to be the owner of the bus.
This reverts commit 585dc15f99.
I did misunderstand this feature: This only inverts the data
bits (instead of `c` uart will transmit `~c`), not the whole
line level.
This is not very useful on it's own, so revert it.
If esp_idf_heap is not used, implement calloc through a custom wrapper
function on top of malloc to add overflow detection, which is not
present in the newlib forks with xtensa support yet.
The handle_trap function is used internally by the trap_entry
implementation from the same file. However, the trap_entry
implementation calls handle_trap from inline assembly. This makes it
difficult for the compiler to infer that the handle_trap function is
used at all. This causes issues when LTO is enabled.
Without this patch compiling any RISC-V RIOT code with `LTO=1` causes
the following linker error:
/home/soeren/src/RIOT/cpu/riscv_common/irq_arch.c:134: undefined reference to `handle_trap'
/tmp/hello-world.elf.Nngidp.ltrans0.ltrans.o:cpu/riscv_common/irq_arch.c:134:(.text.trap_entry+0x34):
relocation truncated to fit: R_RISCV_GPREL_I against undefined symbol `handle_trap'
This commit fixes LTO support for RISC-V.
While at it, also mark the function as static as it is only used by the
trap_entry function from the same compilation unit.
The esp8266 CPU has actually two hardware UART peripherals. UART0 is
used by the boot ROM for flashing and serial output during boot,
typically at a baudrate of 74880 bps until the bootloader or application
sets the more standard 115200 baudrate. This UART0 device has two
possible pins for TXD, GPIO1 and GPIO2, which are both set to TXD by the
boot ROM. esp8266 modules will typically have GPIO1 labeled as the TX
pin, but it is possible to use GPIO2 for that purpose even while
flashing the device with esptool.py.
The second device, UART1, also has two options for TXD, GPIO2 and GPIO7,
and only one option for RXD, GPIO8. However, GPIO7 and GPIO8 are used
by the flash internally so those options are not very useful unless
maybe while running from IRAM with the flash disabled, for example for
a debugger over UART1.
This patch allows boards to override UART{0,1}_{R,T}XD in their
periph_conf.h to configure the uart selection. Defining UART1_TX will
make the UART_DEV(1) device available.
Tested with:
```CFLAGS='-DUART1_TXD=GPIO2' make -C tests/periph_uart BOARD=esp8266-esp-12x flash term```
* Connected one USB-UART to the standard GPIO1 and GPIO3 for flashing
and console. After flashing we see the manual test output at 115200
bps
* Connected a second USB-UART with RX to GPIO2 running at 74880.
Then run on the first console:
```
> init 1 74880
> send 1 hello
```
The word "hello" appears on the second UART connection.
Note that GPIO2 is used during boot for UART0's TX until the application
or bootloader set it to a regular GPIO, so some boot ROM messages at
74880 bps are visible. After running `init 1 74880` it is set to UART1's
TX.
The RTT overflow callback is not available on all RTT implementations.
This means it is either a no-op or `rtt_set_overflow_cb()` is a no-op
or it will overwrite the alarm set with `rtt_set_alarm()`.
This adds a feature to indicate that proper overflow reporting is available.
This allows to use the sam0 RTT together with the rtt_rtc module.
The idea is to use RTT as a monotonic counter, but still keep track
of the time with the virtual RTC module.
In I2C, clock stretching occurs when the controller stops driving SCL
down but the peripheral continues to drive SCL down until the value of
SDA that is expected to be set by the peripheral is ready. This allows a
peripheral to communicate at a high speed but introduce a delay in the
response (like an ACK or read) in some specific situations. Not all I2C
peripherals require I2C stretching, and in many cases SCL is only an
input to these peripherals.
Clock stretching is the only situation where a peripheral may drive down
SCL, which technically makes SCL an open-drain with a pull-up like SDA.
However, if clock stretching is not needed, SCL can be configured as an
output removing the need for a pull-up and specially, allowing to use
as SCL GPIO pins that otherwise have a pull-down connected. In
particular, GPIO15 in the ESP8266 requires an external pull-down during
boot for the ESP8266 to boot from the flash.
This patch allows a board to define `I2C_CLOCK_STRETCH` to 0 to disable
clock stretching and allowing to use GPIO15 as SCL.
If we configure TAMPCTRL early, GPIO events will set bits in the
TAMPCTRL register.
That means that after a wake-up, we can't tell if the bit was set
because it was the wake-up source or if it was already set by a
run-time GPIO event.
The extra `)` was a typo from the commit that changes the makefile
inline "if" to a multi-line "if" block.
Tested with `USEMODULE="esp_gdbstub" make BOARD=esp8266-esp-12x -C tests/lwip`
The current xmega don't have a way to disable peripherals that are
not in used. Add peripheral management to allow enable only the mcu
blocks that will be used by application. This saves power on active
and sleep modes. By default, at clock initialization, all peripherals
are now disabled and each drive must activate at initialization phase.
The periph_timer and periph_uart were updated with this new feature.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
The current ATxmega clock_init enable DFLL to improve the accuracy of
the 2MHz and 32MHz internal oscillators. In some ATxmega revisions,
after started DFLL the clock become unstable. Add another sync point
for 32MHz internal oscilator.
Note: If clock is not stable, system won't switch from 2MHz to 32MHz
as main clock.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Fix compilation with module `stm32_eth_link_up` when `stm32_eth_auto`
is not used by relying on the compiler to optimize unused functions
and variables out, rather than using the preprocessor.
- Clear the PTP timer interrupt *after* the user callback is executed
- Otherwise it would be possible that the ISR sets another super
short timeout that triggers during ISR, which also gets cleared
- This is a pretty nasty race condition :-/
- The debug output was a bit too verbose to be generally useful. Some
noise is now silenced unless `DEBUG_VERBOSE` is `#define`d to 1
Atmel AVR-8 CPU was reworked to accomodate variants like ATxmega.
This rename to atmega.inc.mk to avr8.inc.mk to be compliant with
new directory structure.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
ATxmega have many clock options. This introduce clk_init into cpu_init
to allow user select between a default configuration or perform fine
clock tune.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
