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cc2538_rf: adapt to Radio HAL changes
This commit is contained in:
Jose Alamos
Jose Alamos
parent
4cfe62fc99
commit
44934d300c
@ -107,7 +107,10 @@ extern "C" {
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#define CC2538_RSSI_OFFSET (-73) /**< Signal strength offset value */
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#define CC2538_RF_SENSITIVITY (-97) /**< dBm typical, normal conditions */
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#define CC2538_ACCEPT_FT_0_BEACON (1 << 3) /**< enable or disable the BEACON filter */
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#define CC2538_ACCEPT_FT_1_DATA (1 << 4) /**< enable or disable the DATA filter */
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#define CC2538_ACCEPT_FT_2_ACK (1 << 5) /**< enable or disable the ACK filter */
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#define CC2538_ACCEPT_FT_3_CMD (1 << 6) /**< enable or disable the CMD filter */
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#define CC2538_STATE_SFD_WAIT_RANGE_MIN (0x03U) /**< min range value of SFD wait state */
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#define CC2538_STATE_SFD_WAIT_RANGE_MAX (0x06U) /**< max range value of SFD wait state */
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#define CC2538_FRMCTRL1_PENDING_OR_MASK (0x04) /**< mask for enabling or disabling the
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@ -174,6 +174,9 @@ void cc2538_init(void)
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/* setup mac timer */
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_cc2538_setup_mac_timer();
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/* Enable Auto ACK */
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RFCORE->XREG_FRMCTRL0bits.AUTOACK = !IS_ACTIVE(CONFIG_IEEE802154_AUTO_ACK_DISABLE);
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/* Flush the receive and transmit FIFOs */
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RFCORE_SFR_RFST = ISFLUSHTX;
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RFCORE_SFR_RFST = ISFLUSHRX;
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@ -352,7 +352,7 @@ void cc2538_irq_handler(void)
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/* Disable RX while the frame has not been processed */
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RFCORE_XREG_RXMASKCLR = 0xFF;
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/* If AUTOACK is enabled and the ACK request bit is set */
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if (RFCORE->XREG_FRMCTRL0bits.AUTOACK &&
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if (!IS_ACTIVE(CONFIG_IEEE802154_AUTO_ACK_DISABLE) &&
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(rfcore_peek_rx_fifo(1) & IEEE802154_FCF_ACK_REQ)) {
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/* The next SFD will be the ACK's, ignore it */
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cc2538_sfd_listen = false;
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@ -400,31 +400,51 @@ static int _off(ieee802154_dev_t *dev)
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return -ENOTSUP;
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}
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static int _set_hw_addr_filter(ieee802154_dev_t *dev, const network_uint16_t *short_addr,
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const eui64_t *ext_addr, const uint16_t *pan_id)
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static int _config_addr_filter(ieee802154_dev_t *dev, ieee802154_af_cmd_t cmd, const void *value)
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{
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(void) dev;
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if (short_addr) {
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RFCORE_FFSM_SHORT_ADDR0 = short_addr->u8[1];
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RFCORE_FFSM_SHORT_ADDR1 = short_addr->u8[0];
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const network_uint16_t *short_addr = value;
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const eui64_t *ext_addr = value;
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const uint16_t *pan_id = value;
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switch(cmd) {
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case IEEE802154_AF_SHORT_ADDR:
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RFCORE_FFSM_SHORT_ADDR0 = short_addr->u8[1];
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RFCORE_FFSM_SHORT_ADDR1 = short_addr->u8[0];
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break;
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case IEEE802154_AF_EXT_ADDR:
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RFCORE_FFSM_EXT_ADDR0 = ext_addr->uint8[7];
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RFCORE_FFSM_EXT_ADDR1 = ext_addr->uint8[6];
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RFCORE_FFSM_EXT_ADDR2 = ext_addr->uint8[5];
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RFCORE_FFSM_EXT_ADDR3 = ext_addr->uint8[4];
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RFCORE_FFSM_EXT_ADDR4 = ext_addr->uint8[3];
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RFCORE_FFSM_EXT_ADDR5 = ext_addr->uint8[2];
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RFCORE_FFSM_EXT_ADDR6 = ext_addr->uint8[1];
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RFCORE_FFSM_EXT_ADDR7 = ext_addr->uint8[0];
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break;
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case IEEE802154_AF_PANID:
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RFCORE_FFSM_PAN_ID0 = *pan_id;
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RFCORE_FFSM_PAN_ID1 = (*pan_id) >> 8;
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break;
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case IEEE802154_AF_PAN_COORD:
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return -ENOTSUP;
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}
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if (ext_addr) {
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RFCORE_FFSM_EXT_ADDR0 = ext_addr->uint8[7];
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RFCORE_FFSM_EXT_ADDR1 = ext_addr->uint8[6];
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RFCORE_FFSM_EXT_ADDR2 = ext_addr->uint8[5];
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RFCORE_FFSM_EXT_ADDR3 = ext_addr->uint8[4];
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RFCORE_FFSM_EXT_ADDR4 = ext_addr->uint8[3];
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RFCORE_FFSM_EXT_ADDR5 = ext_addr->uint8[2];
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RFCORE_FFSM_EXT_ADDR6 = ext_addr->uint8[1];
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RFCORE_FFSM_EXT_ADDR7 = ext_addr->uint8[0];
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}
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return 0;
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}
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if (pan_id) {
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RFCORE_FFSM_PAN_ID0 = *pan_id;
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RFCORE_FFSM_PAN_ID1 = (*pan_id) >> 8;
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static int _config_src_addr_match(ieee802154_dev_t *dev, ieee802154_src_match_t cmd, const void *value)
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{
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(void) dev;
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switch(cmd) {
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case IEEE802154_SRC_MATCH_EN:
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RFCORE_XREG_FRMCTRL1 &= ~CC2538_FRMCTRL1_PENDING_OR_MASK;
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if (*((const bool*) value) == true) {
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RFCORE_XREG_FRMCTRL1 |= CC2538_FRMCTRL1_PENDING_OR_MASK;
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}
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break;
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default:
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return -ENOTSUP;
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}
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return 0;
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}
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@ -468,43 +488,6 @@ static int _set_cca_mode(ieee802154_dev_t *dev, ieee802154_cca_mode_t mode)
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return 0;
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}
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static int _set_rx_mode(ieee802154_dev_t *dev, ieee802154_rx_mode_t mode)
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{
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(void) dev;
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bool promisc = false;
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bool ack_filter = true;
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switch (mode) {
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case IEEE802154_RX_AACK_DISABLED:
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RFCORE->XREG_FRMCTRL0bits.AUTOACK = 0;
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break;
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case IEEE802154_RX_AACK_ENABLED:
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RFCORE->XREG_FRMCTRL0bits.AUTOACK = 1;
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RFCORE_XREG_FRMCTRL1 &= ~CC2538_FRMCTRL1_PENDING_OR_MASK;
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break;
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case IEEE802154_RX_AACK_FRAME_PENDING:
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RFCORE->XREG_FRMCTRL0bits.AUTOACK = 1;
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RFCORE_XREG_FRMCTRL1 |= CC2538_FRMCTRL1_PENDING_OR_MASK;
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break;
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case IEEE802154_RX_PROMISC:
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promisc = true;
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break;
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case IEEE802154_RX_WAIT_FOR_ACK:
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ack_filter = false;
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break;
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}
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if (ack_filter) {
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RFCORE_XREG_FRMFILT1 &= ~CC2538_ACCEPT_FT_2_ACK;
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}
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else {
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RFCORE_XREG_FRMFILT1 |= CC2538_ACCEPT_FT_2_ACK;
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}
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cc2538_set_monitor(promisc);
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return 0;
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}
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static int _set_csma_params(ieee802154_dev_t *dev, const ieee802154_csma_be_t *bd, int8_t retries)
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{
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(void) dev;
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@ -518,6 +501,34 @@ static int _set_csma_params(ieee802154_dev_t *dev, const ieee802154_csma_be_t *b
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return 0;
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}
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static int _set_frame_filter_mode(ieee802154_dev_t *dev, ieee802154_filter_mode_t mode)
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{
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(void) dev;
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uint8_t flags = 0;
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bool promisc = false;
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switch (mode) {
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case IEEE802154_FILTER_ACCEPT:
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flags = CC2538_ACCEPT_FT_0_BEACON
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| CC2538_ACCEPT_FT_1_DATA
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| CC2538_ACCEPT_FT_3_CMD;
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break;
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case IEEE802154_FILTER_PROMISC:
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promisc = true;
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break;
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case IEEE802154_FILTER_ACK_ONLY:
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flags = CC2538_ACCEPT_FT_2_ACK;
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break;
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default:
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return -ENOTSUP;
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}
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RFCORE_XREG_FRMFILT1 |= flags;
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cc2538_set_monitor(promisc);
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return 0;
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}
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static const ieee802154_radio_ops_t cc2538_rf_ops = {
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.caps = IEEE802154_CAP_24_GHZ
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| IEEE802154_CAP_AUTO_CSMA
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@ -543,7 +554,8 @@ static const ieee802154_radio_ops_t cc2538_rf_ops = {
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.set_cca_threshold = _set_cca_threshold,
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.set_cca_mode = _set_cca_mode,
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.config_phy = _config_phy,
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.set_hw_addr_filter = _set_hw_addr_filter,
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.config_addr_filter = _config_addr_filter,
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.config_src_addr_match = _config_src_addr_match,
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.set_csma_params = _set_csma_params,
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.set_rx_mode = _set_rx_mode,
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.set_frame_filter_mode = _set_frame_filter_mode,
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};
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