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cpu/saml21: fix timer skew for slow clocks

This commit is contained in:
Antonio Galea 2021-05-05 10:56:37 +02:00
parent 43103a65d5
commit 8bd90aaf00
2 changed files with 8 additions and 4 deletions

View File

@ -99,8 +99,12 @@ uint32_t sam0_gclk_freq(uint8_t id)
switch (id) {
case SAM0_GCLK_MAIN:
return CLOCK_CORECLOCK;
case SAM0_GCLK_8MHZ:
case SAM0_GCLK_TIMER:
#if (CLOCK_CORECLOCK == 48000000U) || (CLOCK_CORECLOCK == 16000000U) || (CLOCK_CORECLOCK == 8000000U)
return 8000000;
#else
return 4000000;
#endif
case SAM0_GCLK_32KHZ:
return 32768;
case SAM0_GCLK_48MHZ:
@ -292,8 +296,8 @@ void cpu_init(void)
}
}
/* clock used by timers */
_gclk_setup(SAM0_GCLK_8MHZ, GCLK_GENCTRL_GENEN | GCLK_GENCTRL_SRC_OSC16M
| GCLK_GENCTRL_DIV(2));
_gclk_setup(SAM0_GCLK_TIMER, GCLK_GENCTRL_GENEN | GCLK_GENCTRL_SRC_OSC16M
| GCLK_GENCTRL_DIV(CLOCK_CORECLOCK/sam0_gclk_freq(SAM0_GCLK_TIMER)));
#ifdef MODULE_PERIPH_PM
PM->CTRLA.reg = PM_CTRLA_MASK & (~PM_CTRLA_IORET);

View File

@ -44,7 +44,7 @@ extern "C" {
*/
enum {
SAM0_GCLK_MAIN = 0, /**< Main clock */
SAM0_GCLK_8MHZ = 1, /**< 8MHz clock */
SAM0_GCLK_TIMER = 1, /**< 4/8MHz clock for timers */
SAM0_GCLK_32KHZ = 2, /**< 32 kHz clock */
SAM0_GCLK_48MHZ = 3, /**< 48MHz clock */
};