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cpu/saml21: fix timer skew for slow clocks
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@ -99,8 +99,12 @@ uint32_t sam0_gclk_freq(uint8_t id)
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switch (id) {
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case SAM0_GCLK_MAIN:
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return CLOCK_CORECLOCK;
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case SAM0_GCLK_8MHZ:
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case SAM0_GCLK_TIMER:
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#if (CLOCK_CORECLOCK == 48000000U) || (CLOCK_CORECLOCK == 16000000U) || (CLOCK_CORECLOCK == 8000000U)
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return 8000000;
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#else
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return 4000000;
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#endif
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case SAM0_GCLK_32KHZ:
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return 32768;
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case SAM0_GCLK_48MHZ:
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@ -292,8 +296,8 @@ void cpu_init(void)
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}
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}
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/* clock used by timers */
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_gclk_setup(SAM0_GCLK_8MHZ, GCLK_GENCTRL_GENEN | GCLK_GENCTRL_SRC_OSC16M
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| GCLK_GENCTRL_DIV(2));
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_gclk_setup(SAM0_GCLK_TIMER, GCLK_GENCTRL_GENEN | GCLK_GENCTRL_SRC_OSC16M
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| GCLK_GENCTRL_DIV(CLOCK_CORECLOCK/sam0_gclk_freq(SAM0_GCLK_TIMER)));
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#ifdef MODULE_PERIPH_PM
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PM->CTRLA.reg = PM_CTRLA_MASK & (~PM_CTRLA_IORET);
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@ -44,7 +44,7 @@ extern "C" {
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*/
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enum {
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SAM0_GCLK_MAIN = 0, /**< Main clock */
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SAM0_GCLK_8MHZ = 1, /**< 8MHz clock */
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SAM0_GCLK_TIMER = 1, /**< 4/8MHz clock for timers */
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SAM0_GCLK_32KHZ = 2, /**< 32 kHz clock */
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SAM0_GCLK_48MHZ = 3, /**< 48MHz clock */
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};
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