For consistency, use named GCLKs.
- `SAM0_GCLK_32KHZ` will always be 2 for samd21
- `SAM0_GCLK_MAIN` will always be 0
So no change in functionality, just makes the code easier to understand.
Creating an `exti_config` array for a new MCU manually is tedious and error prone.
Luckiely all information is already availiable in the vendor files.
Credit for this discovery & method goes to @Sizurka
The file was generated with
```C
int main(void) {
puts("static const int8_t exti_config[PORT_GROUPS][32] = {");
for (unsigned port = 1; port < 5; ++port) {
printf("#if PORT_GROUPS >= %d\n{\n", port);
for (unsigned pin = 0; pin < 32; ++pin) {
printf("#ifdef PIN_P%c%02uA_EIC_EXTINT_NUM\n", '@' + port, pin);
printf(" PIN_P%c%02uA_EIC_EXTINT_NUM,\n", '@' + port, pin);
printf("#else\n -1,\n#endif\n");
}
printf("},\n#endif\n\n");
}
puts("};");
return 0;
}
```
No changes in generated code are expected, but this makes adding new members
of the sam0 CPU families much easier.
samr30 is the only MCU of this family where the vendor files do not
define the PIN_($pin)_EIC_EXTINT_NUM macro yet.
This macro is needed to create a generic EXTI configuration for all
sam0 MCUs.
The defines were generated with
sed -Ei '/define PIN_(.*)_EIC_EXTINT([0-9]*)/
{h; x;
s/define PIN_(.*)A_EIC_EXTINT([0-9]*)(.*)/
define PIN_\1A_EIC_EXTINT_NUM _L_\(\2\)
\/**< \brief EIC signal: PIN_\1 External Interrupt Line *\/
/g; G}' samr30g18a.h samr30e18a.h
bitarithm.h is not needed for the interface of shed but may cause conflicts
due to different definitions of SETBIT and CLRBIT
common implementations are: (value, offset) xor (value, mask) bitarithm
implements the later
frac.c and nrf52/usbdev.c use bitarithm.h but where missing the include
sam0/rtt.c defined a bit using mask from bitarithm,
changed that to the soulution used in sam0/rtc.c
Instead of hard-coding the peripheral clocks to CLOCK_CORECLOCK
introduce helper functions to return the frequency of the individual
GCLKs and use those for baud-rate calculations.
This requires the GCLK to be part of the peripheral's config struct.
While this is already the case for most peripherals, this also adds
it for those where it wasn't used before.
As it defaults to 0 (CLOCK_CORECLOCK) no change is to be expected.
To simplify board definitions and for unification between samd2x and
newer models, don't use the GCLK bitmask in board definitions.
Instead use the GCLK index and generate the bitmask when needed.
The common ADC API dictates that a sample call must return -1 on an
incorrect resolution. The sam0 ADC implementation instead threw an
assertion failure.
Currently, spi_acquire() will always re-configure the SPI bus.
If the configuration did not change, this is entirely uneccecary
and makes SPI operations take longer than needed.
Instead, compare the current configuration with the new configuration
and skip the initialisation if it didn't change since the last call.
The RTC expects to be clocked from a 1kHz source.
Previously it would re-configure GCLK2 from 32kHz to 1kHz when used.
Since GCLK2 is also used by EIC, this would break external interrupts
in strange and unexpected ways.
Dedicate a 1kHz clock to it to avoid the damage.
From the data sheet:
> The COUNT register requires synchronization when reading.
> Disabling the synchronization will prevent reading valid
> values from the COUNT register.
Without this bit enabled, rtt_get_counter() will always return 0.
Scan-build detected that sercom_id could return -1 and the value of this function is affected to uint8_t variables. Since these variables are used for shitfing bit in registers, this could lead to undefined behavior
This change is for all boards with a sam0 cpu. This cpu just has one ADC.
It is unnecessary to have defines with ADC_0_ prefix as if multiple ADCs
are possible.
Some defines were not used, such as ADC_0_EN, ADC_0_CHANNELS,
ADC_MAX_CHANNELS, ADC_0_CLK_SOURCE, ADC_0_CHANNELS
Change all ADC_0_ prefixes to ADC_
In fractional mode, 3 bits are used to store the fractional part.
Therefore we must multiply / divide by 8 instead of 10 in order to
get the correct values.
A naive implementation may set a RTC alarm in 30s by calling
struct tm now;
rtc_get_time(&now);
now.tm_sec += 30;
rtc_set_alarm(&now, _cb, NULL);
This works for RTC implementations that use a RTT internally and call
mktime() to convert the struct tm to a unix timestamp, as mktime() will
normalize the struct in the process.
Call rtc_tm_normalize() when the RTC uses separate registers for time / date
components to ensure it is normalized.
This also modifies tests/periph_rtc to exercise this case.
The INTFLAGS register is cleared by writing a 1 to the corresponding interrupt
flag bit. From the samr21's manual:
> Writing a zero to this bit has no effect.
> Writing a one to this bit clears the Compare 0 interrupt flag.
This is a common pattern in flag registers.
This RTT driver is using or-equal to clear the flags, which means it can
possibly clear other interrupts. There's a small chance that one event is
missed if it happens very close to another event.
Credits to @benpicco, @dylad for pointing out missing fixes.
_exti() always assumes only 2 ports, so it will always fail when using
e.g. port C or port D on same54.
Instead, determine the number of ports from the dimensions of the exti_config
array.
This adds supoprt for the Atmel SAMD51 & SAME54 SoC.
The SAME5x/SAMD5x is a line of Cortex-M4F MCUs that share peripherals
with the samd2x Cortex-M0+ and saml1x Cortex-M23 parts.
Atmel Software Framework (ASF) provides a set of low-level header files
that give access to different hardware peripherals of Atmel's ICs.
Origin: Atmel SAMD51 Series Device Support (1.1.96)
License: Apache-2.0
URL: http://packs.download.atmel.com/Atmel.SAMD51_DFP.1.1.96.atpack
Atmel Software Framework (ASF) provides a set of low-level header
files that give access to different hardware peripherals of Atmel's
ICs.
Origin: Atmel SAME54 Series Device Support (1.0.87)
License: Apache-2.0
URL: http://packs.download.atmel.com/Atmel.SAME54_DFP.1.0.87.atpack
This cleans up the sam0 timer driver:
- remove the check for the unused freq parameter
- the MCU provides dedicated SET/CLR registers to avoid
read-modify-write, so don't do read-modify-write on them.
- workaround a possible hardware bug on SAMD5x:
loop until the CMD_READSYNC is really set
Rational: the periph_common module is required by (most) other periph drivers
and also during startup of the CPU/MCU to run periph_init. The latter is only
required if other periph drivers are used, hence periph_common should be a
depency of periph_* modules and *not* of the CPU/MCU. This PR fixes that
by making periph_common a depency of periph_* and removing the explicit
include in the CPU/MCU implementation.
The currently supported SAM0 MCUs (samd21, saml21, saml1x) share the same
Timer peripheral, yet each of them carries it's own copy of the Timer
driver.
This introduces a new timer driver that is common for all sam0 MCUs and
uses structs for configuration instead of defines.
The currently supported SAM0 MCUs (samd21, saml21, saml1x) share the
same RTC peripheral, yet each of them carries it's own copy of the RTT
driver.
Unify the drivers and move them to sam0_common.
The currently supported SAM0 MCUs (samd21, saml21, saml1x) share the
same RTC peripheral, yet each of them carries it's own copy of the RTC
driver.
Unify the drivers and move them to sam0_common.
