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boards: add initial hamilton board support

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This commit is contained in:
Hyungsin 2019-04-03 15:00:35 -07:00
parent 88171698e0
commit d9c17c2154
14 changed files with 530 additions and 8 deletions
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3
boards/hamilton/Makefile Normal file
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@ -0,0 +1,3 @@
MODULE = board
include $(RIOTBASE)/Makefile.base

14
boards/hamilton/Makefile.dep Normal file
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ifneq (,$(filter gnrc_netdev_default netdev_default,$(USEMODULE)))
USEMODULE += at86rf233
endif
ifneq (,$(filter saul_default,$(USEMODULE)))
USEMODULE += fxos8700
USEMODULE += hdc1000
USEMODULE += pir
USEMODULE += pulse_counter
USEMODULE += saul_gpio
USEMODULE += tmp006
# ToDo: peripherals to be added in the future
#USEMODULE += apds9007
endif

14
boards/hamilton/Makefile.features Normal file
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# Put defined MCU peripherals here (in alphabetical order)
FEATURES_PROVIDED += periph_adc
FEATURES_PROVIDED += periph_gpio periph_gpio_irq
FEATURES_PROVIDED += periph_i2c
FEATURES_PROVIDED += periph_pwm
FEATURES_PROVIDED += periph_rtc
FEATURES_PROVIDED += periph_rtt
FEATURES_PROVIDED += periph_spi
FEATURES_PROVIDED += periph_timer
# The board MPU family (used for grouping by the CI system)
FEATURES_MCU_GROUP = cortex_m0_2
-include $(RIOTCPU)/samd21/Makefile.features

16
boards/hamilton/Makefile.include Normal file
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# define the cpu used by Hamilton
export CPU = samd21
export CPU_MODEL = samr21e18a
# debugger config
export JLINK_DEVICE := atsamr21e18a
export OBJDUMPFLAGS += --disassemble --source --disassembler-options=force-thumb
export OFLAGS := -O binary --gap-fill 0xff
# Configure terminal, hamilton doesn't provide any UART, thus use RTT
TERMPROG = $(RIOTTOOLS)/jlink/jlink.sh
TERMFLAGS = term_rtt
USEMODULE += stdio_rtt
include $(RIOTMAKE)/tools/jlink.inc.mk

33
boards/hamilton/board.c Normal file
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/*
* Copyright (C) 2016 University of California, Berkeley
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup boards_hamilton
* @{
*
* @file
* @brief Board specific implementations for the Hamilton mote
*
* @author Michael Andersen <m.andersen@berkeley.edu>
*
* @}
*/
#include <stdio.h>
#include "board.h"
#include "periph/gpio.h"
void board_init(void)
{
/* initialize the on-board LED */
gpio_init(LED0_PIN, GPIO_OUT);
/* initialize the CPU */
cpu_init();
}

141
boards/hamilton/include/board.h Normal file
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/*
* Copyright (C) 2016 UC Berkeley
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @defgroup boards_hamilton HamiltonIoT Hamilton
* @ingroup boards
* @brief Support for the HamiltonIoT Hamilton board.
* @{
*
* @file
* @brief Board specific definitions for the Hamilton board
*
* @author Michael Andersen <m.andersen@cs.berkeley.edu>
* @author Hyung-Sin Kim <hs.kim@cs.berkeley.edu>
*/
#ifndef BOARD_H
#define BOARD_H
#include "cpu.h"
#include "periph_conf.h"
#include "periph_cpu.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name xtimer configuration
* @{
*/
#define XTIMER_DEV TIMER_DEV(1)
#define XTIMER_CHAN (0)
#define XTIMER_OVERHEAD (0)
/** @} */
/**
* @name AT86RF233 configuration
* @{
*/
#define AT86RF2XX_PARAM_SPI SPI_DEV(0)
#define AT86RF2XX_PARAM_SPI_CLK SPI_CLK_5MHZ
#define AT86RF2XX_PARAM_CS GPIO_PIN(PB, 31)
#define AT86RF2XX_PARAM_INT GPIO_PIN(PB, 0)
#define AT86RF2XX_PARAM_SLEEP GPIO_PIN(PA, 20)
#define AT86RF2XX_PARAM_RESET GPIO_PIN(PB, 15)
/** @} */
/**
* @name LED pin definitions and handlers
* @{
*/
#define LED0_PIN GPIO_PIN(0, 19)
#define LED0_PORT PORT->Group[0]
#define LED0_MASK (1 << 19)
#define LED0_ON (LED0_PORT.OUTCLR.reg = LED0_MASK)
#define LED0_OFF (LED0_PORT.OUTSET.reg = LED0_MASK)
#define LED0_TOGGLE (LED0_PORT.OUTTGL.reg = LED0_MASK)
/** @} */
/**
* @name Button pin definitions
* @{
*/
#define BTN0_PORT PORT->Group[0]
#define BTN0_PIN GPIO_PIN(0, 18)
#define BTN0_MODE GPIO_IN_PU
/** @} */
/**
* @name FXOS8700 configuration
* Note that another fxos8700 operation option, FXOS8700_USE_ACC_RAW_VALUES,
* need to be set according to the application purposes
* @{
*/
#define FXOS8700_PARAM_I2C I2C_DEV(0)
#define FXOS8700_PARAM_ADDR (0x1E)
#define FXOS8700_PARAM_RENEW_INTERVAL (1000000ul)
/** @} */
/**
* @name HDC1080 configuration
* @{
*/
#define HDC1000_PARAM_I2C I2C_DEV(0)
#define HDC1000_PARAM_ADDR (0x40)
#define HDC1000_PARAM_RES HDC1000_14BIT
#define HDC1000_PARAM_RENEW_INTERVAL (1000000ul)
/** @} */
/**
* @name EKMB (PIR motion sensor) configuration
* @{
*/
#define PIR_PARAM_GPIO GPIO_PIN(PA, 6)
#define PIR_PARAM_ACTIVE_HIGH (1)
/** @} */
/**
* @name PULSE_COUNTER configuration
* @{
*/
#define PULSE_COUNTER_GPIO BTN0_PIN
#define PULSE_COUNTER_GPIO_FLANK GPIO_FALLING
/** @} */
/**
* @name TMP006 configuration
* Note that two other tmp006 operation options, TMP006_USE_LOW_POWER and
* TMP006_USE_RAW_VALUES, need to be set according to the application purpose
* @{
*/
#define TMP006_PARAM_I2C I2C_DEV(0)
#define TMP006_PARAM_ADDR (0x44)
#define TMP006_PARAM_RATE TMP006_CONFIG_CR_AS2
/** @} */
/**
* @name ToDo: APDS9007 configuration
* @{
*/
/** @} */
/**
* @brief Initialize board specific hardware, including clock, LEDs and std-IO
*/
void board_init(void);
#ifdef __cplusplus
}
#endif
#endif /* BOARD_H */
/** @} */

58
boards/hamilton/include/gpio_params.h Normal file
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@ -0,0 +1,58 @@
/*
* Copyright (C) 2015 Freie Universität Berlin
* 2015 Kaspar Schleiser <kaspar@schleiser.de>
* 2016 UC Berkeley
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup boards_hamilton
* @{
*
* @file
* @brief Board specific configuration of direct mapped GPIOs
*
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
* @author Kaspar Schleiser <kaspar@schleiser.de>
* @author Sebastian Meiling <s@mlng.net>
* @author Michael Andersen <m.andersen@berkeley.edu>
*/
#ifndef GPIO_PARAMS_H
#define GPIO_PARAMS_H
#include "board.h"
#include "saul/periph.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief GPIO pin configuration
*/
static const saul_gpio_params_t saul_gpio_params[] =
{
{
.name = "LED(red)",
.pin = LED0_PIN,
.mode = GPIO_OUT,
.flags = SAUL_GPIO_INVERTED,
},
{
.name = "Button",
.pin = BTN0_PIN,
.mode = BTN0_MODE,
.flags = SAUL_GPIO_INVERTED,
},
};
#ifdef __cplusplus
}
#endif
#endif /* GPIO_PARAMS_H */
/** @} */

242
boards/hamilton/include/periph_conf.h Normal file
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/*
* Copyright (C) 2014-2015 Freie Universität Berlin
* 2016 UC Berkeley
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup boards_hamilton
* @{
*
* @file
* @brief Configuration of CPU peripherals for the Hamilton mote
*
* @author Thomas Eichinger <thomas.eichinger@fu-berlin.de>
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
* @author Peter Kietzmann <peter.kietzmann@haw-hamburg.de>
* @author Michael Andersen <m.andersen@berkeley.edu>
* @author Hyung-Sin Kim <hs.kim@berkeley.edu>
*/
#ifndef PERIPH_CONF_H
#define PERIPH_CONF_H
#include <stdint.h>
#include "cpu.h"
#include "periph_cpu.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name External oscillator and clock configuration
*
* There are three choices for selection of CORECLOCK:
*
* - usage of the 48 MHz DFLL fed by external oscillator running at 32 kHz
* - usage of the PLL fed by the internal 8MHz oscillator divided by 8
* - usage of the internal 8MHz oscillator directly, divided by N if needed
*
*
* The PLL option allows for the usage of a wider frequency range and a more
* stable clock with less jitter. This is why this option is default.
*
* The target frequency is computed from the PLL multiplier and the PLL divisor.
* Use the following formula to compute your values:
*
* CORECLOCK = ((PLL_MUL + 1) * 1MHz) / PLL_DIV
*
* NOTE: The PLL circuit does not run with less than 32MHz while the maximum PLL
* frequency is 96MHz. So PLL_MUL must be between 31 and 95!
*
*
* The internal Oscillator used directly can lead to a slightly better power
* efficiency to the cost of a less stable clock. Use this option when you know
* what you are doing! The actual core frequency is adjusted as follows:
*
* CORECLOCK = 8MHz / DIV
*
* NOTE: A core clock frequency below 1MHz is not recommended
*
* @{
*/
#define CLOCK_USE_PLL (1)
#if CLOCK_USE_PLL
/* edit these values to adjust the PLL output frequency */
#define CLOCK_PLL_MUL (47U) /* must be >= 31 & <= 95 */
#define CLOCK_PLL_DIV (1U) /* adjust to your needs */
/* generate the actual used core clock frequency */
#define CLOCK_CORECLOCK (((CLOCK_PLL_MUL + 1) * 1000000U) / CLOCK_PLL_DIV)
#elif CLOCK_USE_XOSC32_DFLL
/* Settings for 32 kHz external oscillator and 48 MHz DFLL */
#define CLOCK_CORECLOCK (48000000U)
#define CLOCK_XOSC32K (32768UL)
#define CLOCK_8MHZ (1)
#define GEN2_ULP32K (1)
#else
/* edit this value to your needs */
#define CLOCK_DIV (1U)
/* generate the actual core clock frequency */
#define CLOCK_CORECLOCK (8000000 / CLOCK_DIV)
#endif
/** @} */
/**
* @name RTC configuration
* @{
*/
#define RTC_NUMOF (1U)
#define RTC_DEV RTC->MODE2
/** @} */
/**
* @name RTT configuration
* @{
*/
#define RTT_NUMOF (1U)
#define RTT_DEV RTC->MODE0
#define RTT_IRQ RTC_IRQn
#define RTT_IRQ_PRIO 10
#define RTT_ISR isr_rtc
#define RTT_MAX_VALUE (0xffffffff)
#define RTT_FREQUENCY (32768U) /* in Hz. For changes see `rtt.c` */
#define RTT_RUNSTDBY (1) /* Keep RTT running in sleep states */
/** @} */
/**
* @name Timer peripheral configuration
* @{
*/
#define TIMER_NUMOF (2U)
#define TIMER_0_EN 1
#define TIMER_1_EN 1
/* Timer 0 configuration */
#define TIMER_0_DEV TC3->COUNT16
#define TIMER_0_CHANNELS 2
#define TIMER_0_MAX_VALUE (0xffff)
#define TIMER_0_ISR isr_tc3
/* Timer 1 configuration */
#define TIMER_1_DEV TC4->COUNT32
#define TIMER_1_CHANNELS 2
#define TIMER_1_MAX_VALUE (0xffffffff)
#define TIMER_1_ISR isr_tc4
/** @} */
/**
* @name ADC Configuration
* @{
*/
#define ADC_0_EN 1
#define ADC_MAX_CHANNELS 14
/* ADC 0 device configuration */
#define ADC_0_DEV ADC
#define ADC_0_IRQ ADC_IRQn
/* ADC 0 Default values */
#define ADC_0_CLK_SOURCE 0 /* GCLK_GENERATOR_0 */
#define ADC_0_PRESCALER ADC_CTRLB_PRESCALER_DIV512
#define ADC_0_NEG_INPUT ADC_INPUTCTRL_MUXNEG_GND
#define ADC_0_GAIN_FACTOR_DEFAULT ADC_INPUTCTRL_GAIN_1X
#define ADC_0_REF_DEFAULT ADC_REFCTRL_REFSEL_INT1V
static const adc_conf_chan_t adc_channels[] = {
/* port, pin, muxpos */
{GPIO_PIN(PA, 6), ADC_INPUTCTRL_MUXPOS_PIN6},
{GPIO_PIN(PA, 7), ADC_INPUTCTRL_MUXPOS_PIN7},
{GPIO_PIN(PA, 8), ADC_INPUTCTRL_MUXPOS_PIN16},
};
#define ADC_0_CHANNELS (3U)
#define ADC_NUMOF ADC_0_CHANNELS
/** @} */
/**
* @name PWM configuration
* @{
*/
#define PWM_0_EN 1
#define PWM_1_EN 1
#define PWM_NUMOF (PWM_0_EN + PWM_1_EN)
#define PWM_MAX_CHANNELS 2
/* PWM device configuration */
#if PWM_NUMOF
static const pwm_conf_t pwm_config[] = {
#if PWM_0_EN
{TCC1, {
/* GPIO pin, MUX value, TCC channel */
{GPIO_PIN(PA, 6), GPIO_MUX_E, 0},
{GPIO_PIN(PA, 7), GPIO_MUX_E, 1}
}},
#endif
#if PWM_1_EN
{TCC0, {
/* GPIO pin, MUX value, TCC channel */
{GPIO_PIN(PA, 18), GPIO_MUX_F, 2},
{GPIO_PIN(PA, 19), GPIO_MUX_F, 3}
}},
#endif
};
#endif
/** @} */
/**
* @name SPI configuration
* @{
*/
static const spi_conf_t spi_config[] = {
{
.dev = &SERCOM4->SPI,
.miso_pin = GPIO_PIN(PC, 19),
.mosi_pin = GPIO_PIN(PB, 30),
.clk_pin = GPIO_PIN(PC, 18),
.miso_mux = GPIO_MUX_F,
.mosi_mux = GPIO_MUX_F,
.clk_mux = GPIO_MUX_F,
.miso_pad = SPI_PAD_MISO_0,
.mosi_pad = SPI_PAD_MOSI_2_SCK_3
}
};
#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
/** @} */
/**
* @name I2C configuration
* @{
*/
static const i2c_conf_t i2c_config[] = {
{
.dev = &(SERCOM3->I2CM),
.speed = I2C_SPEED_FAST,
.scl_pin = GPIO_PIN(PA, 17),
.sda_pin = GPIO_PIN(PA, 16),
.mux = GPIO_MUX_D,
.gclk_src = GCLK_CLKCTRL_GEN_GCLK0,
.flags = I2C_FLAG_NONE
}
};
#define I2C_NUMOF (sizeof(i2c_config) / sizeof(i2c_config[0]))
/**
* @name Random Number Generator configuration
* @{
*/
#define RANDOM_NUMOF (0U)
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* PERIPH_CONF_H */
/** @} */

2
cpu/sam0_common/Makefile.include
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@ -2,7 +2,7 @@
CFLAGS += -DCPU_FAM_$(shell echo $(CPU_FAM) | tr 'a-z-' 'A-Z_')
# Set ROM and RAM lengths according to CPU model
ifneq (,$(filter samd21g18a samd21j18a saml21j18b saml21j18a samr21g18a samr30g18a,$(CPU_MODEL)))
ifneq (,$(filter samd21g18a samd21j18a saml21j18b saml21j18a samr21e18a samr21g18a samr30g18a,$(CPU_MODEL)))
ROM_LEN ?= 0x40000
RAM_LEN ?= 0x8000
endif

2
examples/lua_REPL/Makefile
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@ -7,7 +7,7 @@ BOARD ?= native
RIOTBASE ?= $(CURDIR)/../..
BOARD_INSUFFICIENT_MEMORY := blackpill bluepill calliope-mini cc2650-launchpad \
cc2650stk maple-mini microbit nrf51dk nrf51dongle \
cc2650stk hamilton maple-mini microbit nrf51dk nrf51dongle \
nucleo-f030r8 nucleo-f031k6 nucleo-f042k6 \
nucleo-f070rb nucleo-f072rb nucleo-f103rb \
nucleo-f302r8 nucleo-f303k8 nucleo-f334r8 \

4
tests/gnrc_ipv6_ext/Makefile
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@ -9,8 +9,8 @@ BOARD_INSUFFICIENT_MEMORY := arduino-duemilanove arduino-mega2560 arduino-nano \
nucleo-f303k8 nucleo-f334r8 nucleo-l031k6 \
nucleo-l053r8 stm32f0discovery telosb thingy52 \
waspmote-pro wsn430-v1_3b wsn430-v1_4 z1
# chronos, mips-malta, and ruuvitag boards don't support ethos
BOARD_BLACKLIST := chronos mips-malta ruuvitag
# chronos, hamilton, mips-malta, and ruuvitag boards don't support ethos
BOARD_BLACKLIST := chronos hamilton mips-malta ruuvitag
export TAP ?= tap0

4
tests/gnrc_rpl_srh/Makefile
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@ -10,8 +10,8 @@ BOARD_INSUFFICIENT_MEMORY := arduino-duemilanove arduino-mega2560 arduino-nano \
nucleo-l053r8 saml10-xpro saml11-xpro \
stm32f0discovery telosb thingy52 waspmote-pro \
wsn430-v1_3b wsn430-v1_4 z1
# chronos, mips-malta, and ruuvitag boards don't support ethos
BOARD_BLACKLIST := chronos mips-malta ruuvitag
# chronos, hamilton mips-malta, and ruuvitag boards don't support ethos
BOARD_BLACKLIST := chronos hamilton mips-malta ruuvitag
export TAP ?= tap0

4
tests/gnrc_sock_dns/Makefile
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@ -8,8 +8,8 @@ BOARD_INSUFFICIENT_MEMORY := arduino-duemilanove arduino-mega2560 arduino-nano \
nucleo-f030r8 nucleo-f303k8 nucleo-l053r8 \
nucleo-l031k6 stm32f0discovery thingy52 telosb \
waspmote-pro wsn430-v1_3b wsn430-v1_4 z1
# chronos, mips-malta, and ruuvitag boards don't support ethos
BOARD_BLACKLIST := chronos mips-malta ruuvitag
# chronos, hamilton mips-malta, and ruuvitag boards don't support ethos
BOARD_BLACKLIST := chronos hamilton mips-malta ruuvitag
export TAP ?= tap0

1
tests/unittests/Makefile
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@ -22,6 +22,7 @@ BOARD_INSUFFICIENT_MEMORY := airfy-beacon \
ek-lm4f120xl \
feather-m0 \
firefly \
hamilton \
ikea-tradfri \
limifrog-v1 maple-mini \
lobaro-lorabox \