This commits adds a common type for the block writes to the flash of the
stm32. Depending on the family, the type has a different size. This
allows the removal of a number of ifdefs to track the differences
between families, simplifying the flashpage code
Note that Kconfig.models was not generated with gen_kconfig.py tool
due to lack of ProductsList.xlsx file for STM32MP1 family.
Signed-off-by: Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
In STM32MP1 family, independant watchdogs (IWDG1 and IWDG2) are
dedicated to the MPU (Cortex-A7). Thus simply disable the feature
for STM32MP1 family.
Signed-off-by: Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
The stm32mp157c has the particularity to not having flash memory but
only SRAM.
Thus a part of SRAM must be considered as a ROM to flash the firmware
into.
In case of the stm32mp157c, the RETRAM (64kB) is used as ROM and the
4 banks of SRAM (384kB) are used as RAM.
However, as ROM_LEN, RAM_LEN, ROM_START_ADDRESS, RAM_START_ADDRESS and
ROM_OFFSET could be overloaded by user, set them with "?=" operator.
If the ROM_START_ADDRESS and the RAM_START_ADDRESS are not set at the
end of that file, it is a classic stm32 MCU with flash, thus set this
variables with common memory addresses for stm32 MCU family:
ROM_START_ADDR ?= 0x08000000
RAM_START_ADDR ?= 0x20000000
Signed-off-by: Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
In Engineering mode (BOOT0 off and BOOT2 on), only the Cortex-M4
core is running. It means that all clocks have to be setup
by the Cortex-M4 core.
In other modes, the clocks are setup by the Cortex-A7 and then should
not be setup by Cortex-M4.
stm32mp1_eng_mode pseudomodule have to be used in Engineering mode
to ensure clocks configuration with IS_USED(MODULE_STM32MP1_ENG_MODE)
macro.
This macro can also be used in periph_conf.h to define clock source
for each peripheral.
Signed-off-by: Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
STM32_PM_STOP and STM32_PM_STANDBY are always defined in periph_cpu.h,
Thus it is not needed to test them.
Signed-off-by: Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
According to stm32mp157 documentation:
* "The CStop mode is entered for MCU when the SLEEPDEEP bit in the Cortex®-M4 System Control
register is set." Thus set PM_STOP_CONFIG to 0.
* "The CStandby mode applies only to the MPU sub-system."
Set PM_STANDBY_CONFIG to (0) and do not enter standby mode for
stm32mp1.
As PM_STOP_CONFIG is already defined before for CPU_FAM_STM32WB, replace
it with CPU_FAM_STM32MP1.
Signed-off-by: Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
stm32mp1 is configuring gpio slightly differently that common stm32:
* port_num is computed differently, thus test MCU family to apply
the good calculation.
* Rising and falling edge state on interrupts. Do not test if falling
or rising edge, just launch the callback in all cases.
Signed-off-by: Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
Normally, CMSIS headers are retrieved as package from ST git repository
for each stm32.
However stm32mp1 family does not have a CMSIS headers repository but
have been included into RIOT source code in a previous commit.
For stm32mp1, CMSIS headers package must then not be retrieved and
vectors have to be generated from already in-source CMSIS headers.
Signed-off-by: Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
Include stm32mp1 vendors header. CORE_CM4 must be defined to include
Cortex-M4 core headers.
Signed-off-by: Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
stm32mp1 ordering informations are not the same than classical
single MCU.
And as stm32mp1 has no flash, just extract second part of model name
and pincount.
Signed-off-by: Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
The stm32mp1 family has no flash. The firmware is loaded directly in
RAM by stlink programmer or by Cortex-A7 bootloader/OS.
Thus bootloader is useless for this family, disable it.
Signed-off-by: Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
As stm32mp1 family accesses gpio pins with a different
offset than other stm32, create a specific macro.
Signed-off-by: Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
clk_conf is a useful tool to produce clock headers for new boards.
But it only supports STM32Fx families.
This commits add the definition of a new family: STM32MP1.
Only the STM32MP157 is supported for now.
First build clk_conf:
$ make -C cpu/stm32/dist/clk_conf/
Clock header can be generated with the following command once clk_conf is
built:
$ cpu/stm32/dist/clk_conf/clk_conf stm32mp157 208000000 24000000 1
This command line will produce a core clock of 208MHz with a 24MHz HSE
oscillator and will use LSE clock which corresponds to the STM32MP157C-DK2
board configuration.
The command will output the header to copy paste into the periph_conf.h of
the board:
/**
* @name Clock settings
*
* @note This is auto-generated from
* `cpu/stm32/dist/clk_conf/clk_conf.c`
* @{
*/
/* give the target core clock (HCLK) frequency [in Hz],
* maximum: 209MHz */
#define CLOCK_CORECLOCK (208000000U)
/* 0: no external high speed crystal available
* else: actual crystal frequency [in Hz] */
#define CLOCK_HSE (24000000U)
/* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz) */
#define CLOCK_LSE (1U)
/* peripheral clock setup */
#define CLOCK_MCU_DIV RCC_MCUDIVR_MCUDIV_1 /* max 209MHz */
#define CLOCK_MCU (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1_DIV RCC_APB1DIVR_APB1DIV_2 /* max 104MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
#define CLOCK_APB2_DIV RCC_APB2DIVR_APB2DIV_2 /* max 104MHz */
#define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
#define CLOCK_APB3_DIV RCC_APB3DIVR_APB3DIV_2 /* max 104MHz */
#define CLOCK_APB3 (CLOCK_CORECLOCK / 2)
/* Main PLL factors */
#define CLOCK_PLL_M (2)
#define CLOCK_PLL_N (52)
#define CLOCK_PLL_P (3)
#define CLOCK_PLL_Q (13)
/** @} */
This result has been verified with STM32CubeMX, the official ST tool.
Signed-off-by: Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
APB1 bus clock is always enabled is not manageable by RCC register.
So avoid enabling it.
Signed-off-by: Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
* Setup i2c speed to I2C_SPEED_LOW by default
* enable i2c_write_regs() function.
* i2c frequency needs to be specified into board periph_conf.h
Signed-off-by: Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
In some CMSIS headers, "typedef enum" could be preceded by white
spaces. Thus consider them when parsing the line.
Signed-off-by: Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
Default values were wrong for WB when using HSE 32MHz as PLL input source
Default PLL input source was wrong when not using HSE and the board
provides an HSE
The reception code hands RX DMA descriptors back to the DMA right after its
contents were copied into the network stack internal buffer. This increases
the odds that the DMA never runs out of DMA descriptors to fill, even under
high load. However, the loop fetching the Ethernet frame stops to iterate at the
end of the frame. If the DMA used one more descriptor to store the FCS, this
was not returned back to the DMA. This commit fixes it.
Expose the auto-negotiation feature of the Ethernet device via the
pseudo-module stm32_eth_auto. With this enabled, the static speed configuration
set in the boards periph_conf.h will only be used if the PHY lacks
auto-negotiation capabilities - which is unlikely to ever happen.
