RIOT-OS/RIOT
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Code Releases Activity
37,538 Commits 40 Branches 189 Tags 262 MiB
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Commit Graph

94 Commits

Author SHA1 Message Date
Koen Zandberg
a6b6f43ce2
sam0_common/usbdev: Adapt to xmit API 2021-11-16 20:17:04 +01:00
Jan Romann
4384795cb9
treewide: Remove excessive newlines 2021-08-13 19:50:38 +02:00
Benjamin Valentin
5f002ced1f Revert "cpu/sam0_common: UART: implement inverted RX & TX" 
This reverts commit 585dc15f99.

I did misunderstand this feature: This only inverts the data
bits (instead of `c` uart will transmit `~c`), not the whole
line level.

This is not very useful on it's own, so revert it.
 2021-05-21 12:47:03 +02:00
benpicco
bd6114ae9d
Merge pull request #16187 from benpicco/cpu/sam0_common/get_tamper 
cpu/sam0_common: add rtc_get_tamper_event()
 2021-04-13 14:11:46 +02:00
Benjamin Valentin
13fbb7c1a0 cpu/sam0_common: add rtc_tamper_pin_mask() 2021-04-13 10:45:16 +02:00
Benjamin Valentin
73dbda99ac cpu/sam0_common: add rtc_get_tamper() 
Add a function to query which tamper event woke the CPU from hibernation.
 2021-04-13 10:45:16 +02:00
dylad
99764b82ab cpu/sam0: correct periph_cpu_common.h documentation 2021-03-31 22:17:01 +02:00
Benjamin Valentin
31b8dad147 cpu/samd21: add support for SAMD20 2021-01-12 15:48:39 +01:00
dylad
e98459f414 cpu/saml11: fix GPIO/IOBUS management 2020-12-15 17:00:54 +01:00
dylad
a1f5b6182d cpu/sam0: add initial Ethernet support 2020-12-13 22:01:50 +01:00
Benjamin Valentin
8f72212eb0 cpu/sam0_common: SPI: add support for QSPI in SPI mode 
We can use the QSPI peripheral as an additional (non-Quad) SPI peripheral.
 2020-12-11 22:33:08 +01:00
Benjamin Valentin
2845554b4e cpu/sam0_common: flashpage: rename to sam0_flashpage_aux_write() 
`flashpage_write_raw()` got renamed to `flashpage_write()`.
Now `sam0_flashpage_aux_write_raw()` is the only remaining 'raw'
function, even though it behaves just like `flashpage_write()`.

So let's also rename that for consistency.
 2020-11-17 00:34:31 +01:00
Benjamin Valentin
20f093ede6 cpu/sam0_common: flashpage: introduce functions to write to user page 2020-11-10 12:18:47 +01:00
Benjamin Valentin
0499d016ad cpu/sam0_common: implement RTC tamper detection 2020-09-17 18:45:50 +02:00
benpicco
5715f5776b
Merge pull request #14804 from bergzand/pr/sam0/gpio_iobus 
sam0_common: Use Single-cycle I/O Port for GPIO when available
 2020-09-10 23:45:43 +02:00
Dylan Laduranty
4db8a1f602
Merge pull request #14478 from benpicco/cpu/sam0/tc_pwm 
cpu/sam0_common: add support to run PWM off TC timers
 2020-09-10 23:04:58 +02:00
Koen Zandberg
ddb22a3c56
sam0_common: Use Single-cycle I/O Port for GPIO when available 
The Cortex-m0 based ATSAM devices can use the Single-cycle I/O Port for
GPIO. This commit modifies the gpio_t type to use this port when
available. It is mapped back to the peripheral memory space for
configuration access.  When it is not available, the _port_iobus() and
_port() functions behave identical, which is the case for the samd51.
 2020-09-10 22:13:24 +02:00
Benjamin Valentin
0437461812 cpu/sam0_common: PWM: add support to run PWM off TC timers 2020-09-10 21:47:03 +02:00
Benjamin Valentin
7ed4979148 cpu/samd5x: define CPU_COMMON_SAMD5X symbol and use it 2020-08-24 16:13:18 +02:00
Benjamin Valentin
5d96151775 cpu/saml21: define CPU_COMMON_SAML21 symbol and use it 2020-08-24 16:13:18 +02:00
Benjamin Valentin
e32b0783c4 cpu/samd21: define CPU_COMMON_SAMD21 symbol and use it 2020-08-24 16:13:18 +02:00
Leandro Lanzieri
d7dbbb71ac
Merge pull request #14226 from benpicco/cpu/sam0_common/i2c_arbitrary_freqs 
cpu/sam0_common: i2c: fix BAUD handling & cleanup
 2020-08-04 14:49:10 +02:00
Benjamin Valentin
1472d2095c cpu/sam0_common: i2c: document frequency constraints 2020-08-04 12:13:28 +02:00
Benjamin Valentin
003c25b2e8 cpu/sam0_common: uart: document frequency constraints 2020-07-28 11:22:22 +02:00
Benjamin Valentin
e6f33fc436 cpu/sam0_common: uart: implement the periph_uart_reconfigure feature 2020-07-28 10:10:15 +02:00
Benjamin Valentin
c5f6a5c6f5 cpu/sam0_common: PWM: prepare for TC timers as PWM source 2020-07-19 01:38:15 +02:00
benpicco
30ebabb84e
Merge pull request #14007 from benpicco/cpu/sam0_common-pwm 
cpu/sam0_common: move PWM to common code, add support for saml21, samd5x
 2020-07-09 10:01:08 +02:00
Benjamin Valentin
bce7d25f10 cpu/sam0_common: add PWM support for saml2x, samd5x 2020-07-08 21:51:12 +02:00
Francisco
325b7a8d8e
Merge pull request #13631 from benpicco/cpu/sam0_common/spi-deinit 
drivers/periph/spi: add periph_spi_reconfigure feature & implementation for sam0
 2020-06-30 15:34:53 +02:00
Benjamin Valentin
c8ff026640 cpu/sam0_common: use TIMER_CHANNEL_NUMOF 2020-06-24 00:45:35 +02:00
Benjamin Valentin
3e91914831 cpu/sam0_common: spi: implement the periph_spi_reconfigure feature 2020-06-21 21:19:17 +02:00
Alexandre Abadie
07c78efc83
Merge pull request #14285 from fjmolinas/pr_uart_nb_race 
sam0/stm32: fix possible uart_nonblocking deadlock
 2020-06-17 12:14:25 +02:00
Francisco Molina
0b8adb2d27
cpu/sam0-stm32/uart: rename tx buf size to UART_TXBUF_SIZE 2020-06-17 10:01:20 +02:00
Benjamin Valentin
585dc15f99 cpu/sam0_common: UART: implement inverted RX & TX 
The UART TX and TX lines on SAMD5x and SAML1x can be inverted.
However, the flags don't do exactly what one would expect.

See errata 2.18.5: SERCOM-UART: TXINV and RXINV Bits Reference:

> The TXINV and RXINV bits in the CTRLA register have inverted functionality.
>
> Workaround:
> In software interpret the TXINV bit as a functionality of RXINV, and conversely,
> interpret the RXINV bit as a functionality of TXINV.
 2020-06-16 22:55:37 +02:00
benpicco
1992f57765
Merge pull request #14261 from bergzand/pr/sam0_common/spi_dma 
sam0_common: Make SPI peripheral DMA compatible
 2020-06-14 18:25:37 +02:00
Koen Zandberg
60f4502e6c
cpu/sam0_common: Make SPI peripheral DMA compatible 2020-06-14 14:56:20 +02:00
Koen Zandberg
22c8788b58
sam0_common/dma: Rename len to num 2020-06-14 11:51:36 +02:00
Koen Zandberg
02b2b58358
sam0_common: Add additional documentation on DMA usage 2020-06-14 11:48:43 +02:00
Koen Zandberg
7a8566c391
sam0_common/dma: Mark src parameter as const 2020-06-13 21:02:04 +02:00
benpicco
74299a2b03
Merge pull request #14260 from bergzand/pr/sam0_common/dma_periph 
sam0_common: Add DMA peripheral driver
 2020-06-12 21:18:31 +02:00
Koen Zandberg
6be1b27bbb
sam0_common: Add DMA peripheral driver 2020-06-12 20:04:05 +02:00
Benjamin Valentin
54b57bd97f cpu/sam0_common: drop prescaler from timer config 
since c05984b341 the prescaler in the timer
config struct is no longer used.

Let's remove it.
 2020-06-11 19:29:43 +02:00
Benjamin Valentin
824f7aa82b cpu/sam0_common: move PWM to common code 2020-06-07 16:50:17 +02:00
Benjamin Valentin
ec7ae668e2 cpu/sam0_common: define TIMER_CHANNELS 2020-05-28 13:24:06 +02:00
Francisco
cea0d1c532
Merge pull request #13421 from benpicco/cpu/sam0_common/i2c-deinit 
drivers/periph/i2c: add periph_i2c_reconfigure feature & implementation for sam0
 2020-05-05 19:09:47 +02:00
Benjamin Valentin
8c502322f4 cpu/sam0_common: i2c: implement the periph_i2c_reconfigure feature 
This adds sam0 implementations for

 - i2c_init_pins()
 - i2c_deinit_pins()
 - i2c_pin_sda()
 - i2c_pin_scl()
 2020-05-05 16:12:19 +02:00
Benjamin Valentin
5d123cbb22 cpu/sam0_common: distribute PM_NUM_MODES among siblings 
Also adapt the defines to the documentation

 - CPUs define up to 4 power modes (from zero, the lowest power mode,
   to PM_NUM_MODES-1, the highest)
 - >> there is an implicit extra idle mode (which has the number PM_NUM_MODES) <<

Previously on saml21 this would always generate pm_set(3) which is an illegal state.
Now pm_layered will correctly generate pm_set(2) for IDLE modes.

Idle power consumption dropped from 750µA to 368µA and wake-up from standby is also
possible. (Before it would just enter STANDBY again as the mode register was never
written with the illegal value.)
 2020-04-01 18:10:23 +02:00
Benjamin Valentin
895eb943d8 cpu/sam0_common: add cpu_pm_cb_enter()/leave() 
This allows to implement needed work-arounds surrounding sleep on
a per-MCU basis.
 2020-03-31 17:18:58 +02:00
Benjamin Valentin
9b90fd478a cpu/sam0_common: provide function to switch voltage regulator 
Add a fucntion to switch between LDO and Buck concerter to provide the
internal CPU voltage.
The Buck Converter is not compatible with internal fast oscillators (DFLL, DPLL)
and requires an inductivity to be present on the board.
 2020-03-31 17:18:20 +02:00
Dylan Laduranty
7a095a80d7 cpu/sam0: use generic hw fc module 2020-03-10 14:22:34 +01:00