If the same callback function is used for multiple interfaces
(`NETDEV_INDEX_ANY`), it is necessary to also provide the index of
the interface to hand out and address.
Add periph_uart_nonblocking. Since cc2538 has a transmit FIFO write
to the FIFO first and to a tsrb buffer only when the transmit FIFO
is full.
Rely on the FIFO TXIFLSEL condition to fill up FIFO as space becomes
available.
Flash Customer Configuration Area (CCA) is never written when the
riotboot module is used. This required a riot application to have
been previously flashed. riotboot will completely ignore this
section, neither writing or erasing it.
Slot flashing is currenly only supported with Jlink.
Co-authored-by: Brenton Chetty <brent7984@gmail.com>
The Watchdog on the CC2538 only supports 4 intervals (2ms, 16ms, 250ms & 1s).
Since the watchdog timer API specifies a `max_time`, the interval equal or
below that time is selected.
E.g. for `max_time=125ms` the 16ms interval would be selected.
This is outside the tolerance of the `tests/periph_wdt` test.
Co-authored-by: Thomas Geithner <thomas.geithner@dai-labor.de>
cc2538 implements 4 sleep modes.
In the lightest mode (3) any interrupt source can wake up the CPU.
In mode 2, only RTT, GPIO or USB may wake the CPU.
In mode 1 only RTT and GPIO can wake the CPU.
In mode 0 only GPIO can wake the CPU.
In mode 0 and 1 the lower 16k RAM are lost. This is a problem since those
are usually used by RIOT.
The linkerscripts in cc2538/ldscripts take different approaches towards that.
Some only use the upper 16k and leave the other half to be managed by the
application.
`cc2538sf53.ld` which is used by `openmote-b` uses the entire RAM starting
at the lower half, so it will not be able to wake up from those modes.
A quick fix to test those modes with `tests/periph_pm` would be
--- a/cpu/cc2538/ldscripts/cc2538sf53.ld
+++ b/cpu/cc2538/ldscripts/cc2538sf53.ld
@@ -21,7 +21,7 @@ MEMORY
{
rom (rx) : ORIGIN = 0x00200000, LENGTH = 512K - 44
cca : ORIGIN = 0x0027ffd4, LENGTH = 44
- ram (w!rx) : ORIGIN = 0x20000000, LENGTH = 32K
+ ram (w!rx) : ORIGIN = 0x20004000, LENGTH = 16K
}
This commit adds the periph_uart_mode USEMODULE
It implements all functionality defined in the common uart driver
This means all parity modes, data bits, and stop bits
Adapt the periph ADC implementation to use vendor defines where
ever possible. Remove duplicate or obsolete defines and adapt
board configuration as required.
Rework SPI periph driver to use proper RIOT GPIO API functions.
Also cleanup header files by using vendor defines and remove
obsolete code. Further, adapt board config accordingly.
The SPI bus frequency/clock is calculated relative to the MCUs
core clock. Currently all boards use the default 32MHz, hence
prescaler settings for SPI are all the same. This PR moves the
default config for 32MHz to the CPU and allows to be overriden
by board config if needed.
Remove unused or obsolete defines in headers, due to usage of
vendor headers. Also remove register bit definition in timer
struct because they where not used in the implementation.
Currently the cc2538 is based on from-scratch adaption which is
not feature complete and thus lacks defines etc. Introducing the
official vendor header will ease future extension and adaptions
of the CPU and its features.
