1
0
mirror of https://github.com/RIOT-OS/RIOT.git synced 2024-12-29 04:50:03 +01:00
Commit Graph

21 Commits

Author SHA1 Message Date
Jean-Pierre De Jesus DIAZ
0d9f6ca3f4 cpu/cc26xx_cc13xx: fix doxygen grouping warnings
Signed-off-by: Jean-Pierre De Jesus DIAZ <me@jeandudey.tech>
2021-09-11 12:45:15 +02:00
Jan Romann
4384795cb9
treewide: Remove excessive newlines 2021-08-13 19:50:38 +02:00
Jean Pierre Dudey
f443a8bc84 cpu/cc26xx_cc13xx: enable periph clocks on sleep
Signed-off-by: Jean Pierre Dudey <me@jeandudey.tech>
2020-10-01 18:38:03 -05:00
Jean Pierre Dudey
447cdebd26 cpu/cc26xx_cc13xx: add & link CCFG configuration
> Allows flahsing CCFG configuration using Kconfig,
formely "make menuconfig".
> Supports cc26x0, cc26x2_cc13x2.
> Can be used to enable bootloader backdoor, to use
cc2538-bsl flashing script.
> Not all options are in Kconfig, most important ones,
others can be added in further commits.
> On cc13xx targets the VDDR high option can be enabled
using Kconfig.
> With this, RIOT can flash blank chips and the firmware
will run just fine.

Signed-off-by: Jean Pierre Dudey <me@jeandudey.tech>
2020-09-27 17:58:11 -05:00
Benjamin Valentin
098b37a7dc cpu/cc26x2_cc13x2: set CPU_HAS_BITBAND
> Bit-banding is supported in order to reduce the execution time for
> read-modify-write (RMW) operations to memory.
> With bit-banding, certain regions in the memory map
> (SRAM and peripheral space) can use address aliases to access
> individual bits in one atomic operation.

https://www.ti.com/lit/ug/swcu185d/swcu185d.pdf
2020-08-08 12:44:11 +02:00
Jean Pierre Dudey
a66c693ad5
cc26x2_cc13x2: add oscillator switching functions
Signed-off-by: Jean Pierre Dudey <jeandudey@hotmail.com>
2020-05-02 13:25:41 -05:00
Jean Pierre Dudey
951a99dba3
cc26x2_cc13x2: add setup_trim_device function
This function trims the necessary registers for the device to operate
normally.

Signed-off-by: Jean Pierre Dudey <jeandudey@hotmail.com>
2020-04-29 18:32:58 -05:00
Jean Pierre Dudey
dc1d2ace42
cc26xx_cc13xx: add ADI3 and masked access
- Added ADI instruction offsets
- Added register banks and address bases for masked access (writes).

Signed-off-by: Jean Pierre Dudey <jeandudey@hotmail.com>
2020-04-29 18:32:58 -05:00
Jean Pierre Dudey
92589c2129
cc26x2_cc13x2: update AON_PMCTL register bank
- Updated documentation.
- Fixed offset of JTAGUSERCODE.
- Added necessary register values to perform startup trims.

Signed-off-by: Jean Pierre Dudey <jeandudey@hotmail.com>
2020-04-29 18:16:45 -05:00
Jean Pierre Dudey
e514266186
cc26x2_cc13x2: add FCFG->DAC_BIAS_CNF values
These are necessary to trim some registers at startup.

Signed-off-by: Jean Pierre Dudey <jeandudey@hotmail.com>
2020-04-29 18:16:45 -05:00
Jean Pierre Dudey
cdf2e88804
cc26x2_cc13x2: add 16-bit masked access to DDI_0_OSC
Signed-off-by: Jean Pierre Dudey <jeandudey@hotmail.com>
2020-04-29 18:16:45 -05:00
Jean Pierre Dudey
1586c89f1a
cc26x2_cc13x2: update DDI_0_OSC register bank
- Fixes padding.
- Updates documentation.
- Removes documentation longer than 80-chars for the registers values.

Signed-off-by: Jean Pierre Dudey <jeandudey@hotmail.com>
2020-04-29 10:17:20 -05:00
Jean Pierre Dudey
2921944c66
cc26x2_cc13x2: add function to change AUX opmode
This function is needed to setup the AUX operational mode at startup,
also used for managing low-power states.

Signed-off-by: Jean Pierre Dudey <jeandudey@hotmail.com>
2020-04-29 09:38:36 -05:00
Jean Pierre Dudey
81d0d7c1f8
cc26x2_cc13x2: update AUX domain documentation
The following registers were updated:

- AIO_AIODIOx documentation
- AUX_TDC documentation
- AUX_EVCTL documentation
- AUX_SYSIF documentation
  - Fixed a copy/paste error in AUX_SYSIF definition.
  - Registers now match original names.
- AUX_TIMER01 documentation
- AUX_TIMER2 documentation
- AUX_SMPH documentation
- AUX_ANAIF documentation
- update ADI_4_AUX documentation
  - Added missing LPMBIAS register
- ADDI_SEM documentation

Signed-off-by: Jean Pierre Dudey <jeandudey@hotmail.com>
2020-04-26 09:35:26 -05:00
benpicco
91200aa6ea
Merge pull request #13867 from btcven/2020_04_14-ccfg-fcfg1
cc26xx_cc13xx: fix CCFG/FCFG1 register offsets
2020-04-15 17:33:12 +02:00
Jean Pierre Dudey
e944638d3d
cc26x2_cc13x2: fix FCFG1 register offsets
Signed-off-by: Jean Pierre Dudey <jeandudey@hotmail.com>
2020-04-14 17:22:02 -05:00
Jean Pierre Dudey
d4084d6df9
cc26xx_cc13xx: fix UART1 initialization
Signed-off-by: Jean Pierre Dudey <jeandudey@hotmail.com>
2020-04-08 12:24:02 -05:00
Jean Pierre Dudey
ffa5005021
cc26xx_cc13xx: add API to manage peripheral clocks
Signed-off-by: Jean Pierre Dudey <jeandudey@hotmail.com>
2020-03-23 09:33:53 -05:00
Jean Pierre Dudey
c6e4768997
cc26xx_cc13xx: add PRCM_NONBUF register bank
Signed-off-by: Jean Pierre Dudey <jeandudey@hotmail.com>
2020-03-23 09:33:23 -05:00
Jean Pierre Dudey
1bb689ff45
cc26x2_cc13x2: add AON_RTC definitions
Signed-off-by: Jean Pierre Dudey <jeandudey@hotmail.com>
2020-03-16 19:36:54 -05:00
Jean Pierre Dudey
a73f3809cc
cpu/cc13x2: rename cc13x2 cpu to cc26x2_cc13x2
The CC26x2 and CC13x2 share the same register definitions, and both are
treated equally in the TI's technical reference manual. [1]

- To avoid confusions in the future I renamed it to `cc26x2_cc13x2`.
- Documentation was updated.
- The `cc1312-launchpad` board that uses the `cc13x2` MCU was updated.
- The `cc1352-launchpad` board that uses the `cc13x2` MCU was updated.

[1]: https://www.ti.com/lit/ug/swcu185d/swcu185d.pdf

Signed-off-by: Jean Pierre Dudey <jeandudey@hotmail.com>
2020-01-20 09:31:48 -05:00