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https://github.com/RIOT-OS/RIOT.git
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cpu/cc26xx_cc13xx: fix doxygen grouping warnings
Signed-off-by: Jean-Pierre De Jesus DIAZ <me@jeandudey.tech>
This commit is contained in:
Jean-Pierre De Jesus DIAZ
parent
35d1a2fc02
commit
0d9f6ca3f4
@ -5,6 +5,7 @@
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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/**
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* @ingroup cpu_cc26x0_cc13x0_definitions
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* @{
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@ -25,7 +26,7 @@ extern "C" {
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#endif
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/**
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* AUX_AIODIO registers
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* @brief AUX_AIODIO registers
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*/
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typedef struct {
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reg32_t GPIODOUT; /**< gpio data out */
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@ -37,9 +38,10 @@ typedef struct {
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reg32_t GPIODIE; /**< gpio data input enable */
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} aux_aiodio_regs_t;
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/** @ingroup cpu_specific_peripheral_memory_map
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* @{
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*/
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/**
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* @ingroup cpu_specific_peripheral_memory_map
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* @{
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*/
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#define AUX_AIODIO0_BASE 0x400C1000 /**< AUX_AIODIO0 base address */
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#define AUX_AIODIO1_BASE 0x400C2000 /**< AUX_AIODIO1 base address */
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/** @} */
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@ -48,7 +50,7 @@ typedef struct {
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#define AUX_AIODIO1 ((aux_aiodio_regs_t *) (AUX_AIODIO1_BASE)) /**< AUX_AIODIO1 register bank */
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/**
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* AUX_TDC registers
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* @brief AUX_TDC registers
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*/
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typedef struct {
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reg32_t CTL; /**< control */
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@ -63,16 +65,17 @@ typedef struct {
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reg32_t PRECNT; /**< prescaler counter */
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} aux_tdc_regs_t;
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/** @ingroup cpu_specific_peripheral_memory_map
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* @{
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*/
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/**
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* @ingroup cpu_specific_peripheral_memory_map
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* @{
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*/
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#define AUX_TDC_BASE 0x400C4000 /**< AUX_TDC base address */
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/** @} */
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#define AUX_TDC ((aux_tdc_regs_t *) (AUX_TDC_BASE)) /**< AUX_TDC register bank */
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/**
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* AUX_EVCTL registers
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* @brief AUX_EVCTL registers
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*/
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typedef struct {
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reg32_t VECCFG0; /**< vector config 0 */
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@ -94,9 +97,10 @@ typedef struct {
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reg32_t VECFLAGSCLR; /**< vector flags clear */
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} aux_evtcl_regs_t;
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/** @ingroup cpu_specific_peripheral_memory_map
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* @{
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*/
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/**
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* @ingroup cpu_specific_peripheral_memory_map
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* @{
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*/
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#define AUX_EVCTL_BASE 0x400C5000 /**< AUX_EVCTL base address */
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/** @} */
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@ -142,16 +146,17 @@ typedef struct {
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#define MODCLKEN0_AUX_ADI4_EN 0x00000080 /* enable clock for AUX_ADI4 */
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/** @} */
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/** @ingroup cpu_specific_peripheral_memory_map
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* @{
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*/
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/**
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* @ingroup cpu_specific_peripheral_memory_map
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* @{
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*/
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#define AUX_WUC_BASE 0x400C6000 /**< AUX_WUC base address */
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/** @} */
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#define AUX_WUC ((aux_wuc_regs_t *) (AUX_WUC_BASE)) /**< AUX_WUC register bank */
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/**
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* AUX_TIMER registers
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* @brief AUX_TIMER registers
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*/
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typedef struct {
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reg32_t T0CFG; /**< timer 0 config */
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@ -162,9 +167,10 @@ typedef struct {
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reg32_t T1CTL; /**< timer 1 control */
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} aux_timer_regs_t;
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/** @ingroup cpu_specific_peripheral_memory_map
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* @{
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*/
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/**
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* @ingroup cpu_specific_peripheral_memory_map
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* @{
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*/
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#define AUX_TIMER_BASE 0x400C7000 /**< AUX_WUC base address */
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/** @} */
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@ -185,11 +191,12 @@ typedef struct {
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reg32_t AUTOTAKE; /**< sticky request for single semaphore */
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} aux_smph_regs_t;
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/** @ingroup cpu_specific_peripheral_memory_map
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* @{
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*/
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/**
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* @ingroup cpu_specific_peripheral_memory_map
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* @{
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*/
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#define AUX_SMPH_BASE 0x400C8000 /**< AUX_WUC base address */
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/* @} */
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/** @} */
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#define AUX_SMPH ((aux_smph_regs_t *) (AUX_SMPH_BASE)) /**< AUX_SMPH register bank */
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@ -205,9 +212,10 @@ typedef struct {
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reg32_t ISRCCTL; /**< current source control */
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} aux_anaif_regs_t;
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/** @ingroup cpu_specific_peripheral_memory_map
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* @{
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*/
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/**
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* @ingroup cpu_specific_peripheral_memory_map
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* @{
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*/
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#define AUX_ANAIF_BASE 0x400C9000 /**< AUX_WUC base address */
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/** @} */
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@ -230,9 +238,10 @@ typedef struct {
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reg8_t ADCREF1; /**< ADC reference 1 */
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} adi_4_aux_regs_t;
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/** @ingroup cpu_specific_peripheral_memory_map
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* @{
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*/
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/**
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* @ingroup cpu_specific_peripheral_memory_map
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* @{
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*/
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#define ADI_4_AUX_BASE 0x400CB000 /**< AUX_WUC base address */
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/** @} */
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@ -245,4 +254,4 @@ typedef struct {
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#endif
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#endif /* CC26X0_CC13X0_AUX_H */
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/** @}*/
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/** @} */
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@ -5,6 +5,7 @@
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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/**
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* @ingroup cpu_cc26x0_cc13x0_definitions
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* @{
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@ -22,20 +23,24 @@
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extern "C" {
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#endif
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/** @ingroup cpu_specific_peripheral_memory_map
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/**
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* @ingroup cpu_specific_peripheral_memory_map
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* @{
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*/
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#define FCFG_BASE 0x50001000 /**< base address of FCFG memory */
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/*@}*/
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/**
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* @brief Base address of FCFG memory
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*/
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#define FCFG_BASE (0x50001000)
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/** @} */
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/**
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* FCFG registers
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* @brief FCFG registers
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*/
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typedef struct {
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uint8_t __reserved1[0xA0]; /**< meh */
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uint8_t __reserved1[0xA0]; /**< Reserved */
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/* TODO does it pad here? */
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reg32_t MISC_CONF_1; /**< misc config */
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reg32_t __reserved2[8]; /**< meh */
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reg32_t __reserved2[8]; /**< Reserved */
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reg32_t CONFIG_RF_FRONTEND_DIV5; /**< config of RF frontend in divide-by-5 mode */
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reg32_t CONFIG_RF_FRONTEND_DIV6; /**< config of RF frontend in divide-by-6 mode */
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reg32_t CONFIG_RF_FRONTEND_DIV10; /**< config of RF frontend in divide-by-10 mode */
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@ -54,15 +59,15 @@ typedef struct {
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reg32_t CONFIG_MISC_ADC_DIV12; /**< config of IFADC in divide-by-12-mode */
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reg32_t CONFIG_MISC_ADC_DIV15; /**< config of IFADC in divide-by-15-mode */
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reg32_t CONFIG_MISC_ADC_DIV30; /**< config of IFADC in divide-by-30-mode */
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reg32_t __reserved3[3]; /**< meh */
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reg32_t __reserved3[3]; /**< Reserved */
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reg32_t SHDW_DIE_ID_0; /**< shadow of JTAG_TAP::EFUSE::DIE_ID_0.* */
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reg32_t SHDW_DIE_ID_1; /**< shadow of JTAG_TAP::EFUSE::DIE_ID_1.* */
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reg32_t SHDW_DIE_ID_2; /**< shadow of JTAG_TAP::EFUSE::DIE_ID_2.* */
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reg32_t SHDW_DIE_ID_3; /**< shadow of JTAG_TAP::EFUSE::DIE_ID_3.* */
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reg32_t __reserved4[4]; /**< meh */
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reg32_t __reserved4[4]; /**< Reserved */
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reg32_t SHDW_OSC_BIAS_LDO_TRIM; /**< shadow of JTAG_TAP::EFUSE::BIAS_LDO_TIM.* */
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reg32_t SHDW_ANA_TRIM; /**< shadow of JTAG_TAP::EFUSE::ANA_TIM.* */
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reg32_t __reserved5[9]; /**< meh */
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reg32_t __reserved5[9]; /**< Reserved */
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reg32_t FLASH_NUMBER; /**< number of manufactoring lot that produced this unit */
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reg32_t FLASH_COORDINATE; /**< X and Y coordinates of this unit on the wafer */
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reg32_t FLASH_E_P; /**< flash erase and program setup time */
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@ -76,35 +81,35 @@ typedef struct {
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reg32_t FLASH_VHV; /**< flash VHV */
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reg32_t FLASH_VHV_PV; /**< flash VHV program verify */
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reg32_t FLASH_V; /**< flash voltages */
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reg32_t __reserved6[0x3E]; /**< meh */
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reg32_t __reserved6[0x3E]; /**< Reserved */
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reg32_t USER_ID; /**< user identification */
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reg32_t __reserved7[6]; /**< meh */
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reg32_t __reserved7[6]; /**< Reserved */
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reg32_t FLASH_OTP_DATA3; /**< flash OTP data 3 */
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reg32_t ANA2_TRIM; /**< misc analog trim */
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reg32_t LDO_TRIM; /**< LDO trim */
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reg32_t __reserved8[0xB]; /**< meh */
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reg32_t __reserved8[0xB]; /**< Reserved */
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reg32_t MAC_BLE_0; /**< MAC BLE address 0 */
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reg32_t MAC_BLE_1; /**< MAC BLE address 1 */
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reg32_t MAC_15_4_0; /**< MAC IEEE 820.15.4 address 0 */
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reg32_t MAC_15_4_1; /**< MAC IEEE 820.15.4 address 1 */
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reg32_t __reserved9[4]; /**< meh */
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reg32_t __reserved9[4]; /**< Reserved */
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reg32_t FLASH_OTP_DATA4; /**< flash OTP data 4 */
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reg32_t MISC_TRIM; /**< misc trim parameters */
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reg32_t RCOSC_HF_TEMPCOMP; /**< RFOSC HF temperature compensation */
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reg32_t __reserved10; /**< meh */
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reg32_t __reserved10; /**< Reserved */
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reg32_t ICEPICK_DEVICE_ID; /**< IcePick device identification */
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reg32_t FCFG1_REVISION; /**< FCFG1 revision */
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reg32_t MISC_OTP_DATA; /**< misc OTP data */
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reg32_t __reserved11[8]; /**< meh */
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reg32_t __reserved11[8]; /**< Reserved */
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reg32_t IOCONF; /**< IO config */
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reg32_t __reserved12; /**< meh */
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reg32_t __reserved12; /**< Reserved */
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reg32_t CONFIG_IF_ADC; /**< config of IF_ADC */
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reg32_t CONFIG_OSC_TOP; /**< config of OSC */
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reg32_t CONFIG_RF_FRONTEND; /**< config of RF frontend in dividy-by-2-mode */
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reg32_t CONFIG_SYNTH; /**< config of synthesizer in dividy-by-2-mode */
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reg32_t SOC_ADC_ABS_GAIN; /**< AUX_ADC gain in absolute reference mode */
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reg32_t SOC_ADC_REL_GAIN; /**< AUX_ADC gain in relative reference mode */
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reg32_t __reserved13; /**< meh */
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reg32_t __reserved13; /**< Reserved */
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reg32_t SOC_ADC_OFFSET_INT; /**< AUX_ADC temperature offsets in absolute reference mode */
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reg32_t SOC_ADC_REF_TRIM_AND_OFFSET_EXT; /**< AUX_ADC reference trim and offset of external reference mode */
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reg32_t AMPCOMP_TH1; /**< amplitude compensation threshold 1 */
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@ -112,10 +117,10 @@ typedef struct {
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reg32_t AMPCOMP_CTRL1; /**< amplitude compensation control */
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reg32_t ANABYPASS_VALUE2; /**< analog bypass value for OSC */
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reg32_t CONFIG_MISC_ADC; /**< config of IFADC in divide-by-2-mode */
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reg32_t __reserved14; /**< meh */
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reg32_t __reserved14; /**< Reserved */
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reg32_t VOLT_TRIM; /**< voltage trim */
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reg32_t OSC_CONF; /**< OSC configuration */
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reg32_t __reserved15; /**< meh */
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reg32_t __reserved15; /**< Reserved */
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reg32_t CAP_TRIM; /**< capacitor trim (it says 'capasitor' in the manual - if you know what that is ;-) */
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reg32_t MISC_OTP_DATA_1; /**< misc OSC control */
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reg32_t PWD_CURR_20C; /**< power down current control 20C */
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@ -128,7 +133,10 @@ typedef struct {
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reg32_t PWD_CURR_125C; /**< power down current control 125C */
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} fcfg_regs_t;
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#define FCFG ((fcfg_regs_t *) (FCFG_BASE)) /**< FCFG register bank */
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/**
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* @brief FCFG register bank
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*/
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#define FCFG ((fcfg_regs_t *) (FCFG_BASE)
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#ifdef __cplusplus
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} /* end extern "C" */
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@ -24,7 +24,7 @@ extern "C" {
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#endif
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/**
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* DDI_0_OSC registers
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* @brief DDI_0_OSC registers
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*/
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typedef struct {
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reg32_t CTL0; /**< control 0 */
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@ -69,16 +69,20 @@ typedef struct {
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#define DDI_0_OSC_CTL0_XTAL_IS_24M 0x80000000
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/** @} */
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/** @ingroup cpu_specific_peripheral_memory_map
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* @{
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*/
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/**
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* @ingroup cpu_specific_peripheral_memory_map
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* @{
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*/
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#define DDI0_OSC_BASE 0x400CA000 /**< DDI0_OSC base address */
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/*@}*/
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#define DDI_0_OSC ((ddi0_osc_regs_t *) (DDI0_OSC_BASE)) /**< DDI_0_OSC register bank */
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/** @} */
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/**
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* AON_SYSCTL registers
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* @brief DDI_0_OSC register bank
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*/
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#define DDI_0_OSC ((ddi0_osc_regs_t *) (DDI0_OSC_BASE))
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/**
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* @brief AON_SYSCTL registers
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*/
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typedef struct {
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reg32_t PWRCTL; /**< power management */
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@ -86,16 +90,17 @@ typedef struct {
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reg32_t SLEEPCTL; /**< sleep mode */
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} aon_sysctl_regs_t;
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/** @ingroup cpu_specific_peripheral_memory_map
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* @{
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*/
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/**
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* @ingroup cpu_specific_peripheral_memory_map
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* @{
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*/
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#define AON_SYSCTL_BASE 0x40090000 /**< AON_SYSCTL base address */
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/*@}*/
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/** @} */
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#define AON_SYSCTL ((aon_sysctl_regs_t *) (AON_SYSCTL_BASE)) /**< AON_SYSCTL register bank */
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/**
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* AON_WUC registers
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* @brief AON_WUC registers
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*/
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typedef struct {
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reg32_t MCUCLK; /**< MCU clock management */
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@ -104,14 +109,14 @@ typedef struct {
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reg32_t AUXCFG; /**< AUX config */
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reg32_t AUXCTL; /**< AUX control */
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reg32_t PWRSTAT; /**< power status */
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reg32_t __reserved1; /**< meh */
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reg32_t __reserved1; /**< Reserved */
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reg32_t SHUTDOWN; /**< shutdown control */
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reg32_t CTL0; /**< control 0 */
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reg32_t CTL1; /**< control 1 */
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reg32_t __reserved2[2]; /**< meh */
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reg32_t __reserved2[2]; /**< Reserved */
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reg32_t RECHARGECFG; /**< recharge controller config */
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reg32_t RECHARGESTAT; /**< recharge controller status */
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reg32_t __reserved3; /**< meh */
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reg32_t __reserved3; /**< Reserved */
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reg32_t OSCCFG; /**< oscillator config */
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reg32_t JTAGCFG; /**< JTAG config */
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reg32_t JTAGUSERCODE; /**< JTAG USERCODE */
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@ -181,16 +186,17 @@ typedef struct {
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#define JTAGCFG_JTAG_PD_FORCE_ON 0x10
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/** @} */
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/** @ingroup cpu_specific_peripheral_memory_map
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* @{
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*/
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/**
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* @ingroup cpu_specific_peripheral_memory_map
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* @{
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*/
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#define AON_WUC_BASE 0x40091000 /**< AON_WUC base address */
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/*@}*/
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/** @} */
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#define AON_WUC ((aon_wuc_regs_t *) (AON_WUC_BASE)) /**< AON_WUC register bank */
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/**
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* AON_RTC registers
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* @brief AON_RTC registers
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*/
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typedef struct {
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reg32_t CTL; /**< Control */
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@ -215,27 +221,28 @@ typedef struct {
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*/
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#define AON_RTC_CTL_RTC_UPD_EN 0x00000002
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/** @ingroup cpu_specific_peripheral_memory_map
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* @{
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*/
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/**
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* @ingroup cpu_specific_peripheral_memory_map
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* @{
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*/
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#define AON_RTC_BASE (PERIPH_BASE + 0x92000) /**< AON_RTC base address */
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/** @} */
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#define AON_RTC ((aon_rtc_regs_t *) (AON_RTC_BASE)) /**< AON_RTC register bank */
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/**
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* PRCM registers
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* @brief PRCM registers
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*/
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typedef struct {
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reg32_t INFRCLKDIVR; /**< infrastructure clock division factor for run mode */
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reg32_t INFRCLKDIVS; /**< infrastructure clock division factor for sleep mode */
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reg32_t INFRCLKDIVDS; /**< infrastructure clock division factor for deep sleep mode */
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reg32_t VDCTL; /**< MCU voltage domain control */
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reg32_t __reserved1[6]; /**< meh */
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reg32_t __reserved1[6]; /**< Reserved */
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reg32_t CLKLOADCTL; /**< clock load control */
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reg32_t RFCCLKG; /**< RFC clock gate */
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reg32_t VIMSCLKG; /**< VIMS clock gate */
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reg32_t __reserved2[2]; /**< meh */
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reg32_t __reserved2[2]; /**< Reserved */
|
||||
reg32_t SECDMACLKGR; /**< TRNG, CRYPTO, and UDMA clock gate for run mode */
|
||||
reg32_t SECDMACLKGS; /**< TRNG, CRYPTO, and UDMA clock gate for sleep mode */
|
||||
reg32_t SECDMACLKGDS; /**< TRNG, CRYPTO, and UDMA clock gate for deep sleep mode */
|
||||
@ -257,47 +264,47 @@ typedef struct {
|
||||
reg32_t I2SCLKGR; /**< I2S clock gate for run mode */
|
||||
reg32_t I2SCLKGS; /**< I2S clock gate for sleep mode */
|
||||
reg32_t I2SCLKGDS; /**< I2S clock gate for deep sleep mode */
|
||||
reg32_t __reserved3[10]; /**< meh */
|
||||
reg32_t __reserved3[10]; /**< Reserved */
|
||||
reg32_t CPUCLKDIV; /**< CPU clock division factor */
|
||||
reg32_t __reserved4[3]; /**< meh */
|
||||
reg32_t __reserved4[3]; /**< Reserved */
|
||||
reg32_t I2SBCLKSEL; /**< I2S clock select */
|
||||
reg32_t GPTCLKDIV; /**< GPT scalar */
|
||||
reg32_t I2SCLKCTL; /**< I2S clock control */
|
||||
reg32_t I2SMCLKDIV; /**< MCLK division ratio */
|
||||
reg32_t I2SBCLKDIV; /**< BCLK division ratio */
|
||||
reg32_t I2SWCLKDIV; /**< WCLK division ratio */
|
||||
reg32_t __reserved5[11]; /**< meh */
|
||||
reg32_t __reserved5[11]; /**< Reserved */
|
||||
reg32_t SWRESET; /**< SW initiated resets */
|
||||
reg32_t WARMRESET; /**< WARM reset control and status */
|
||||
reg32_t __reserved6[6]; /**< meh */
|
||||
reg32_t __reserved6[6]; /**< Reserved */
|
||||
reg32_t PDCTL0; /**< power domain control */
|
||||
reg32_t PDCTL0RFC; /**< RFC power domain control */
|
||||
reg32_t PDCTL0SERIAL; /**< SERIAL power domain control */
|
||||
reg32_t PDCTL0PERIPH; /**< PERIPH power domain control */
|
||||
reg32_t __reserved7; /**< meh */
|
||||
reg32_t __reserved7; /**< Reserved */
|
||||
reg32_t PDSTAT0; /**< power domain status */
|
||||
reg32_t PDSTAT0RFC; /**< RFC power domain status */
|
||||
reg32_t PDSTAT0SERIAL; /**< SERIAL power domain status */
|
||||
reg32_t PDSTAT0PERIPH; /**< PERIPH power domain status */
|
||||
reg32_t __reserved8[11]; /**< meh */
|
||||
reg32_t __reserved8[11]; /**< Reserved */
|
||||
reg32_t PDCTL1; /**< power domain control */
|
||||
reg32_t __reserved9; /**< power domain control */
|
||||
reg32_t PDCTL1CPU; /**< CPU power domain control */
|
||||
reg32_t PDCTL1RFC; /**< RFC power domain control */
|
||||
reg32_t PDCTL1VIMS; /**< VIMS power domain control */
|
||||
reg32_t __reserved10; /**< meh */
|
||||
reg32_t __reserved10; /**< Reserved */
|
||||
reg32_t PDSTAT1; /**< power domain status */
|
||||
reg32_t PDSTAT1BUS; /**< BUS power domain status */
|
||||
reg32_t PDSTAT1RFC; /**< RFC power domain status */
|
||||
reg32_t PDSTAT1CPU; /**< CPU power domain status */
|
||||
reg32_t PDSTAT1VIMS; /**< VIMS power domain status */
|
||||
reg32_t __reserved11[10]; /**< meh */
|
||||
reg32_t __reserved11[10]; /**< Reserved */
|
||||
reg32_t RFCMODESEL; /**< selected RFC mode */
|
||||
reg32_t __reserved12[20]; /**< meh */
|
||||
reg32_t __reserved12[20]; /**< Reserved */
|
||||
reg32_t RAMRETEN; /**< memory retention control */
|
||||
reg32_t __reserved13; /**< meh */
|
||||
reg32_t __reserved13; /**< Reserved */
|
||||
reg32_t PDRETEN; /**< power domain retention (undocumented) */
|
||||
reg32_t __reserved14[8]; /**< meh */
|
||||
reg32_t __reserved14[8]; /**< Reserved */
|
||||
reg32_t RAMHWOPT; /**< undocumented */
|
||||
} prcm_regs_t;
|
||||
|
||||
@ -337,12 +344,13 @@ typedef struct {
|
||||
#define UARTCLKGDS_CLK_EN_UART0 0x1
|
||||
/** @} */
|
||||
|
||||
/** @ingroup cpu_specific_peripheral_memory_map
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @ingroup cpu_specific_peripheral_memory_map
|
||||
* @{
|
||||
*/
|
||||
#define PRCM_BASE (PERIPH_BASE + 0x82000) /**< PRCM base address */
|
||||
#define PRCM_BASE_NONBUF (PERIPH_BASE_NONBUF + 0x82000) /**< PRCM base address (nonbuf) */
|
||||
/*@}*/
|
||||
/** @} */
|
||||
|
||||
#define PRCM ((prcm_regs_t *) (PRCM_BASE)) /**< PRCM register bank */
|
||||
#define PRCM_NONBUF ((prcm_regs_t *) (PRCM_BASE_NONBUF)) /**< PRCM register bank (nonbuf) */
|
||||
|
||||
@ -247,11 +247,11 @@ typedef struct {
|
||||
reg32_t INFRCLKDIVS; /**< infrastructure clock division factor for sleep mode */
|
||||
reg32_t INFRCLKDIVDS; /**< infrastructure clock division factor for deep sleep mode */
|
||||
reg32_t VDCTL; /**< MCU voltage domain control */
|
||||
reg32_t __reserved1[6]; /**< meh */
|
||||
reg32_t __reserved1[6]; /**< Reserved */
|
||||
reg32_t CLKLOADCTL; /**< clock load control */
|
||||
reg32_t RFCCLKG; /**< RFC clock gate */
|
||||
reg32_t VIMSCLKG; /**< VIMS clock gate */
|
||||
reg32_t __reserved2[2]; /**< meh */
|
||||
reg32_t __reserved2[2]; /**< Reserved */
|
||||
reg32_t SECDMACLKGR; /**< TRNG, CRYPTO, and UDMA clock gate for run mode */
|
||||
reg32_t SECDMACLKGS; /**< TRNG, CRYPTO, and UDMA clock gate for sleep mode */
|
||||
reg32_t SECDMACLKGDS; /**< TRNG, CRYPTO, and UDMA clock gate for deep sleep mode */
|
||||
@ -273,11 +273,11 @@ typedef struct {
|
||||
reg32_t I2SCLKGR; /**< I2S clock gate for run mode */
|
||||
reg32_t I2SCLKGS; /**< I2S clock gate for sleep mode */
|
||||
reg32_t I2SCLKGDS; /**< I2S clock gate for deep sleep mode */
|
||||
reg32_t __reserved3[9]; /**< meh */
|
||||
reg32_t __reserved3[9]; /**< Reserved */
|
||||
reg32_t SYSBUSCLKDIV; /**< System bus clock division factor */
|
||||
reg32_t CPUCLKDIV; /**< CPU clock division factor */
|
||||
reg32_t PERBUSCPUCLKDIV; /**< Peripheral bus division factor */
|
||||
reg32_t __reserved4; /**< meh */
|
||||
reg32_t __reserved4; /**< Reserved */
|
||||
reg32_t PERDMACLKDIV; /**< DMA clock division factor */
|
||||
reg32_t I2SBCLKSEL; /**< I2S clock select */
|
||||
reg32_t GPTCLKDIV; /**< GPT scalar */
|
||||
@ -285,7 +285,7 @@ typedef struct {
|
||||
reg32_t I2SMCLKDIV; /**< MCLK division ratio */
|
||||
reg32_t I2SBCLKDIV; /**< BCLK division ratio */
|
||||
reg32_t I2SWCLKDIV; /**< WCLK division ratio */
|
||||
reg32_t __reserved5[4]; /**< meh */
|
||||
reg32_t __reserved5[4]; /**< Reserved */
|
||||
reg32_t RESETSECDMA; /**< Reset SEC and UDMA */
|
||||
reg32_t RESETGPIO; /**< Reset GPIO */
|
||||
reg32_t RESETGPT; /**< Reset GPTs */
|
||||
@ -293,39 +293,39 @@ typedef struct {
|
||||
reg32_t RESETUART; /**< Reset UART */
|
||||
reg32_t RESETSSI; /**< Reset SSI */
|
||||
reg32_t RESETI2S; /**< Reset I2S */
|
||||
reg32_t __reserved6[8]; /**< meh */
|
||||
reg32_t __reserved6[8]; /**< Reserved */
|
||||
reg32_t PDCTL0; /**< power domain control */
|
||||
reg32_t PDCTL0RFC; /**< RFC power domain control */
|
||||
reg32_t PDCTL0SERIAL; /**< SERIAL power domain control */
|
||||
reg32_t PDCTL0PERIPH; /**< PERIPH power domain control */
|
||||
reg32_t __reserved7; /**< meh */
|
||||
reg32_t __reserved7; /**< Reserved */
|
||||
reg32_t PDSTAT0; /**< power domain status */
|
||||
reg32_t PDSTAT0RFC; /**< RFC power domain status */
|
||||
reg32_t PDSTAT0SERIAL; /**< SERIAL power domain status */
|
||||
reg32_t PDSTAT0PERIPH; /**< PERIPH power domain status */
|
||||
reg32_t __reserved8[11]; /**< meh */
|
||||
reg32_t __reserved8[11]; /**< Reserved */
|
||||
reg32_t PDCTL1; /**< power domain control */
|
||||
reg32_t __reserved9; /**< power domain control */
|
||||
reg32_t PDCTL1CPU; /**< CPU power domain control */
|
||||
reg32_t PDCTL1RFC; /**< RFC power domain control */
|
||||
reg32_t PDCTL1VIMS; /**< VIMS power domain control */
|
||||
reg32_t __reserved10; /**< meh */
|
||||
reg32_t __reserved10; /**< Reserved */
|
||||
reg32_t PDSTAT1; /**< power domain status */
|
||||
reg32_t PDSTAT1BUS; /**< BUS power domain status */
|
||||
reg32_t PDSTAT1RFC; /**< RFC power domain status */
|
||||
reg32_t PDSTAT1CPU; /**< CPU power domain status */
|
||||
reg32_t PDSTAT1VIMS; /**< VIMS power domain status */
|
||||
reg32_t __reserved11[9]; /**< meh */
|
||||
reg32_t __reserved11[9]; /**< Reserved */
|
||||
reg32_t RFCBITS; /**< Control to RFC */
|
||||
reg32_t RFCMODESEL; /**< selected RFC mode */
|
||||
reg32_t RFCMODEHWOPT; /**< allowed RFC modes */
|
||||
reg32_t __reserved12[2]; /**< meh */
|
||||
reg32_t __reserved12[2]; /**< Reserved */
|
||||
reg32_t PWRPROFSTAT; /**< power profiler register */
|
||||
reg32_t __reserved13[14]; /**< meh */
|
||||
reg32_t __reserved13[14]; /**< Reserved */
|
||||
reg32_t MCUSRAMCFG; /**< MCU SRAM configuration */
|
||||
reg32_t __reserved14; /**< meh */
|
||||
reg32_t __reserved14; /**< Reserved */
|
||||
reg32_t RAMRETEN; /**< memory retention control */
|
||||
reg32_t __reserved15[27]; /**< meh */
|
||||
reg32_t __reserved15[27]; /**< Reserved */
|
||||
reg32_t OSCIMSC; /**< oscillator interrupt mask */
|
||||
reg32_t OSCRIS; /**< oscillator raw interrupt status */
|
||||
reg32_t OSCICR; /**< oscillator raw interrupt clear */
|
||||
@ -370,12 +370,13 @@ typedef struct {
|
||||
#define UARTCLKGDS_CLK_EN_UART1 0x2
|
||||
/** @} */
|
||||
|
||||
/** @ingroup cpu_specific_peripheral_memory_map
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @ingroup cpu_specific_peripheral_memory_map
|
||||
* @{
|
||||
*/
|
||||
#define PRCM_BASE (PERIPH_BASE + 0x82000) /**< PRCM base address */
|
||||
#define PRCM_BASE_NONBUF (PERIPH_BASE_NONBUF + 0x82000) /**< PRCM base address (nonbuf) */
|
||||
/*@}*/
|
||||
/** @} */
|
||||
|
||||
#define PRCM ((prcm_regs_t *) (PRCM_BASE)) /**< PRCM register bank */
|
||||
#define PRCM_NONBUF ((prcm_regs_t *) (PRCM_BASE_NONBUF)) /**< PRCM register bank (nonbuf) */
|
||||
@ -385,5 +386,4 @@ typedef struct {
|
||||
#endif
|
||||
|
||||
#endif /* CC26X2_CC13X2_PRCM_H */
|
||||
|
||||
/*@}*/
|
||||
/** @} */
|
||||
|
||||
@ -26,8 +26,17 @@
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Unsigned 8-bit register type.
|
||||
*/
|
||||
typedef volatile uint8_t reg8_t;
|
||||
/**
|
||||
* @brief Unsigned 16-bit register type.
|
||||
*/
|
||||
typedef volatile uint16_t reg16_t;
|
||||
/**
|
||||
* @brief Unsigned 32-bit register type.
|
||||
*/
|
||||
typedef volatile uint32_t reg32_t;
|
||||
|
||||
/**
|
||||
@ -51,12 +60,14 @@ typedef struct {
|
||||
reg32_t HIGH; /**< High 16-bit half */
|
||||
} reg32_m16_t;
|
||||
|
||||
/** @addtogroup CC13x2_cmsis CMSIS Definitions */
|
||||
/*@{*/
|
||||
|
||||
/** interrupt number definition */
|
||||
typedef enum IRQn
|
||||
{
|
||||
/**
|
||||
* @addtogroup CC13x2_cmsis CMSIS Definitions
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Interrupt number definition
|
||||
*/
|
||||
typedef enum IRQn {
|
||||
/****** Cortex-M4 Processor Exceptions Numbers ****************************/
|
||||
ResetHandler_IRQn = -15, /**< 1 Reset Handler */
|
||||
NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */
|
||||
@ -119,11 +130,12 @@ typedef enum IRQn
|
||||
|
||||
/**
|
||||
* @brief Configuration of the Cortex-M4 processor and core peripherals
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define __MPU_PRESENT 1 /**< CC13x2 does provide a MPU */
|
||||
#define __NVIC_PRIO_BITS 3 /**< CC13x2 offers priority levels from 0..7 */
|
||||
#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick config is used */
|
||||
/** @} */
|
||||
|
||||
#define RCOSC48M_FREQ 48000000 /**< 48 MHz */
|
||||
#define RCOSC24M_FREQ 24000000 /**< 24 MHz */
|
||||
@ -136,17 +148,18 @@ typedef enum IRQn
|
||||
#else
|
||||
#include <core_cm3.h>
|
||||
#endif
|
||||
/*@}*/
|
||||
/** @} */
|
||||
|
||||
/** @ingroup cpu_specific_peripheral_memory_map
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @ingroup cpu_specific_peripheral_memory_map
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_BASE 0x00000000 /**< FLASH base address */
|
||||
#define PERIPH_BASE 0x40000000 /**< Peripheral base address */
|
||||
#define PERIPH_BASE_NONBUF 0x60000000 /**< Peripheral base address (nonbuf) */
|
||||
#define ROM_HARD_API_BASE 0x10000048 /**< ROM Hard-API base address */
|
||||
#define ROM_API_TABLE ((uint32_t *) 0x10000180) /**< ROM API table */
|
||||
/*@}*/
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @brief ADI master instruction offsets
|
||||
@ -165,5 +178,4 @@ typedef enum IRQn
|
||||
#endif
|
||||
|
||||
#endif /* CC26XX_CC13XX_H */
|
||||
|
||||
/*@}*/
|
||||
/** @} */
|
||||
|
||||
@ -185,9 +185,10 @@ cycle or continues on to a repeated START condition
|
||||
*/
|
||||
#define MCTRL_RUN 0x00000001
|
||||
|
||||
/** @ingroup cpu_specific_peripheral_memory_map
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @ingroup cpu_specific_peripheral_memory_map
|
||||
* @{
|
||||
*/
|
||||
#define I2C_BASE (PERIPH_BASE + 0x2000) /**< I2C base address */
|
||||
/** @} */
|
||||
|
||||
@ -198,5 +199,4 @@ cycle or continues on to a repeated START condition
|
||||
#endif
|
||||
|
||||
#endif /* CC26XX_CC13XX_I2C_H */
|
||||
|
||||
/*@}*/
|
||||
/** @} */
|
||||
|
||||
@ -37,7 +37,7 @@ extern "C" {
|
||||
* @param[in] dio_num DIO number (0-31)
|
||||
*/
|
||||
typedef struct {
|
||||
reg32_t CFG[32]; /**< config */
|
||||
reg32_t CFG[32]; /**< Config */
|
||||
} cc26x0_ioc_regs_t;
|
||||
|
||||
#define IOC ((cc26x0_ioc_regs_t *)(MCU_IOC_BASE)) /**< IOC register banks */
|
||||
@ -53,7 +53,7 @@ typedef struct {
|
||||
#define IOCFG_PORTID_AON_SCK 0x00000002 /**< AON SPI-S SCK */
|
||||
#define IOCFG_PORTID_AON_SDI 0x00000003 /**< AON SPI-S SDI */
|
||||
#define IOCFG_PORTID_AON_SDO 0x00000004 /**< AON SPI-S SDO */
|
||||
#endif //CPU_VARIANT_X0
|
||||
#endif /* CPU_VARIANT_X0 */
|
||||
|
||||
#define IOCFG_PORTID_AON_CLK32K 0x00000007 /**< AON external 32kHz clock */
|
||||
#define IOCFG_PORTID_AUX_IO 0x00000008 /**< AUX IO */
|
||||
@ -183,5 +183,4 @@ typedef struct {
|
||||
#endif
|
||||
|
||||
#endif /* CC26XX_CC13XX_IOC_H */
|
||||
|
||||
/*@}*/
|
||||
/** @} */
|
||||
|
||||
@ -92,5 +92,4 @@ void power_clock_disable_uart(uart_t uart);
|
||||
#endif
|
||||
|
||||
#endif /* CC26XX_CC13XX_POWER_H */
|
||||
|
||||
/*@}*/
|
||||
/** @} */
|
||||
|
||||
@ -168,5 +168,4 @@ typedef struct {
|
||||
#endif
|
||||
|
||||
#endif /* CC26XX_CC13XX_RFC_H */
|
||||
|
||||
/*@}*/
|
||||
/** @} */
|
||||
|
||||
@ -190,7 +190,7 @@ typedef struct {
|
||||
* @brief FLASH base address
|
||||
*/
|
||||
#define FLASH_BASEADDR (PERIPH_BASE + 0x30000)
|
||||
/*@}*/
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @brief FLASH register bank
|
||||
@ -213,7 +213,7 @@ typedef struct {
|
||||
* @brief VIMS base address
|
||||
*/
|
||||
#define VIMS_BASE (PERIPH_BASE + 0x34000)
|
||||
/*@}*/
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @brief VIMS register bank
|
||||
@ -259,5 +259,4 @@ typedef struct {
|
||||
#endif
|
||||
|
||||
#endif /* CC26XX_CC13XX_VIMS_H */
|
||||
|
||||
/*@}*/
|
||||
/** @} */
|
||||
|
||||
@ -40,11 +40,12 @@ typedef struct {
|
||||
reg32_t LOCK; /**< lock */
|
||||
} wdt_regs_t;
|
||||
|
||||
/** @ingroup cpu_specific_peripheral_memory_map
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @ingroup cpu_specific_peripheral_memory_map
|
||||
* @{
|
||||
*/
|
||||
#define WDT_BASE 0x40080000 /**< WDT base address */
|
||||
/*@}*/
|
||||
/** @} */
|
||||
|
||||
#define WDT ((wdt_regs_t *) (WDT_BASE)) /**< WDT register bank */
|
||||
|
||||
@ -53,5 +54,4 @@ typedef struct {
|
||||
#endif
|
||||
|
||||
#endif /* CC26XX_CC13XX_WDT_H */
|
||||
|
||||
/*@}*/
|
||||
/** @} */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user