From 0d9f6ca3f4a6cbb0f4b9b9ffcba73906de039c7e Mon Sep 17 00:00:00 2001 From: Jean-Pierre De Jesus DIAZ Date: Sun, 5 Sep 2021 20:41:13 +0200 Subject: [PATCH] cpu/cc26xx_cc13xx: fix doxygen grouping warnings Signed-off-by: Jean-Pierre De Jesus DIAZ --- cpu/cc26x0_cc13x0/include/cc26x0_cc13x0_aux.h | 69 ++++++++------ .../include/cc26x0_cc13x0_fcfg.h | 48 ++++++---- .../include/cc26x0_cc13x0_prcm.h | 92 ++++++++++--------- .../include/cc26x2_cc13x2_prcm.h | 40 ++++---- cpu/cc26xx_cc13xx/include/cc26xx_cc13xx.h | 40 +++++--- cpu/cc26xx_cc13xx/include/cc26xx_cc13xx_i2c.h | 10 +- cpu/cc26xx_cc13xx/include/cc26xx_cc13xx_ioc.h | 7 +- .../include/cc26xx_cc13xx_power.h | 3 +- cpu/cc26xx_cc13xx/include/cc26xx_cc13xx_rfc.h | 3 +- .../include/cc26xx_cc13xx_vims.h | 7 +- cpu/cc26xx_cc13xx/include/cc26xx_cc13xx_wdt.h | 12 +-- 11 files changed, 182 insertions(+), 149 deletions(-) diff --git a/cpu/cc26x0_cc13x0/include/cc26x0_cc13x0_aux.h b/cpu/cc26x0_cc13x0/include/cc26x0_cc13x0_aux.h index ee58094562..bee273b3c0 100644 --- a/cpu/cc26x0_cc13x0/include/cc26x0_cc13x0_aux.h +++ b/cpu/cc26x0_cc13x0/include/cc26x0_cc13x0_aux.h @@ -5,6 +5,7 @@ * Public License v2.1. See the file LICENSE in the top level directory for more * details. */ + /** * @ingroup cpu_cc26x0_cc13x0_definitions * @{ @@ -25,7 +26,7 @@ extern "C" { #endif /** - * AUX_AIODIO registers + * @brief AUX_AIODIO registers */ typedef struct { reg32_t GPIODOUT; /**< gpio data out */ @@ -37,9 +38,10 @@ typedef struct { reg32_t GPIODIE; /**< gpio data input enable */ } aux_aiodio_regs_t; -/** @ingroup cpu_specific_peripheral_memory_map - * @{ - */ +/** + * @ingroup cpu_specific_peripheral_memory_map + * @{ + */ #define AUX_AIODIO0_BASE 0x400C1000 /**< AUX_AIODIO0 base address */ #define AUX_AIODIO1_BASE 0x400C2000 /**< AUX_AIODIO1 base address */ /** @} */ @@ -48,7 +50,7 @@ typedef struct { #define AUX_AIODIO1 ((aux_aiodio_regs_t *) (AUX_AIODIO1_BASE)) /**< AUX_AIODIO1 register bank */ /** - * AUX_TDC registers + * @brief AUX_TDC registers */ typedef struct { reg32_t CTL; /**< control */ @@ -63,16 +65,17 @@ typedef struct { reg32_t PRECNT; /**< prescaler counter */ } aux_tdc_regs_t; -/** @ingroup cpu_specific_peripheral_memory_map - * @{ - */ +/** + * @ingroup cpu_specific_peripheral_memory_map + * @{ + */ #define AUX_TDC_BASE 0x400C4000 /**< AUX_TDC base address */ /** @} */ #define AUX_TDC ((aux_tdc_regs_t *) (AUX_TDC_BASE)) /**< AUX_TDC register bank */ /** - * AUX_EVCTL registers + * @brief AUX_EVCTL registers */ typedef struct { reg32_t VECCFG0; /**< vector config 0 */ @@ -94,9 +97,10 @@ typedef struct { reg32_t VECFLAGSCLR; /**< vector flags clear */ } aux_evtcl_regs_t; -/** @ingroup cpu_specific_peripheral_memory_map - * @{ - */ +/** + * @ingroup cpu_specific_peripheral_memory_map + * @{ + */ #define AUX_EVCTL_BASE 0x400C5000 /**< AUX_EVCTL base address */ /** @} */ @@ -142,16 +146,17 @@ typedef struct { #define MODCLKEN0_AUX_ADI4_EN 0x00000080 /* enable clock for AUX_ADI4 */ /** @} */ -/** @ingroup cpu_specific_peripheral_memory_map - * @{ - */ +/** + * @ingroup cpu_specific_peripheral_memory_map + * @{ + */ #define AUX_WUC_BASE 0x400C6000 /**< AUX_WUC base address */ /** @} */ #define AUX_WUC ((aux_wuc_regs_t *) (AUX_WUC_BASE)) /**< AUX_WUC register bank */ /** - * AUX_TIMER registers + * @brief AUX_TIMER registers */ typedef struct { reg32_t T0CFG; /**< timer 0 config */ @@ -162,9 +167,10 @@ typedef struct { reg32_t T1CTL; /**< timer 1 control */ } aux_timer_regs_t; -/** @ingroup cpu_specific_peripheral_memory_map - * @{ - */ +/** + * @ingroup cpu_specific_peripheral_memory_map + * @{ + */ #define AUX_TIMER_BASE 0x400C7000 /**< AUX_WUC base address */ /** @} */ @@ -185,11 +191,12 @@ typedef struct { reg32_t AUTOTAKE; /**< sticky request for single semaphore */ } aux_smph_regs_t; -/** @ingroup cpu_specific_peripheral_memory_map - * @{ - */ +/** + * @ingroup cpu_specific_peripheral_memory_map + * @{ + */ #define AUX_SMPH_BASE 0x400C8000 /**< AUX_WUC base address */ -/* @} */ +/** @} */ #define AUX_SMPH ((aux_smph_regs_t *) (AUX_SMPH_BASE)) /**< AUX_SMPH register bank */ @@ -205,9 +212,10 @@ typedef struct { reg32_t ISRCCTL; /**< current source control */ } aux_anaif_regs_t; -/** @ingroup cpu_specific_peripheral_memory_map - * @{ - */ +/** + * @ingroup cpu_specific_peripheral_memory_map + * @{ + */ #define AUX_ANAIF_BASE 0x400C9000 /**< AUX_WUC base address */ /** @} */ @@ -230,9 +238,10 @@ typedef struct { reg8_t ADCREF1; /**< ADC reference 1 */ } adi_4_aux_regs_t; -/** @ingroup cpu_specific_peripheral_memory_map - * @{ - */ +/** + * @ingroup cpu_specific_peripheral_memory_map + * @{ + */ #define ADI_4_AUX_BASE 0x400CB000 /**< AUX_WUC base address */ /** @} */ @@ -245,4 +254,4 @@ typedef struct { #endif #endif /* CC26X0_CC13X0_AUX_H */ -/** @}*/ +/** @} */ diff --git a/cpu/cc26x0_cc13x0/include/cc26x0_cc13x0_fcfg.h b/cpu/cc26x0_cc13x0/include/cc26x0_cc13x0_fcfg.h index 41d7fa0f80..f5017b1011 100644 --- a/cpu/cc26x0_cc13x0/include/cc26x0_cc13x0_fcfg.h +++ b/cpu/cc26x0_cc13x0/include/cc26x0_cc13x0_fcfg.h @@ -5,6 +5,7 @@ * Public License v2.1. See the file LICENSE in the top level directory for more * details. */ + /** * @ingroup cpu_cc26x0_cc13x0_definitions * @{ @@ -22,20 +23,24 @@ extern "C" { #endif -/** @ingroup cpu_specific_peripheral_memory_map +/** + * @ingroup cpu_specific_peripheral_memory_map * @{ */ -#define FCFG_BASE 0x50001000 /**< base address of FCFG memory */ -/*@}*/ +/** + * @brief Base address of FCFG memory + */ +#define FCFG_BASE (0x50001000) +/** @} */ /** - * FCFG registers + * @brief FCFG registers */ typedef struct { - uint8_t __reserved1[0xA0]; /**< meh */ + uint8_t __reserved1[0xA0]; /**< Reserved */ /* TODO does it pad here? */ reg32_t MISC_CONF_1; /**< misc config */ - reg32_t __reserved2[8]; /**< meh */ + reg32_t __reserved2[8]; /**< Reserved */ reg32_t CONFIG_RF_FRONTEND_DIV5; /**< config of RF frontend in divide-by-5 mode */ reg32_t CONFIG_RF_FRONTEND_DIV6; /**< config of RF frontend in divide-by-6 mode */ reg32_t CONFIG_RF_FRONTEND_DIV10; /**< config of RF frontend in divide-by-10 mode */ @@ -54,15 +59,15 @@ typedef struct { reg32_t CONFIG_MISC_ADC_DIV12; /**< config of IFADC in divide-by-12-mode */ reg32_t CONFIG_MISC_ADC_DIV15; /**< config of IFADC in divide-by-15-mode */ reg32_t CONFIG_MISC_ADC_DIV30; /**< config of IFADC in divide-by-30-mode */ - reg32_t __reserved3[3]; /**< meh */ + reg32_t __reserved3[3]; /**< Reserved */ reg32_t SHDW_DIE_ID_0; /**< shadow of JTAG_TAP::EFUSE::DIE_ID_0.* */ reg32_t SHDW_DIE_ID_1; /**< shadow of JTAG_TAP::EFUSE::DIE_ID_1.* */ reg32_t SHDW_DIE_ID_2; /**< shadow of JTAG_TAP::EFUSE::DIE_ID_2.* */ reg32_t SHDW_DIE_ID_3; /**< shadow of JTAG_TAP::EFUSE::DIE_ID_3.* */ - reg32_t __reserved4[4]; /**< meh */ + reg32_t __reserved4[4]; /**< Reserved */ reg32_t SHDW_OSC_BIAS_LDO_TRIM; /**< shadow of JTAG_TAP::EFUSE::BIAS_LDO_TIM.* */ reg32_t SHDW_ANA_TRIM; /**< shadow of JTAG_TAP::EFUSE::ANA_TIM.* */ - reg32_t __reserved5[9]; /**< meh */ + reg32_t __reserved5[9]; /**< Reserved */ reg32_t FLASH_NUMBER; /**< number of manufactoring lot that produced this unit */ reg32_t FLASH_COORDINATE; /**< X and Y coordinates of this unit on the wafer */ reg32_t FLASH_E_P; /**< flash erase and program setup time */ @@ -76,35 +81,35 @@ typedef struct { reg32_t FLASH_VHV; /**< flash VHV */ reg32_t FLASH_VHV_PV; /**< flash VHV program verify */ reg32_t FLASH_V; /**< flash voltages */ - reg32_t __reserved6[0x3E]; /**< meh */ + reg32_t __reserved6[0x3E]; /**< Reserved */ reg32_t USER_ID; /**< user identification */ - reg32_t __reserved7[6]; /**< meh */ + reg32_t __reserved7[6]; /**< Reserved */ reg32_t FLASH_OTP_DATA3; /**< flash OTP data 3 */ reg32_t ANA2_TRIM; /**< misc analog trim */ reg32_t LDO_TRIM; /**< LDO trim */ - reg32_t __reserved8[0xB]; /**< meh */ + reg32_t __reserved8[0xB]; /**< Reserved */ reg32_t MAC_BLE_0; /**< MAC BLE address 0 */ reg32_t MAC_BLE_1; /**< MAC BLE address 1 */ reg32_t MAC_15_4_0; /**< MAC IEEE 820.15.4 address 0 */ reg32_t MAC_15_4_1; /**< MAC IEEE 820.15.4 address 1 */ - reg32_t __reserved9[4]; /**< meh */ + reg32_t __reserved9[4]; /**< Reserved */ reg32_t FLASH_OTP_DATA4; /**< flash OTP data 4 */ reg32_t MISC_TRIM; /**< misc trim parameters */ reg32_t RCOSC_HF_TEMPCOMP; /**< RFOSC HF temperature compensation */ - reg32_t __reserved10; /**< meh */ + reg32_t __reserved10; /**< Reserved */ reg32_t ICEPICK_DEVICE_ID; /**< IcePick device identification */ reg32_t FCFG1_REVISION; /**< FCFG1 revision */ reg32_t MISC_OTP_DATA; /**< misc OTP data */ - reg32_t __reserved11[8]; /**< meh */ + reg32_t __reserved11[8]; /**< Reserved */ reg32_t IOCONF; /**< IO config */ - reg32_t __reserved12; /**< meh */ + reg32_t __reserved12; /**< Reserved */ reg32_t CONFIG_IF_ADC; /**< config of IF_ADC */ reg32_t CONFIG_OSC_TOP; /**< config of OSC */ reg32_t CONFIG_RF_FRONTEND; /**< config of RF frontend in dividy-by-2-mode */ reg32_t CONFIG_SYNTH; /**< config of synthesizer in dividy-by-2-mode */ reg32_t SOC_ADC_ABS_GAIN; /**< AUX_ADC gain in absolute reference mode */ reg32_t SOC_ADC_REL_GAIN; /**< AUX_ADC gain in relative reference mode */ - reg32_t __reserved13; /**< meh */ + reg32_t __reserved13; /**< Reserved */ reg32_t SOC_ADC_OFFSET_INT; /**< AUX_ADC temperature offsets in absolute reference mode */ reg32_t SOC_ADC_REF_TRIM_AND_OFFSET_EXT; /**< AUX_ADC reference trim and offset of external reference mode */ reg32_t AMPCOMP_TH1; /**< amplitude compensation threshold 1 */ @@ -112,10 +117,10 @@ typedef struct { reg32_t AMPCOMP_CTRL1; /**< amplitude compensation control */ reg32_t ANABYPASS_VALUE2; /**< analog bypass value for OSC */ reg32_t CONFIG_MISC_ADC; /**< config of IFADC in divide-by-2-mode */ - reg32_t __reserved14; /**< meh */ + reg32_t __reserved14; /**< Reserved */ reg32_t VOLT_TRIM; /**< voltage trim */ reg32_t OSC_CONF; /**< OSC configuration */ - reg32_t __reserved15; /**< meh */ + reg32_t __reserved15; /**< Reserved */ reg32_t CAP_TRIM; /**< capacitor trim (it says 'capasitor' in the manual - if you know what that is ;-) */ reg32_t MISC_OTP_DATA_1; /**< misc OSC control */ reg32_t PWD_CURR_20C; /**< power down current control 20C */ @@ -128,7 +133,10 @@ typedef struct { reg32_t PWD_CURR_125C; /**< power down current control 125C */ } fcfg_regs_t; -#define FCFG ((fcfg_regs_t *) (FCFG_BASE)) /**< FCFG register bank */ +/** + * @brief FCFG register bank + */ +#define FCFG ((fcfg_regs_t *) (FCFG_BASE) #ifdef __cplusplus } /* end extern "C" */ diff --git a/cpu/cc26x0_cc13x0/include/cc26x0_cc13x0_prcm.h b/cpu/cc26x0_cc13x0/include/cc26x0_cc13x0_prcm.h index 03187a1db0..8ded977243 100644 --- a/cpu/cc26x0_cc13x0/include/cc26x0_cc13x0_prcm.h +++ b/cpu/cc26x0_cc13x0/include/cc26x0_cc13x0_prcm.h @@ -24,7 +24,7 @@ extern "C" { #endif /** - * DDI_0_OSC registers + * @brief DDI_0_OSC registers */ typedef struct { reg32_t CTL0; /**< control 0 */ @@ -69,16 +69,20 @@ typedef struct { #define DDI_0_OSC_CTL0_XTAL_IS_24M 0x80000000 /** @} */ -/** @ingroup cpu_specific_peripheral_memory_map - * @{ - */ +/** + * @ingroup cpu_specific_peripheral_memory_map + * @{ + */ #define DDI0_OSC_BASE 0x400CA000 /**< DDI0_OSC base address */ -/*@}*/ - -#define DDI_0_OSC ((ddi0_osc_regs_t *) (DDI0_OSC_BASE)) /**< DDI_0_OSC register bank */ +/** @} */ /** - * AON_SYSCTL registers + * @brief DDI_0_OSC register bank + */ +#define DDI_0_OSC ((ddi0_osc_regs_t *) (DDI0_OSC_BASE)) + +/** + * @brief AON_SYSCTL registers */ typedef struct { reg32_t PWRCTL; /**< power management */ @@ -86,16 +90,17 @@ typedef struct { reg32_t SLEEPCTL; /**< sleep mode */ } aon_sysctl_regs_t; -/** @ingroup cpu_specific_peripheral_memory_map - * @{ - */ +/** + * @ingroup cpu_specific_peripheral_memory_map + * @{ + */ #define AON_SYSCTL_BASE 0x40090000 /**< AON_SYSCTL base address */ -/*@}*/ +/** @} */ #define AON_SYSCTL ((aon_sysctl_regs_t *) (AON_SYSCTL_BASE)) /**< AON_SYSCTL register bank */ /** - * AON_WUC registers + * @brief AON_WUC registers */ typedef struct { reg32_t MCUCLK; /**< MCU clock management */ @@ -104,14 +109,14 @@ typedef struct { reg32_t AUXCFG; /**< AUX config */ reg32_t AUXCTL; /**< AUX control */ reg32_t PWRSTAT; /**< power status */ - reg32_t __reserved1; /**< meh */ + reg32_t __reserved1; /**< Reserved */ reg32_t SHUTDOWN; /**< shutdown control */ reg32_t CTL0; /**< control 0 */ reg32_t CTL1; /**< control 1 */ - reg32_t __reserved2[2]; /**< meh */ + reg32_t __reserved2[2]; /**< Reserved */ reg32_t RECHARGECFG; /**< recharge controller config */ reg32_t RECHARGESTAT; /**< recharge controller status */ - reg32_t __reserved3; /**< meh */ + reg32_t __reserved3; /**< Reserved */ reg32_t OSCCFG; /**< oscillator config */ reg32_t JTAGCFG; /**< JTAG config */ reg32_t JTAGUSERCODE; /**< JTAG USERCODE */ @@ -181,16 +186,17 @@ typedef struct { #define JTAGCFG_JTAG_PD_FORCE_ON 0x10 /** @} */ -/** @ingroup cpu_specific_peripheral_memory_map - * @{ - */ +/** + * @ingroup cpu_specific_peripheral_memory_map + * @{ + */ #define AON_WUC_BASE 0x40091000 /**< AON_WUC base address */ -/*@}*/ +/** @} */ #define AON_WUC ((aon_wuc_regs_t *) (AON_WUC_BASE)) /**< AON_WUC register bank */ /** - * AON_RTC registers + * @brief AON_RTC registers */ typedef struct { reg32_t CTL; /**< Control */ @@ -215,27 +221,28 @@ typedef struct { */ #define AON_RTC_CTL_RTC_UPD_EN 0x00000002 -/** @ingroup cpu_specific_peripheral_memory_map - * @{ - */ +/** + * @ingroup cpu_specific_peripheral_memory_map + * @{ + */ #define AON_RTC_BASE (PERIPH_BASE + 0x92000) /**< AON_RTC base address */ /** @} */ #define AON_RTC ((aon_rtc_regs_t *) (AON_RTC_BASE)) /**< AON_RTC register bank */ /** - * PRCM registers + * @brief PRCM registers */ typedef struct { reg32_t INFRCLKDIVR; /**< infrastructure clock division factor for run mode */ reg32_t INFRCLKDIVS; /**< infrastructure clock division factor for sleep mode */ reg32_t INFRCLKDIVDS; /**< infrastructure clock division factor for deep sleep mode */ reg32_t VDCTL; /**< MCU voltage domain control */ - reg32_t __reserved1[6]; /**< meh */ + reg32_t __reserved1[6]; /**< Reserved */ reg32_t CLKLOADCTL; /**< clock load control */ reg32_t RFCCLKG; /**< RFC clock gate */ reg32_t VIMSCLKG; /**< VIMS clock gate */ - reg32_t __reserved2[2]; /**< meh */ + reg32_t __reserved2[2]; /**< Reserved */ reg32_t SECDMACLKGR; /**< TRNG, CRYPTO, and UDMA clock gate for run mode */ reg32_t SECDMACLKGS; /**< TRNG, CRYPTO, and UDMA clock gate for sleep mode */ reg32_t SECDMACLKGDS; /**< TRNG, CRYPTO, and UDMA clock gate for deep sleep mode */ @@ -257,47 +264,47 @@ typedef struct { reg32_t I2SCLKGR; /**< I2S clock gate for run mode */ reg32_t I2SCLKGS; /**< I2S clock gate for sleep mode */ reg32_t I2SCLKGDS; /**< I2S clock gate for deep sleep mode */ - reg32_t __reserved3[10]; /**< meh */ + reg32_t __reserved3[10]; /**< Reserved */ reg32_t CPUCLKDIV; /**< CPU clock division factor */ - reg32_t __reserved4[3]; /**< meh */ + reg32_t __reserved4[3]; /**< Reserved */ reg32_t I2SBCLKSEL; /**< I2S clock select */ reg32_t GPTCLKDIV; /**< GPT scalar */ reg32_t I2SCLKCTL; /**< I2S clock control */ reg32_t I2SMCLKDIV; /**< MCLK division ratio */ reg32_t I2SBCLKDIV; /**< BCLK division ratio */ reg32_t I2SWCLKDIV; /**< WCLK division ratio */ - reg32_t __reserved5[11]; /**< meh */ + reg32_t __reserved5[11]; /**< Reserved */ reg32_t SWRESET; /**< SW initiated resets */ reg32_t WARMRESET; /**< WARM reset control and status */ - reg32_t __reserved6[6]; /**< meh */ + reg32_t __reserved6[6]; /**< Reserved */ reg32_t PDCTL0; /**< power domain control */ reg32_t PDCTL0RFC; /**< RFC power domain control */ reg32_t PDCTL0SERIAL; /**< SERIAL power domain control */ reg32_t PDCTL0PERIPH; /**< PERIPH power domain control */ - reg32_t __reserved7; /**< meh */ + reg32_t __reserved7; /**< Reserved */ reg32_t PDSTAT0; /**< power domain status */ reg32_t PDSTAT0RFC; /**< RFC power domain status */ reg32_t PDSTAT0SERIAL; /**< SERIAL power domain status */ reg32_t PDSTAT0PERIPH; /**< PERIPH power domain status */ - reg32_t __reserved8[11]; /**< meh */ + reg32_t __reserved8[11]; /**< Reserved */ reg32_t PDCTL1; /**< power domain control */ reg32_t __reserved9; /**< power domain control */ reg32_t PDCTL1CPU; /**< CPU power domain control */ reg32_t PDCTL1RFC; /**< RFC power domain control */ reg32_t PDCTL1VIMS; /**< VIMS power domain control */ - reg32_t __reserved10; /**< meh */ + reg32_t __reserved10; /**< Reserved */ reg32_t PDSTAT1; /**< power domain status */ reg32_t PDSTAT1BUS; /**< BUS power domain status */ reg32_t PDSTAT1RFC; /**< RFC power domain status */ reg32_t PDSTAT1CPU; /**< CPU power domain status */ reg32_t PDSTAT1VIMS; /**< VIMS power domain status */ - reg32_t __reserved11[10]; /**< meh */ + reg32_t __reserved11[10]; /**< Reserved */ reg32_t RFCMODESEL; /**< selected RFC mode */ - reg32_t __reserved12[20]; /**< meh */ + reg32_t __reserved12[20]; /**< Reserved */ reg32_t RAMRETEN; /**< memory retention control */ - reg32_t __reserved13; /**< meh */ + reg32_t __reserved13; /**< Reserved */ reg32_t PDRETEN; /**< power domain retention (undocumented) */ - reg32_t __reserved14[8]; /**< meh */ + reg32_t __reserved14[8]; /**< Reserved */ reg32_t RAMHWOPT; /**< undocumented */ } prcm_regs_t; @@ -337,12 +344,13 @@ typedef struct { #define UARTCLKGDS_CLK_EN_UART0 0x1 /** @} */ -/** @ingroup cpu_specific_peripheral_memory_map - * @{ - */ +/** + * @ingroup cpu_specific_peripheral_memory_map + * @{ + */ #define PRCM_BASE (PERIPH_BASE + 0x82000) /**< PRCM base address */ #define PRCM_BASE_NONBUF (PERIPH_BASE_NONBUF + 0x82000) /**< PRCM base address (nonbuf) */ -/*@}*/ +/** @} */ #define PRCM ((prcm_regs_t *) (PRCM_BASE)) /**< PRCM register bank */ #define PRCM_NONBUF ((prcm_regs_t *) (PRCM_BASE_NONBUF)) /**< PRCM register bank (nonbuf) */ diff --git a/cpu/cc26x2_cc13x2/include/cc26x2_cc13x2_prcm.h b/cpu/cc26x2_cc13x2/include/cc26x2_cc13x2_prcm.h index 571bcdbeee..77f0c5036c 100644 --- a/cpu/cc26x2_cc13x2/include/cc26x2_cc13x2_prcm.h +++ b/cpu/cc26x2_cc13x2/include/cc26x2_cc13x2_prcm.h @@ -247,11 +247,11 @@ typedef struct { reg32_t INFRCLKDIVS; /**< infrastructure clock division factor for sleep mode */ reg32_t INFRCLKDIVDS; /**< infrastructure clock division factor for deep sleep mode */ reg32_t VDCTL; /**< MCU voltage domain control */ - reg32_t __reserved1[6]; /**< meh */ + reg32_t __reserved1[6]; /**< Reserved */ reg32_t CLKLOADCTL; /**< clock load control */ reg32_t RFCCLKG; /**< RFC clock gate */ reg32_t VIMSCLKG; /**< VIMS clock gate */ - reg32_t __reserved2[2]; /**< meh */ + reg32_t __reserved2[2]; /**< Reserved */ reg32_t SECDMACLKGR; /**< TRNG, CRYPTO, and UDMA clock gate for run mode */ reg32_t SECDMACLKGS; /**< TRNG, CRYPTO, and UDMA clock gate for sleep mode */ reg32_t SECDMACLKGDS; /**< TRNG, CRYPTO, and UDMA clock gate for deep sleep mode */ @@ -273,11 +273,11 @@ typedef struct { reg32_t I2SCLKGR; /**< I2S clock gate for run mode */ reg32_t I2SCLKGS; /**< I2S clock gate for sleep mode */ reg32_t I2SCLKGDS; /**< I2S clock gate for deep sleep mode */ - reg32_t __reserved3[9]; /**< meh */ + reg32_t __reserved3[9]; /**< Reserved */ reg32_t SYSBUSCLKDIV; /**< System bus clock division factor */ reg32_t CPUCLKDIV; /**< CPU clock division factor */ reg32_t PERBUSCPUCLKDIV; /**< Peripheral bus division factor */ - reg32_t __reserved4; /**< meh */ + reg32_t __reserved4; /**< Reserved */ reg32_t PERDMACLKDIV; /**< DMA clock division factor */ reg32_t I2SBCLKSEL; /**< I2S clock select */ reg32_t GPTCLKDIV; /**< GPT scalar */ @@ -285,7 +285,7 @@ typedef struct { reg32_t I2SMCLKDIV; /**< MCLK division ratio */ reg32_t I2SBCLKDIV; /**< BCLK division ratio */ reg32_t I2SWCLKDIV; /**< WCLK division ratio */ - reg32_t __reserved5[4]; /**< meh */ + reg32_t __reserved5[4]; /**< Reserved */ reg32_t RESETSECDMA; /**< Reset SEC and UDMA */ reg32_t RESETGPIO; /**< Reset GPIO */ reg32_t RESETGPT; /**< Reset GPTs */ @@ -293,39 +293,39 @@ typedef struct { reg32_t RESETUART; /**< Reset UART */ reg32_t RESETSSI; /**< Reset SSI */ reg32_t RESETI2S; /**< Reset I2S */ - reg32_t __reserved6[8]; /**< meh */ + reg32_t __reserved6[8]; /**< Reserved */ reg32_t PDCTL0; /**< power domain control */ reg32_t PDCTL0RFC; /**< RFC power domain control */ reg32_t PDCTL0SERIAL; /**< SERIAL power domain control */ reg32_t PDCTL0PERIPH; /**< PERIPH power domain control */ - reg32_t __reserved7; /**< meh */ + reg32_t __reserved7; /**< Reserved */ reg32_t PDSTAT0; /**< power domain status */ reg32_t PDSTAT0RFC; /**< RFC power domain status */ reg32_t PDSTAT0SERIAL; /**< SERIAL power domain status */ reg32_t PDSTAT0PERIPH; /**< PERIPH power domain status */ - reg32_t __reserved8[11]; /**< meh */ + reg32_t __reserved8[11]; /**< Reserved */ reg32_t PDCTL1; /**< power domain control */ reg32_t __reserved9; /**< power domain control */ reg32_t PDCTL1CPU; /**< CPU power domain control */ reg32_t PDCTL1RFC; /**< RFC power domain control */ reg32_t PDCTL1VIMS; /**< VIMS power domain control */ - reg32_t __reserved10; /**< meh */ + reg32_t __reserved10; /**< Reserved */ reg32_t PDSTAT1; /**< power domain status */ reg32_t PDSTAT1BUS; /**< BUS power domain status */ reg32_t PDSTAT1RFC; /**< RFC power domain status */ reg32_t PDSTAT1CPU; /**< CPU power domain status */ reg32_t PDSTAT1VIMS; /**< VIMS power domain status */ - reg32_t __reserved11[9]; /**< meh */ + reg32_t __reserved11[9]; /**< Reserved */ reg32_t RFCBITS; /**< Control to RFC */ reg32_t RFCMODESEL; /**< selected RFC mode */ reg32_t RFCMODEHWOPT; /**< allowed RFC modes */ - reg32_t __reserved12[2]; /**< meh */ + reg32_t __reserved12[2]; /**< Reserved */ reg32_t PWRPROFSTAT; /**< power profiler register */ - reg32_t __reserved13[14]; /**< meh */ + reg32_t __reserved13[14]; /**< Reserved */ reg32_t MCUSRAMCFG; /**< MCU SRAM configuration */ - reg32_t __reserved14; /**< meh */ + reg32_t __reserved14; /**< Reserved */ reg32_t RAMRETEN; /**< memory retention control */ - reg32_t __reserved15[27]; /**< meh */ + reg32_t __reserved15[27]; /**< Reserved */ reg32_t OSCIMSC; /**< oscillator interrupt mask */ reg32_t OSCRIS; /**< oscillator raw interrupt status */ reg32_t OSCICR; /**< oscillator raw interrupt clear */ @@ -370,12 +370,13 @@ typedef struct { #define UARTCLKGDS_CLK_EN_UART1 0x2 /** @} */ -/** @ingroup cpu_specific_peripheral_memory_map - * @{ - */ +/** + * @ingroup cpu_specific_peripheral_memory_map + * @{ + */ #define PRCM_BASE (PERIPH_BASE + 0x82000) /**< PRCM base address */ #define PRCM_BASE_NONBUF (PERIPH_BASE_NONBUF + 0x82000) /**< PRCM base address (nonbuf) */ -/*@}*/ +/** @} */ #define PRCM ((prcm_regs_t *) (PRCM_BASE)) /**< PRCM register bank */ #define PRCM_NONBUF ((prcm_regs_t *) (PRCM_BASE_NONBUF)) /**< PRCM register bank (nonbuf) */ @@ -385,5 +386,4 @@ typedef struct { #endif #endif /* CC26X2_CC13X2_PRCM_H */ - -/*@}*/ +/** @} */ diff --git a/cpu/cc26xx_cc13xx/include/cc26xx_cc13xx.h b/cpu/cc26xx_cc13xx/include/cc26xx_cc13xx.h index f58b1d35ed..7f3d1befa2 100644 --- a/cpu/cc26xx_cc13xx/include/cc26xx_cc13xx.h +++ b/cpu/cc26xx_cc13xx/include/cc26xx_cc13xx.h @@ -26,8 +26,17 @@ extern "C" { #endif +/** + * @brief Unsigned 8-bit register type. + */ typedef volatile uint8_t reg8_t; +/** + * @brief Unsigned 16-bit register type. + */ typedef volatile uint16_t reg16_t; +/** + * @brief Unsigned 32-bit register type. + */ typedef volatile uint32_t reg32_t; /** @@ -51,12 +60,14 @@ typedef struct { reg32_t HIGH; /**< High 16-bit half */ } reg32_m16_t; -/** @addtogroup CC13x2_cmsis CMSIS Definitions */ -/*@{*/ - -/** interrupt number definition */ -typedef enum IRQn -{ +/** + * @addtogroup CC13x2_cmsis CMSIS Definitions + * @{ + */ +/** + * @brief Interrupt number definition + */ +typedef enum IRQn { /****** Cortex-M4 Processor Exceptions Numbers ****************************/ ResetHandler_IRQn = -15, /**< 1 Reset Handler */ NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ @@ -119,11 +130,12 @@ typedef enum IRQn /** * @brief Configuration of the Cortex-M4 processor and core peripherals + * @{ */ - #define __MPU_PRESENT 1 /**< CC13x2 does provide a MPU */ #define __NVIC_PRIO_BITS 3 /**< CC13x2 offers priority levels from 0..7 */ #define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick config is used */ +/** @} */ #define RCOSC48M_FREQ 48000000 /**< 48 MHz */ #define RCOSC24M_FREQ 24000000 /**< 24 MHz */ @@ -136,17 +148,18 @@ typedef enum IRQn #else #include #endif -/*@}*/ +/** @} */ -/** @ingroup cpu_specific_peripheral_memory_map - * @{ - */ +/** + * @ingroup cpu_specific_peripheral_memory_map + * @{ + */ #define FLASH_BASE 0x00000000 /**< FLASH base address */ #define PERIPH_BASE 0x40000000 /**< Peripheral base address */ #define PERIPH_BASE_NONBUF 0x60000000 /**< Peripheral base address (nonbuf) */ #define ROM_HARD_API_BASE 0x10000048 /**< ROM Hard-API base address */ #define ROM_API_TABLE ((uint32_t *) 0x10000180) /**< ROM API table */ -/*@}*/ +/** @} */ /** * @brief ADI master instruction offsets @@ -165,5 +178,4 @@ typedef enum IRQn #endif #endif /* CC26XX_CC13XX_H */ - -/*@}*/ +/** @} */ diff --git a/cpu/cc26xx_cc13xx/include/cc26xx_cc13xx_i2c.h b/cpu/cc26xx_cc13xx/include/cc26xx_cc13xx_i2c.h index 8c036114fa..07f40c1197 100644 --- a/cpu/cc26xx_cc13xx/include/cc26xx_cc13xx_i2c.h +++ b/cpu/cc26xx_cc13xx/include/cc26xx_cc13xx_i2c.h @@ -185,9 +185,10 @@ cycle or continues on to a repeated START condition */ #define MCTRL_RUN 0x00000001 -/** @ingroup cpu_specific_peripheral_memory_map - * @{ - */ +/** + * @ingroup cpu_specific_peripheral_memory_map + * @{ + */ #define I2C_BASE (PERIPH_BASE + 0x2000) /**< I2C base address */ /** @} */ @@ -198,5 +199,4 @@ cycle or continues on to a repeated START condition #endif #endif /* CC26XX_CC13XX_I2C_H */ - -/*@}*/ +/** @} */ diff --git a/cpu/cc26xx_cc13xx/include/cc26xx_cc13xx_ioc.h b/cpu/cc26xx_cc13xx/include/cc26xx_cc13xx_ioc.h index 90a37042d7..6f121cc4c8 100644 --- a/cpu/cc26xx_cc13xx/include/cc26xx_cc13xx_ioc.h +++ b/cpu/cc26xx_cc13xx/include/cc26xx_cc13xx_ioc.h @@ -37,7 +37,7 @@ extern "C" { * @param[in] dio_num DIO number (0-31) */ typedef struct { - reg32_t CFG[32]; /**< config */ + reg32_t CFG[32]; /**< Config */ } cc26x0_ioc_regs_t; #define IOC ((cc26x0_ioc_regs_t *)(MCU_IOC_BASE)) /**< IOC register banks */ @@ -53,7 +53,7 @@ typedef struct { #define IOCFG_PORTID_AON_SCK 0x00000002 /**< AON SPI-S SCK */ #define IOCFG_PORTID_AON_SDI 0x00000003 /**< AON SPI-S SDI */ #define IOCFG_PORTID_AON_SDO 0x00000004 /**< AON SPI-S SDO */ -#endif //CPU_VARIANT_X0 +#endif /* CPU_VARIANT_X0 */ #define IOCFG_PORTID_AON_CLK32K 0x00000007 /**< AON external 32kHz clock */ #define IOCFG_PORTID_AUX_IO 0x00000008 /**< AUX IO */ @@ -183,5 +183,4 @@ typedef struct { #endif #endif /* CC26XX_CC13XX_IOC_H */ - -/*@}*/ +/** @} */ diff --git a/cpu/cc26xx_cc13xx/include/cc26xx_cc13xx_power.h b/cpu/cc26xx_cc13xx/include/cc26xx_cc13xx_power.h index d14723df17..05c7ffe8bb 100644 --- a/cpu/cc26xx_cc13xx/include/cc26xx_cc13xx_power.h +++ b/cpu/cc26xx_cc13xx/include/cc26xx_cc13xx_power.h @@ -92,5 +92,4 @@ void power_clock_disable_uart(uart_t uart); #endif #endif /* CC26XX_CC13XX_POWER_H */ - -/*@}*/ +/** @} */ diff --git a/cpu/cc26xx_cc13xx/include/cc26xx_cc13xx_rfc.h b/cpu/cc26xx_cc13xx/include/cc26xx_cc13xx_rfc.h index 673d6f9de2..916a10dac1 100644 --- a/cpu/cc26xx_cc13xx/include/cc26xx_cc13xx_rfc.h +++ b/cpu/cc26xx_cc13xx/include/cc26xx_cc13xx_rfc.h @@ -168,5 +168,4 @@ typedef struct { #endif #endif /* CC26XX_CC13XX_RFC_H */ - -/*@}*/ +/** @} */ diff --git a/cpu/cc26xx_cc13xx/include/cc26xx_cc13xx_vims.h b/cpu/cc26xx_cc13xx/include/cc26xx_cc13xx_vims.h index 38d53317bc..4c432d748c 100644 --- a/cpu/cc26xx_cc13xx/include/cc26xx_cc13xx_vims.h +++ b/cpu/cc26xx_cc13xx/include/cc26xx_cc13xx_vims.h @@ -190,7 +190,7 @@ typedef struct { * @brief FLASH base address */ #define FLASH_BASEADDR (PERIPH_BASE + 0x30000) -/*@}*/ +/** @} */ /** * @brief FLASH register bank @@ -213,7 +213,7 @@ typedef struct { * @brief VIMS base address */ #define VIMS_BASE (PERIPH_BASE + 0x34000) -/*@}*/ +/** @} */ /** * @brief VIMS register bank @@ -259,5 +259,4 @@ typedef struct { #endif #endif /* CC26XX_CC13XX_VIMS_H */ - -/*@}*/ +/** @} */ diff --git a/cpu/cc26xx_cc13xx/include/cc26xx_cc13xx_wdt.h b/cpu/cc26xx_cc13xx/include/cc26xx_cc13xx_wdt.h index 2d9459e353..83f4d98c6e 100644 --- a/cpu/cc26xx_cc13xx/include/cc26xx_cc13xx_wdt.h +++ b/cpu/cc26xx_cc13xx/include/cc26xx_cc13xx_wdt.h @@ -40,11 +40,12 @@ typedef struct { reg32_t LOCK; /**< lock */ } wdt_regs_t; -/** @ingroup cpu_specific_peripheral_memory_map - * @{ - */ +/** + * @ingroup cpu_specific_peripheral_memory_map + * @{ + */ #define WDT_BASE 0x40080000 /**< WDT base address */ -/*@}*/ +/** @} */ #define WDT ((wdt_regs_t *) (WDT_BASE)) /**< WDT register bank */ @@ -53,5 +54,4 @@ typedef struct { #endif #endif /* CC26XX_CC13XX_WDT_H */ - -/*@}*/ +/** @} */