Although ESP32 has four SPI controllers, only two of them can be effectively used (HSP and VSPI). The third one (FSPI) is used for external memory such as flash and PSRAM and can not be used for peripherals. FSPI is therefore removed from the API. In addition, the SPI0_DEV and SPI1_DEV configuration parameters are renamed SPI0_CTRL and SPI1_CTRL to better describe what they define and to avoid confusion with SPI_DEV (0) and SPI_DEV (1).
Although ESP32 has four SPI controllers, only two of them can be effectively used (HSP and VSPI). The third one (FSPI) is used for external memory such as flash and PSRAM and can not be used for peripherals. FSPI is therefore removed from the API. In addition, the SPI0_DEV and SPI1_DEV configuration parameters are renamed SPI0_CTRL and SPI1_CTRL to better describe what they define and to avoid confusion with SPI_DEV (0) and SPI_DEV (1).
Timer restart was moved from esp_now_scan_peers_done to esp_now_scan_peers_start to avoid that the scan for peers isn't triggered anymore if the esp_now_scan_peers_done callback isn't called because of errors.
The brr calculation on the datasheet is different than what is implmented.
This is intentional since it provides better rounding due to truncation.
There was no comment explaining that so this comment should prevent confusion.
Since it is not possible to reenter the function `esp_now_recv_cb`, and the functions netif::_ recv and esp_now_netdev::_ recv are called directly in the same thread context we can read directly from the `buf` and don't need a receive buffer anymmore.
Since it is not possible to reenter the function `esp_now_recv_cb`, and the functions netif::_ recv and esp_now_netdev::_ recv are called directly in the same thread context we only need a buffer which contains one frame and its source mac address.
Since it is not possible to reenter the function `esp_now_recv_cb`, and the functions netif::_ recv and esp_now_netdev::_ recv are called directly in the same thread context, neither a mutual exclusion has to be realized nor have the interrupts to be deactivated.
Since the esp_now_recv_cb function is not called directly as an ISR through interrupts, it is not executed in the interrupt context. _recv can therefore be called directly. The treatment of the recv_event is no longer necessary.
Although it should not be possible to reenter the function esp_now_recv_cb, this is avoided by an additional boolean variable. It can not be realized by mutex because it would reenter from same thread context. If macro NDEBUG is not defined, an assertion is used.
A second slot is defined with a calculated size, from the
remaining flash after the bootloader and the first slot.
Both slots are defined as equal size, but it can be overriden.
Avoids parsing IPv6 packets to determine destination address.
Allows using 6Lo over ESP-NOW, which is required due to the low MTU of
ESP-NOW.
Co-authored-by: Gunar Schorcht <gunar@schorcht.net>
Refactors i2c_2 to match the structure of i2c_1 better.
Corrects functionality issues.
Allows the common implementation of read_regs and write_regs.
Documents constraints of hardware.
Matches error messages with API.
RIOTBOOT_SLOT_LEN is calculated as an hexadecimal value and
handles ROM_LEN defined as kilobytes like '512K'
This enables support for all the cortex-m0+/3/4/7 arch,
so most boards embedding these are potentially supported.
One needs just to ensure that the CPU can be initialised
at least twice.
Co-authored-by: Gaëtan Harter <gaetan.harter@fu-berlin.de>
This new function allows to jump to another execution
environment (VTOR) located at a certain (aligned) address.
It's used to boot firmwares at another location than
`CPU_FLASH_BASE`.
The user needs to ensure that the CPU using this feature
is able to be initialised at least twice while jumping
to the RIOT `reset_handler_default` function, since it
initialises the CPU again (calls cpu_init()).
Co-authored-by: Kaspar Schleiser <kaspar@schleiser.de>
Due to the stdio getting called after periph_init the uart may send before initialized.
This adds a simple check so the uart does not get into a locked-up state.
This commit fixes configuration problems when trying to use i2c pins that need to be remapped.
All B8 and B9 pins for STM32F1 need to be remapped, so a check is done if the remappable pins are selected.
cpu/esp32/include/periph_cpu.h overrides the default definition of adc_res_t from periph/adc with a definition which contains only four resolution, two new resolutions and two resolutions defined by the default definition of adc_res_t. This gives compilation errors if an application uses other resolutions. According to the documentation, adc_sample should return -1 if the resolution is not supported. All other CPUs override adc_res_t either to add new resolutions or to mark resolutions as unsupported. But they all allow to use them at the interface. Therefore, esp32 overrides now the definition of adc_res_t with all resolutions that are defined by the default definition of adc_res_t and new platform specific resolutions. It returns -1 if a resolution is used in adc_sample that is not supported.
cpu/esp8266/include/periph_cpu.h overrides the default definition of adc_res_t from periph/adc with a definition which contains only one resolution. This gives compilation errorss if an application uses other resolutions. According to the documentation, adc_sample should return -1 if the resolution is not supported. All other CPUs override adc_res_t either to add new resolutions or to mark resolutions as unsupported. But they all allow to use them at the interface. Therefore, esp8266 uses now the default definition of adc_res_t and returns -1 if a solution is used in adc_sample that is not supported.
By not forcing a fixed oversampling rate we can achieve better baud rate
accuracy than otherwise possible.
For example, when requesting 115200 with a module clock of 4 MHz,
picking an oversampling rate of 17 (instead of hardware
default 16) yields 117647 baud instead of 125000 baud as the best
matching rate. Better matching baud rate between receiver and
transmitter results in a lower probability of transmission errors.
- correct number of timers for atmega328p from 2 to 1
- correct number of timer channels for atmega328p from 3 to 2
- adapt atmega periph timer implementation accordingly
This commit adds the ESP32 vendor libraries for WLAN to the BASELIBS variable. This avoids having to define an additional archive group in the LINKGFLAGS variable which contains these vendor libraries and again RIOT module archive files with the symbols that are refered by these vendor libraries.
Measurements show that the time from pin edge until return from
interrupt is reduced from 22 us to 6.1 us for KW41Z running at
41.94 MHz. The measurements used a no-op GPIO callback for testing and
were measured using an external logic analyzer.
cpu.c and startup.c were redundant in most platforms, except for
atmega256rfr2. The common code is now in cpu/atmega_common/cpu.c
and cpu/atmega_common/startup.c. cpu_conf.h is also removed as
it's now in cpu/atmega_common/include thus shared by all atmega
based platforms.
Removes duplicated code for atmega platforms. They were all
basically the same, only with the exception of atmegarfr2,
for which there is an #if statement to use the code in the
same file.
Some ESP32 boards (like my SparkFun ESP32 Thing) have a main clock
crystal that runs at 26MHz, not 40MHz. RIOT appears to assume 40MHz.
The mismatch causes the UART to not sync properly, resulting in
garbage written to the terminal instead of log output.
I’ve added:
* A new board configuration constant ESP32_XTAL_FREQ that defaults
to 40, but can be overridden by a board def or at build time to
force a specific value (i.e. 26).
* Some code spliced into system_clk_init() to check this constant and
call rtc_clk_init() to set the correct frequency.
* A copy of the rtf_clk_init() function from the ESP-IDF sources.
Fixes#10272
Errors flags could not clear making the i2c unusable after error.
This fix removes the error check in start so the error flags can clear and does proper checking for status bits before _bus_check.
The problem seemed to be a pipelining problem of write and read instructions when swapping the context. An isync instruction when returning from a context switch solves the potential pipelining problem.
Reason for the problem was that tast_exit function in thread_arch.c tried to release the thread a second time although it was already released in sched_task_exit. A simple check whether the thread is already released (sched_active_thread == NULL) solved the problem.
Xtensa newlib version requires pthread_setcancelstate as symbol. Therefore, the module pthread was always used, which in turn requires the module xtimer. The xtimer module, however, uses TIMER_DEV(0). Therefore, tests/timers failed for TIMER_DEV(0).
The `periph_flash_common` feature was only defined here to trigger
inclusion of a source file with common functions.
It even only defines private symbols `_lock` and `_unlock` so no reason
to expose it to the build system.
And in practice, all stm cpus providing `periph_flashpage` or
`periph_eeprom` were required to provide `periph_flash_common` to allow
including it.
The previous implementation was only parsing in the modules were in
`FEATURES_REQUIRED` wich did not take cases of `FEATURES_OPTIONAL` into
account.
And also, in the same time, as the dependencies was declared in
`Makefile.include` it was processed before `Makefile.dep` so never handled
cases where a module could depend on `periph_flashpage` or
`periph_eeprom` feature.
It is replaced by selecting the common source file when module using it
are included.
The now useless feature `periph_flash_common` is removed from
`FEATURES_PROVIDED`.
`cpu/stm32_common/Makefile.dep` was never included by the global
`Makefile.dep`, so declaring this `USEMODULE +=` here was never shown to
the build system and never exported as `MODULE_PERIPH_I2C_X` variables.
In fact, `USEMODULE` was only used to trigger the `periph.mk`/`SUBMODULES`
mechanism to add matching source files names to `SRC` and so select
the implementation for each CPU type.
It is replaced by just explicitly selecting the right source file.
The commit
- improves the timing of the SDA and SCL signals that fixes communication problems with some slaves (#10115),
- introduces the internal function _i2c_clear which clears the bus when SDA line is locked at LOW, and
- renames internal _i2c_*_sda and _i2c_*_scl functions to function names that are more clear, e.g., _i2c_clear_sda to _i2c_sda_low.
It is the role of boards based on 'cpu/fe310' to give the configuration
for the rtc/rtt.
The fe310/periph/rtc implementation depends on having periph/rtt configured
by the board so depends on the board 'providing' the periph_rtt feature
and declaring the required macros.
It should not simply depend of the 'periph_rtt' module as this does not
enforce having a configuration for the module in the board.
In practice, when compiling, it would result in undefined 'RTT' symbols,
instead of the build system detecting it.
This allows a board configuration to select which kind of averaging
should be applied to the pin instead of always using 32 sample average.
Very high impedance sources may need to disable hardware averaging in
order to give correct values, the on-chip temperature sensor is one such
signal source.
Adapt the periph ADC implementation to use vendor defines where
ever possible. Remove duplicate or obsolete defines and adapt
board configuration as required.
Refactor cortexm_init to allow bits and pieces of
it to be called separately, while retaining the
current API, too. Needed for non-standard
Cortex-M initialisation, such as with nRF52
SoftDevice.
This Patch makes gpio_init precalculate the pin mask once,
This Patch makes gpio_init of atmega_common configure the pin as an input and configure the pullup in the case of GPIO_IN_PU.
GPIO_IN_PU and GPIO_IN need to change pullup so they need to change output (this is coverd by the not touching outputs is not guaranteed statement)
(this is a special case for atmega the pull_up is configured by writing 1 to the port_register which is also the level of the output if the pin is configured to output).
This fix makes it more compliant to comments in periph/gpio.h
- Previous cast was to a function pointer was not legal
- Using already present function pointer to store the IAP entry point to improve
readability. (Which also fixes the cast issue.)
- arm_reset was completely undocumented, even though technical details buried
deeply in the data sheet of the LPC2387 are involved in the code
- The attribute "naked" is misplaced, it should only be used when no C code
is present. However, the function consists of C code only
- The attribute "noreturn" has to be used in the declaration [1] of a function,
not in the implementation. Otherwise the caller is not informed and code using
the function will not be optimized.
[1]: https://gcc.gnu.org/onlinedocs/gcc/Common-Function-Attributes.html
Allow defining a specific rom length to use for linking the firmware,
_fw_rom_length, instead of the default configuration to use the whole rom from
_rom_offset to the end.
* Add cortexm_common/Makefile.include FW_ROM_SIZE configuration
* Add an assertion that _fw_rom_length still respects _rom_length
Define _rom_offset with a conditional evaluated at execution time to allow
setting it in compilation rules and generate in the same make instance different
elf files with different configurations.
Rework SPI periph driver to use proper RIOT GPIO API functions.
Also cleanup header files by using vendor defines and remove
obsolete code. Further, adapt board config accordingly.
The SPI bus frequency/clock is calculated relative to the MCUs
core clock. Currently all boards use the default 32MHz, hence
prescaler settings for SPI are all the same. This PR moves the
default config for 32MHz to the CPU and allows to be overriden
by board config if needed.
Remove unused or obsolete defines in headers, due to usage of
vendor headers. Also remove register bit definition in timer
struct because they where not used in the implementation.
This came up when compiling an application for an NRF5x-based board
with LLVM/clang. The function does not seem to be used throughout the
file so I just removed it.
Currently the cc2538 is based on from-scratch adaption which is
not feature complete and thus lacks defines etc. Introducing the
official vendor header will ease future extension and adaptions
of the CPU and its features.
- dont send stop if bus is busy and before any action is done on bus
- and bus check that looks for bus error, arbitration and nack events
- check for ACK (TXIS) before writing bytes on bus and not between each write
