mirror of
https://github.com/RIOT-OS/RIOT.git
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cpu/stm_common: Refactor and cleanup i2c_1
Refactor to use common read_regs. Add error reporting and handling for unsupported low level commands. Document hardware constraints.
This commit is contained in:
MrKevinWeiss
parent
63e71cbbde
commit
f3b2a62c67
@ -159,9 +159,9 @@ typedef uint32_t gpio_t;
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#define PERIPH_I2C_NEED_READ_REG
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/** Use write reg function from periph common */
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#define PERIPH_I2C_NEED_WRITE_REG
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#define PERIPH_I2C_NEED_READ_REGS
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#if defined(CPU_FAM_STM32F1) || defined(CPU_FAM_STM32F2) || \
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defined(CPU_FAM_STM32L1) || defined(CPU_FAM_STM32F4)
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#define PERIPH_I2C_NEED_READ_REGS
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#define PERIPH_I2C_NEED_WRITE_REGS
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#endif
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/** @} */
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@ -2,6 +2,7 @@
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* Copyright (C) 2015 Jan Pohlmann <jan-pohlmann@gmx.de>
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* 2017 we-sens.com
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* 2018 Inria
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* 2018 HAW Hamburg
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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@ -26,6 +27,7 @@
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* @author Jan Pohlmann <jan-pohlmann@gmx.de>
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* @author Aurélien Fillau <aurelien.fillau@we-sens.com>
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* @author Alexandre Abadie <alexandre.abadie@inria.fr>
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* @author Kevin Weiss <kevin.weiss@haw-hamburg.de>
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*
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* @}
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*/
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@ -46,22 +48,22 @@
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#include "debug.h"
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#define TICK_TIMEOUT (0xFFFF)
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#define MAX_BYTES_PER_FRAME (256)
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#define I2C_IRQ_PRIO (1)
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#define I2C_FLAG_READ (I2C_READ)
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#define I2C_FLAG_WRITE (0)
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#define I2C_IRQ_PRIO (1)
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#define I2C_FLAG_READ (I2C_READ << I2C_CR2_RD_WRN_Pos)
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#define I2C_FLAG_WRITE (0)
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#define CLEAR_FLAG (I2C_ICR_NACKCF | I2C_ICR_ARLOCF | I2C_ICR_BERRCF)
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#define ERROR_FLAG (I2C_ISR_NACKF | I2C_ISR_ARLO | I2C_ISR_BERR)
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#define CLEAR_FLAG (I2C_ICR_NACKCF | I2C_ICR_ARLOCF | I2C_ICR_BERRCF | I2C_ICR_ADDRCF)
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/* static function definitions */
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static inline void _i2c_init(I2C_TypeDef *i2c, uint32_t timing);
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static inline int _start(I2C_TypeDef *dev, uint16_t address, size_t length,
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uint8_t rw_flag, uint8_t flags);
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static inline int _read(I2C_TypeDef *dev, uint8_t *data, size_t length);
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static inline int _write(I2C_TypeDef *i2c, const uint8_t *data, size_t length);
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static inline int _stop(I2C_TypeDef *i2c);
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static inline int _check_bus(I2C_TypeDef *i2c);
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static int _write(I2C_TypeDef *i2c, uint16_t addr, const void *data,
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size_t length, uint8_t flags, uint32_t cr2_flags);
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static int _start(I2C_TypeDef *i2c, uint32_t cr2, uint8_t flags);
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static int _stop(I2C_TypeDef *i2c);
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static int _wait_isr_set(I2C_TypeDef *i2c, uint32_t mask, uint8_t flags);
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static inline int _wait_for_bus(I2C_TypeDef *i2c);
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/**
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* @brief Array holding one pre-initialized mutex for each I2C device
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@ -146,365 +148,248 @@ int i2c_release(i2c_t dev)
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{
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assert(dev < I2C_NUMOF);
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uint16_t tick = TICK_TIMEOUT;
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while ((i2c_config[dev].dev->ISR & I2C_ISR_BUSY) && tick--) {}
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periph_clk_dis(i2c_config[dev].bus, i2c_config[dev].rcc_mask);
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mutex_unlock(&locks[dev]);
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return 0;
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}
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int i2c_write_regs(i2c_t dev, uint16_t addr, uint16_t reg,
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const void *data, size_t len, uint8_t flags)
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{
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assert(dev < I2C_NUMOF);
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if (flags & (I2C_NOSTOP | I2C_NOSTART)) {
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return -EOPNOTSUPP;
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}
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I2C_TypeDef *i2c = i2c_config[dev].dev;
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assert(i2c != NULL);
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DEBUG("[i2c] write_regs: Starting\n");
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/* As a higher level function we know the bus should be free */
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if (i2c->ISR & I2C_ISR_BUSY) {
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return -EAGAIN;
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}
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/* First set ADDR and register with no stop */
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/* No RELOAD should be set so repeated start is valid */
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int ret = _write(i2c, addr, ®, (flags & I2C_REG16) ? 2 : 1,
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flags | I2C_NOSTOP, I2C_CR2_RELOAD);
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if (ret < 0) {
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return ret;
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}
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/* Then get the data from device */
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return _write(i2c, addr, data, len, I2C_NOSTART, 0);
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}
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int i2c_read_bytes(i2c_t dev, uint16_t address, void *data,
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size_t length, uint8_t flags)
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{
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assert(dev < I2C_NUMOF);
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assert(dev < I2C_NUMOF && length < MAX_BYTES_PER_FRAME);
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I2C_TypeDef *i2c = i2c_config[dev].dev;
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assert(i2c != NULL);
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if (flags & I2C_ADDR10) {
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/* If reload was set, cannot send a repeated start */
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if ((i2c->ISR & I2C_ISR_TCR) && !(flags & I2C_NOSTART)) {
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return -EOPNOTSUPP;
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}
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int ret = 0;
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if (!(flags & I2C_NOSTART)) {
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DEBUG("[i2c] read_bytes: send start condition\n");
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/* start reception and send slave address */
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ret = _start(i2c, address, length, I2C_FLAG_READ, flags);
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if (ret < 0) {
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_stop(i2c);
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return ret;
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}
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}
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DEBUG("[i2c] read_bytes: read the data\n");
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/* read the data bytes */
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ret = _read(i2c, data, length);
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DEBUG("[i2c] read_bytes: Starting\n");
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/* RELOAD is needed because we don't know the full frame */
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int ret = _start(i2c, (address << 1) | (length << I2C_CR2_NBYTES_Pos) |
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I2C_CR2_RELOAD | I2C_FLAG_READ, flags);
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if (ret < 0) {
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_stop(i2c);
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DEBUG("[i2c] read_bytes: error while reading\n");
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return ret;
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}
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if (!(flags & I2C_NOSTOP)) {
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DEBUG("[i2c] read_bytes: end transmission\n");
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ret = _stop(i2c);
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for (size_t i = 0; i < length; i++) {
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/* wait for transfer to finish */
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DEBUG("[i2c] read_bytes: Waiting for DR to be full\n");
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ret = _wait_isr_set(i2c, I2C_ISR_RXNE, flags);
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if (ret < 0) {
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return ret;
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}
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/* read data from data register */
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((uint8_t*)data)[i]= i2c->RXDR;
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DEBUG("[i2c] read_bytes: DR full, read 0x%02X\n", ((uint8_t*)data)[i]);
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}
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if (flags & I2C_NOSTOP) {
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/* With NOSTOP, the TCR indicates that the next command is ready */
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/* TCR is needed because RELOAD is set preventing a NACK on last byte */
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return _wait_isr_set(i2c, I2C_ISR_TCR, flags);
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}
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/* Wait until stop before other commands are sent */
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ret = _wait_isr_set(i2c, I2C_ISR_STOPF, flags);
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if (ret < 0) {
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return ret;
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}
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return ret;
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}
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int i2c_read_regs(i2c_t dev, uint16_t address, uint16_t reg, void *data,
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size_t length, uint8_t flags)
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{
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assert(dev < I2C_NUMOF);
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DEBUG("[i2c] read_regs: addr: %04X, reg: %04X\n", address, reg);
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if ((flags & I2C_REG16) || (flags & I2C_ADDR10)) {
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return -EOPNOTSUPP;
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}
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uint16_t tick = TICK_TIMEOUT;
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I2C_TypeDef *i2c = i2c_config[dev].dev;
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/* Check to see if the bus is busy */
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while ((i2c->ISR & I2C_ISR_BUSY) && tick--) {}
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if (!tick) {
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return -ETIMEDOUT;
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}
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if (!(flags & I2C_NOSTART)) {
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DEBUG("[i2c] read_regs: send start sequence\n");
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/* send start sequence and slave address */
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int ret = _start(i2c, address, 1, 0, flags);
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if (ret < 0) {
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_stop(i2c);
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return ret;
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}
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}
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tick = TICK_TIMEOUT;
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/* wait for ack */
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while (!(i2c->ISR & I2C_ISR_TXIS) && tick--) {
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if ((i2c->ISR & ERROR_FLAG) || !tick) {
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/* end transmission */
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_stop(i2c);
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return -ENXIO;
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}
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}
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DEBUG("[i2c] read_regs: Write register to read\n");
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i2c->TXDR = reg;
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/* send repeated start sequence, read registers and end transmission */
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DEBUG("[i2c] read_regs: ACK received, send repeated start sequence\n");
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return i2c_read_bytes(dev, address, data, length, 0);
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return _wait_for_bus(i2c);
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}
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/**
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* Cannot support continuous writes or frame splitting at this level. If an
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* I2C_NOSTOP has been sent it must be followed by a repeated start or stop.
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*/
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int i2c_write_bytes(i2c_t dev, uint16_t address, const void *data,
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size_t length, uint8_t flags)
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{
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assert(dev < I2C_NUMOF);
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I2C_TypeDef *i2c = i2c_config[dev].dev;
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DEBUG("[i2c] write_bytes: Starting\n");
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return _write(i2c, address, data, length, flags, 0);
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}
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if (flags & I2C_ADDR10) {
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static int _write(I2C_TypeDef *i2c, uint16_t addr, const void *data,
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size_t length, uint8_t flags, uint32_t cr2_flags)
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{
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assert(i2c != NULL && length < MAX_BYTES_PER_FRAME);
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/* If reload was NOT set, must either stop or start */
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if ((i2c->ISR & I2C_ISR_TC) && (flags & I2C_NOSTART)) {
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return -EOPNOTSUPP;
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}
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I2C_TypeDef *i2c = i2c_config[dev].dev;
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int ret = 0;
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if (!(flags & I2C_NOSTART)) {
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DEBUG("[i2c] write_bytes: start transmission\n");
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/* start transmission and send slave address */
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ret = _start(i2c, address, length, I2C_FLAG_WRITE, flags);
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if (ret < 0) {
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_stop(i2c);
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return ret;
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}
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}
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DEBUG("[i2c] write_bytes: write the data (%d bytes)\n", length);
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/* send out data bytes */
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ret = _write(i2c, data, length);
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int ret = _start(i2c, (addr << 1) | (length << I2C_CR2_NBYTES_Pos) |
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cr2_flags, flags);
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if (ret < 0) {
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_stop(i2c);
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DEBUG("[i2c] write_bytes: nothing was written\n");
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return ret;
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}
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if (!(flags & I2C_NOSTOP)) {
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DEBUG("[i2c] write_bytes: end transmission\n");
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/* end transmission */
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ret = _stop(i2c);
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for (size_t i = 0; i < length; i++) {
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DEBUG("[i2c] write_bytes: Waiting for TX reg to be free\n");
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ret = _wait_isr_set(i2c, I2C_ISR_TXIS, flags);
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if (ret < 0) {
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return ret;
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}
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DEBUG("[i2c] write_bytes: TX is free so send byte\n");
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/* write data to data register */
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i2c->TXDR = ((uint8_t*)data)[i];
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}
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return ret;
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}
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int i2c_write_regs(i2c_t dev, uint16_t address, uint16_t reg, const void *data,
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size_t length, uint8_t flags)
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{
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assert(dev < I2C_NUMOF);
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uint16_t tick = TICK_TIMEOUT;
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I2C_TypeDef *i2c = i2c_config[dev].dev;
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int ret = 0;
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if ((flags & I2C_REG16) || (flags & I2C_ADDR10)) {
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return -EOPNOTSUPP;
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}
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/* Check to see if the bus is busy */
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while ((i2c->ISR & I2C_ISR_BUSY) && tick--) {}
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if (!tick) {
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return -ETIMEDOUT;
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}
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if (!(flags & I2C_NOSTART)) {
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/* start transmission and send slave address */
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/* increase length because our data is register+data */
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ret = _start(i2c, address, length + 1, I2C_FLAG_WRITE, flags);
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if (ret < 0) {
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_stop(i2c);
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return ret;
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if (flags & I2C_NOSTOP) {
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if (cr2_flags & I2C_CR2_RELOAD) {
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DEBUG("[i2c] write_bytes: Waiting for TCR\n");
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/* With NOSTOP, the TCR indicates that the next command is ready */
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/* TCR is needed because RELOAD allows loading more bytes */
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return _wait_isr_set(i2c, I2C_ISR_TCR, flags);
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}
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else {
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DEBUG("[i2c] write_bytes: Waiting for TC\n");
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/* With NOSTOP, the TC indicates that the next command is ready */
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/* TC is needed because no reload is set for repeated start */
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return _wait_isr_set(i2c, I2C_ISR_TC, flags);
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}
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}
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/* send register number */
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DEBUG("[i2c] write_regs: ACK received, write reg into DR\n");
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i2c->TXDR = reg;
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/* write out data bytes */
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ret = _write(i2c, data, length);
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DEBUG("[i2c] write_bytes: Waiting for stop\n");
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/* Wait until stop before other commands are sent */
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ret = _wait_isr_set(i2c, I2C_ISR_STOPF, flags);
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if (ret < 0) {
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_stop(i2c);
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return ret;
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}
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if (!(flags & I2C_NOSTOP)) {
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/* end transmission */
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ret = _stop(i2c);
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if (ret < 0) {
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return ret;
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}
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}
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return ret;
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return _wait_for_bus(i2c);
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}
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static inline int _start(I2C_TypeDef *i2c, uint16_t address,
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size_t length, uint8_t rw_flag, uint8_t flags)
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{
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/* 10 bit address not supported for now */
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if (flags & I2C_ADDR10) {
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return -EOPNOTSUPP;
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}
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static int _start(I2C_TypeDef *i2c, uint32_t cr2, uint8_t flags)
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{
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assert(i2c != NULL);
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assert((i2c->ISR & I2C_ISR_BUSY) || !(flags & I2C_NOSTART));
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i2c->CR2 = 0;
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DEBUG("[i2c] start: set address mode\n");
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/* set address mode to 7-bit */
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i2c->CR2 &= ~(I2C_CR2_ADD10);
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DEBUG("[i2c] start: set slave address\n");
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/* set slave address */
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i2c->CR2 &= ~(I2C_CR2_SADD);
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i2c->CR2 |= (address << 1);
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DEBUG("[i2c] start: set transfert direction\n");
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/* set transfer direction */
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i2c->CR2 &= ~(I2C_CR2_RD_WRN);
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i2c->CR2 |= (rw_flag << I2C_CR2_RD_WRN_Pos);
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DEBUG("[i2c] start: set number of bytes\n");
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/* set number of bytes */
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i2c->CR2 &= ~(I2C_CR2_NBYTES);
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i2c->CR2 |= (length << I2C_CR2_NBYTES_Pos);
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/* configure autoend configuration */
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i2c->CR2 &= ~(I2C_CR2_AUTOEND);
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/* Clear interrupt */
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i2c->ICR |= CLEAR_FLAG;
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/* generate start condition */
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DEBUG("[i2c] start: generate start condition\n");
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i2c->CR2 |= I2C_CR2_START;
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/* Wait for the start followed by the address to be sent */
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uint16_t tick = TICK_TIMEOUT;
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while ((i2c->CR2 & I2C_CR2_START) && tick--) {}
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if (!tick) {
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return -ETIMEDOUT;
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if (flags & I2C_ADDR10) {
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return -EOPNOTSUPP;
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}
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return _check_bus(i2c);
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}
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static inline int _read(I2C_TypeDef *i2c, uint8_t *data, size_t length)
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{
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assert(i2c != NULL);
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for (size_t i = 0; i < length; i++) {
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/* wait for transfer to finish */
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DEBUG("[i2c] read: Waiting for DR to be full\n");
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if (!(flags & I2C_NOSTART)) {
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DEBUG("[i2c] start: Generate start condition\n");
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/* Generate start condition */
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cr2 |= I2C_CR2_START;
|
||||
}
|
||||
if (!(flags & I2C_NOSTOP)) {
|
||||
cr2 |= I2C_CR2_AUTOEND;
|
||||
cr2 &= ~(I2C_CR2_RELOAD);
|
||||
}
|
||||
DEBUG("[i2c] start: Setting CR2=0x%08lX\n", cr2);
|
||||
i2c->CR2 = cr2;
|
||||
if (!(flags & I2C_NOSTART)) {
|
||||
uint16_t tick = TICK_TIMEOUT;
|
||||
while (!(i2c->ISR & I2C_ISR_RXNE) && tick--) {}
|
||||
if (i2c->ISR & ERROR_FLAG || !tick) {
|
||||
return -ETIMEDOUT;
|
||||
while ((i2c->CR2 & I2C_CR2_START) && tick--) {
|
||||
if (!tick) {
|
||||
/* Try to stop for state error recovery */
|
||||
_stop(i2c);
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
}
|
||||
|
||||
DEBUG("[i2c] read: DR is now full\n");
|
||||
|
||||
/* read data from data register */
|
||||
data[i] = i2c->RXDR;
|
||||
DEBUG("[i2c] read: Read byte %i from DR\n", i);
|
||||
}
|
||||
|
||||
return _check_bus(i2c);
|
||||
}
|
||||
|
||||
static inline int _write(I2C_TypeDef *i2c, const uint8_t *data, size_t length)
|
||||
{
|
||||
assert(i2c != NULL);
|
||||
|
||||
for (size_t i = 0; i < length; i++) {
|
||||
/* wait for ack */
|
||||
DEBUG("[i2c] write: Waiting for ACK\n");
|
||||
uint16_t tick = TICK_TIMEOUT;
|
||||
while (!(i2c->ISR & I2C_ISR_TXIS) && tick--) {}
|
||||
if (i2c->ISR & ERROR_FLAG || !tick) {
|
||||
DEBUG("[i2c] write: TXIS timeout\n");
|
||||
DEBUG("[i2c] start: Start condition and address generated\n");
|
||||
/* Check if the device is there */
|
||||
if ((i2c->ISR & I2C_ISR_NACKF)) {
|
||||
i2c->ICR |= I2C_ICR_NACKCF;
|
||||
_stop(i2c);
|
||||
return -ENXIO;
|
||||
}
|
||||
/* write data to data register */
|
||||
DEBUG("[i2c] write: Write byte %02X to DR\n", data[i]);
|
||||
i2c->TXDR = data[i];
|
||||
DEBUG("[i2c] write: Sending data\n");
|
||||
|
||||
tick = TICK_TIMEOUT;
|
||||
while (!(i2c->ISR & I2C_ISR_TC) && tick--) {}
|
||||
if (!tick) {
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
|
||||
int ret = _check_bus(i2c);
|
||||
if (ret < 0) {
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
DEBUG("[i2c] write: Waiting for write to complete\n");
|
||||
uint16_t tick = TICK_TIMEOUT;
|
||||
while (!(i2c->ISR & I2C_ISR_TC) && tick--) {}
|
||||
if (i2c->ISR & ERROR_FLAG || !tick) {
|
||||
DEBUG("[i2c] write: write didn't complete\n");
|
||||
return -ENXIO;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int _stop(I2C_TypeDef *i2c)
|
||||
static int _stop(I2C_TypeDef *i2c)
|
||||
{
|
||||
assert(i2c != NULL);
|
||||
|
||||
uint16_t tick = TICK_TIMEOUT;
|
||||
|
||||
/* make sure transfer is complete */
|
||||
DEBUG("[i2c] stop: Wait for transfer to be complete\n");
|
||||
while (!(i2c->ISR & I2C_ISR_TC) && tick--) {}
|
||||
if (i2c->ISR & ERROR_FLAG || !tick) {
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
/* send STOP condition */
|
||||
/* Send stop condition */
|
||||
DEBUG("[i2c] stop: Generate stop condition\n");
|
||||
i2c->CR2 |= I2C_CR2_STOP;
|
||||
|
||||
/* Wait for the stop to complete */
|
||||
tick = TICK_TIMEOUT;
|
||||
uint16_t tick = TICK_TIMEOUT;
|
||||
while ((i2c->CR2 & I2C_CR2_STOP) && tick--) {}
|
||||
if (!tick) {
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
|
||||
DEBUG("[i2c] stop: Stop condition succeeded\n");
|
||||
if (_wait_for_bus(i2c) < 0) {
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
DEBUG("[i2c] stop: Bus is free\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int _check_bus(I2C_TypeDef *i2c)
|
||||
static int _wait_isr_set(I2C_TypeDef *i2c, uint32_t mask, uint8_t flags)
|
||||
{
|
||||
assert(i2c != NULL);
|
||||
uint16_t tick = TICK_TIMEOUT;
|
||||
while (tick--) {
|
||||
uint32_t isr = i2c->ISR;
|
||||
|
||||
if (i2c->ISR & I2C_ISR_NACKF) {
|
||||
DEBUG("[i2c] check_bus: NACK received\n");
|
||||
return -ENXIO;
|
||||
if (isr & I2C_ISR_NACKF) {
|
||||
DEBUG("[i2c] wait_isr_set: NACK received\n");
|
||||
|
||||
/* Some devices have a valid data nack, if indicated don't stop */
|
||||
if (!(flags & I2C_NOSTOP)) {
|
||||
_stop(i2c);
|
||||
}
|
||||
i2c->ICR |= CLEAR_FLAG;
|
||||
return -EIO;
|
||||
}
|
||||
if ((isr & I2C_ISR_ARLO) || (isr & I2C_ISR_BERR)) {
|
||||
DEBUG("[i2c] wait_isr_set: Arbitration lost or bus error\n");
|
||||
_stop(i2c);
|
||||
i2c->ICR |= CLEAR_FLAG;
|
||||
return -EAGAIN;
|
||||
}
|
||||
if (isr & mask) {
|
||||
DEBUG("[i2c] wait_isr_set: ISR 0x%08lX set\n", mask);
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
/*
|
||||
* If timeout occurs this means a problem that must be handled on a higher
|
||||
* level. A SWRST is recommended by the datasheet.
|
||||
*/
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
|
||||
if (i2c->ISR & I2C_ISR_ARLO) {
|
||||
DEBUG("[i2c] check_bus: arbitration lost\n");
|
||||
return -EAGAIN;
|
||||
static inline int _wait_for_bus(I2C_TypeDef *i2c)
|
||||
{
|
||||
uint16_t tick = TICK_TIMEOUT;
|
||||
while (tick-- && (i2c->ISR & I2C_ISR_BUSY)) {}
|
||||
if (!tick) {
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
|
||||
if (i2c->ISR & I2C_ISR_BERR) {
|
||||
DEBUG("[i2c] check_bus: bus error\n");
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user