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cpu/lpc1768/gpio: use gpio_irq feature

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This commit is contained in:
Hauke Petersen 2018-09-21 08:18:55 +02:00
parent c7e6d15990
commit 4913dfaa9f
1 changed files with 83 additions and 79 deletions
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162
cpu/lpc1768/periph/gpio.c
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@ -21,6 +21,7 @@
#include "cpu.h"
#include "periph/gpio.h"
#ifdef MODULE_PERIPH_GPIO_IRQ
/**
* @brief Number of external interrupt lines.
*/
@ -32,6 +33,7 @@
static gpio_isr_ctx_t isr_ctx[NUMOF_IRQS];
static gpio_flank_t isr_state[2][32];
#endif
#define PIN_MASK (0x1f)
#define PORT_SHIFT (5U)
@ -51,45 +53,6 @@ static inline LPC_GPIO_TypeDef *_base(gpio_t pin)
return (LPC_GPIO_TypeDef *) (LPC_GPIO_BASE + (_port(pin) * 0x20));
}
static inline void _configure_flank(gpio_t pin, gpio_flank_t flank)
{
switch (flank) {
case GPIO_RISING:
if (_port(pin) == 0) {
LPC_GPIOINT->IO0IntEnF &= ~(1 << _pin(pin));
LPC_GPIOINT->IO0IntEnR |= (1 << _pin(pin));
}
else {
LPC_GPIOINT->IO2IntEnF &= ~(1 << _pin(pin));
LPC_GPIOINT->IO2IntEnR |= (1 << _pin(pin));
}
break;
case GPIO_FALLING:
if (_port(pin) == 0) {
LPC_GPIOINT->IO0IntEnF |= (1 << _pin(pin));
LPC_GPIOINT->IO0IntEnR &= ~(1 << _pin(pin));
}
else {
LPC_GPIOINT->IO2IntEnF |= (1 << _pin(pin));
LPC_GPIOINT->IO2IntEnR &= ~(1 << _pin(pin));
}
break;
case GPIO_BOTH:
if (_port(pin) == 0) {
LPC_GPIOINT->IO0IntEnF |= 1 << _pin(pin);
LPC_GPIOINT->IO0IntEnR |= 1 << _pin(pin);
}
else {
LPC_GPIOINT->IO2IntEnF |= 1 << _pin(pin);
LPC_GPIOINT->IO2IntEnR |= 1 << _pin(pin);
}
break;
}
}
int gpio_init(gpio_t pin, gpio_mode_t mode)
{
/* check for valid pin */
@ -127,6 +90,86 @@ int gpio_init(gpio_t pin, gpio_mode_t mode)
return 0;
}
int gpio_read(gpio_t pin)
{
LPC_GPIO_TypeDef *base = _base(pin);
return (base->FIOPIN & (1 << _pin(pin))) ? 1 : 0;
}
void gpio_set(gpio_t pin)
{
LPC_GPIO_TypeDef *base = _base(pin);
base->FIOSET = (1 << _pin(pin));
}
void gpio_clear(gpio_t pin)
{
LPC_GPIO_TypeDef *base = _base(pin);
base->FIOCLR = (1 << _pin(pin));
}
void gpio_toggle(gpio_t pin)
{
LPC_GPIO_TypeDef *base = _base(pin);
base->FIOPIN ^= (1 << _pin(pin));
}
void gpio_write(gpio_t pin, int value)
{
LPC_GPIO_TypeDef *base = _base(pin);
if (value) {
base->FIOSET = (1 << _pin(pin));
}
else {
base->FIOCLR = (1 << _pin(pin));
}
}
#ifdef MODULE_PERIPH_GPIO_IRQ
static inline void _configure_flank(gpio_t pin, gpio_flank_t flank)
{
switch (flank) {
case GPIO_RISING:
if (_port(pin) == 0) {
LPC_GPIOINT->IO0IntEnF &= ~(1 << _pin(pin));
LPC_GPIOINT->IO0IntEnR |= (1 << _pin(pin));
}
else {
LPC_GPIOINT->IO2IntEnF &= ~(1 << _pin(pin));
LPC_GPIOINT->IO2IntEnR |= (1 << _pin(pin));
}
break;
case GPIO_FALLING:
if (_port(pin) == 0) {
LPC_GPIOINT->IO0IntEnF |= (1 << _pin(pin));
LPC_GPIOINT->IO0IntEnR &= ~(1 << _pin(pin));
}
else {
LPC_GPIOINT->IO2IntEnF |= (1 << _pin(pin));
LPC_GPIOINT->IO2IntEnR &= ~(1 << _pin(pin));
}
break;
case GPIO_BOTH:
if (_port(pin) == 0) {
LPC_GPIOINT->IO0IntEnF |= 1 << _pin(pin);
LPC_GPIOINT->IO0IntEnR |= 1 << _pin(pin);
}
else {
LPC_GPIOINT->IO2IntEnF |= 1 << _pin(pin);
LPC_GPIOINT->IO2IntEnR |= 1 << _pin(pin);
}
break;
}
}
int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank,
gpio_cb_t cb, void *arg)
{
@ -180,46 +223,6 @@ void gpio_irq_disable(gpio_t pin)
}
}
int gpio_read(gpio_t pin)
{
LPC_GPIO_TypeDef *base = _base(pin);
return (base->FIOPIN & (1 << _pin(pin))) ? 1 : 0;
}
void gpio_set(gpio_t pin)
{
LPC_GPIO_TypeDef *base = _base(pin);
base->FIOSET = (1 << _pin(pin));
}
void gpio_clear(gpio_t pin)
{
LPC_GPIO_TypeDef *base = _base(pin);
base->FIOCLR = (1 << _pin(pin));
}
void gpio_toggle(gpio_t pin)
{
LPC_GPIO_TypeDef *base = _base(pin);
base->FIOPIN ^= (1 << _pin(pin));
}
void gpio_write(gpio_t pin, int value)
{
LPC_GPIO_TypeDef *base = _base(pin);
if (value) {
base->FIOSET = (1 << _pin(pin));
}
else {
base->FIOCLR = (1 << _pin(pin));
}
}
void isr_eint3(void)
{
/* combine all interrupts */
@ -238,3 +241,4 @@ void isr_eint3(void)
cortexm_isr_end();
}
#endif