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cortexm_common: enable FPU on cortex-m4f
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@ -148,22 +148,6 @@ char *thread_stack_init(thread_task_func_t task_func,
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*stk = ~((uint32_t)STACK_MARKER);
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}
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#if defined(CPU_ARCH_CORTEX_M4F) || (CPU_ARCH_CORTEX_M7)
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/* TODO: fix FPU handling for Cortex-M4f */
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/*
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stk--;
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*stk = (unsigned int) 0;
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*/
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/* S0 - S15 */
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/*
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for (int i = 15; i >= 0; i--) {
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stk--;
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*stk = i;
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}
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*/
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#endif
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/* ****************************** */
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/* Automatically popped registers */
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/* ****************************** */
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@ -299,7 +283,7 @@ void __attribute__((naked)) __attribute__((used)) isr_pendsv(void) {
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__asm__ volatile (
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/* PendSV handler entry point */
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/* save context by pushing unsaved registers to the stack */
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/* {r0-r3,r12,LR,PC,xPSR} are saved automatically on exception entry */
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/* {r0-r3,r12,LR,PC,xPSR,s0-s15,FPSCR} are saved automatically on exception entry */
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".thumb_func \n"
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"mrs r0, psp \n" /* get stack pointer from user mode */
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#if defined(CPU_ARCH_CORTEX_M0) || defined(CPU_ARCH_CORTEX_M0PLUS)
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@ -317,11 +301,13 @@ void __attribute__((naked)) __attribute__((used)) isr_pendsv(void) {
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"mov r0, sp \n" /* switch back to the exception SP */
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"mov sp, r12 \n"
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#else
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#if (defined(CPU_ARCH_CORTEX_M4F) || defined(CPU_ARCH_CORTEX_M7)) && defined(MODULE_CORTEXM_FPU)
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"tst lr, #0x10 \n"
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"it eq \n"
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"vstmdbeq r0!, {s16-s31} \n" /* save FPU registers if FPU is used */
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#endif
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"stmdb r0!,{r4-r11} \n" /* save regs */
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"stmdb r0!,{lr} \n" /* exception return value */
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#if defined(CPU_ARCH_CORTEX_M4F) || defined(CPU_ARCH_CORTEX_M7)
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/* "vstmdb sp!, {s16-s31} \n" */ /* TODO save FPU registers */
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#endif
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#endif
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"ldr r1, =sched_active_thread \n" /* load address of current tcb */
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"ldr r1, [r1] \n" /* dereference pdc */
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@ -364,14 +350,16 @@ void __attribute__((naked)) __attribute__((used)) isr_svc(void) {
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"ldr r0, [r0] \n" /* dereference TCB */
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"ldr r1, [r0] \n" /* load tcb->sp to register 1 */
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"ldmia r1!, {r0} \n" /* restore exception return value */
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#if defined(CPU_ARCH_CORTEX_M4F) || defined(CPU_ARCH_CORTEX_M7)
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/* "pop {s16-s31} \n" */ /* TODO load FPU registers */
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#endif
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"ldmia r1!, {r4-r11} \n" /* restore other registers */
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#if (defined(CPU_ARCH_CORTEX_M4F) || defined(CPU_ARCH_CORTEX_M7)) && defined(MODULE_CORTEXM_FPU)
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"tst r0, #0x10 \n"
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"it eq \n"
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"vldmiaeq r1!, {s16-s31} \n" /* load FPU registers if saved */
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#endif
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"msr psp, r1 \n" /* restore user mode SP to PSP reg */
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"bx r0 \n" /* load exception return value to PC,
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* causes end of exception*/
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#endif
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/* {r0-r3,r12,LR,PC,xPSR} are restored automatically on exception return */
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/* {r0-r3,r12,LR,PC,xPSR,s0-s15,FPSCR} are restored automatically on exception return */
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);
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}
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@ -63,14 +63,29 @@ ARCH = $(shell echo $(CPU_ARCH) | tr 'a-z-' 'A-Z_')
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export CFLAGS += -DCPU_ARCH_$(ARCH)
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# set the compiler specific CPU and FPU options
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ifeq ($(CPU_ARCH),cortex-m4f)
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# TODO: enable hard floating points for the M4F once the context save/restore
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# code is adjusted to take care of FPU registers
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#export CFLAGS_FPU += -mfloat-abi=hard -mfpu=fpv4-sp-d16
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export MCPU := cortex-m4
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endif
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ifneq (,$(filter $(CPU_ARCH),cortex-m4f cortex-m7))
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ifneq (,$(filter cortexm_fpu,$(DISABLE_MODULE)))
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export CFLAGS_FPU ?= -mfloat-abi=soft
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else
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USEMODULE += cortexm_fpu
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# clang assumes there is an FPU
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ifneq (llvm,$(TOOLCHAIN))
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ifeq ($(CPU_ARCH),cortex-m7)
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export CFLAGS_FPU ?= -mfloat-abi=hard -mfpu=fpv5-d16
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else
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export CFLAGS_FPU ?= -mfloat-abi=hard -mfpu=fpv4-sp-d16
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endif
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endif
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endif
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ifeq ($(CPU_ARCH),cortex-m4f)
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export MCPU := cortex-m4
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else
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export MCPU ?= $(CPU_ARCH)
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endif
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else
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CFLAGS_FPU ?= -mfloat-abi=soft
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export MCPU ?= $(CPU_ARCH)
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endif
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# CMSIS DSP needs to know about the CPU core
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ifneq (,$(filter cmsis-dsp,$(USEPKG)))
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@ -8,6 +8,7 @@ PSEUDOMODULES += conn_can_isotp_multi
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PSEUDOMODULES += cord_ep_standalone
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PSEUDOMODULES += cord_epsim_standalone
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PSEUDOMODULES += core_%
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PSEUDOMODULES += cortexm_fpu
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PSEUDOMODULES += ecc_%
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PSEUDOMODULES += emb6_router
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PSEUDOMODULES += event_%
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