`flashpage_write_raw()` got renamed to `flashpage_write()`.
Now `sam0_flashpage_aux_write_raw()` is the only remaining 'raw'
function, even though it behaves just like `flashpage_write()`.
So let's also rename that for consistency.
The https://github.com/mitls/hacl-c repo was deleted.
Getting the new upstream (https://github.com/project-everest/hacl-star)
to work nicely as a package requires some non-trivial work and in the
meantime all CI jobs will fail.
As a short-term solution, switch the upstream to a backup version of
the original repository.
With the last cleanup an error sneaked in:
Now the 2.4 GHz interface is disabled, when the `at86rf215m` module
(chip with sub-GHz radio only) is *not* used.
This is the reverse of what should happen.
Flash Customer Configuration Area (CCA) is never written when the
riotboot module is used. This required a riot application to have
been previously flashed. riotboot will completely ignore this
section, neither writing or erasing it.
Slot flashing is currenly only supported with Jlink.
Co-authored-by: Brenton Chetty <brent7984@gmail.com>
If multiple debuggers are present when testing for JLinkExe version
a GUI will open to select the debugger to attach, so add -nogui
when testing for version as well.
stm32mp157c-dk2 has not enough memory to build this apps.
However as the stm32mp157xx cpu line has no flash, a part of RAM
is considered as ROM. Thus ROM size could be extend to suit this
apps needs.
Signed-off-by: Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
As the STM32MP157Cxx has no CMSIS header repositories, SUCCESS enum
is not defined.
Thus STM32MP157Cxx line must be specifically handled as the
STM32F030x4 line to create missing enums.
Signed-off-by: Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
This board is based on a stm32mp157cac which has a dual architecture:
* Dual core Cortex-A7
* Cortex-M4
Only Cortex-M4 is supported by RIOT-OS.
Cortex-M4 can be used in Engineering mode if stm32mp1_eng_mode
pseudomodule is used.
By default the RIOT firmware can be loaded by Linux on the Cortex-M4
using remoteproc Linux framework.
This the initial commit with a limited set of supported peripheral:
* gpio
* timer
* uart
Signed-off-by: Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
Note that Kconfig.models was not generated with gen_kconfig.py tool
due to lack of ProductsList.xlsx file for STM32MP1 family.
Signed-off-by: Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
In STM32MP1 family, independant watchdogs (IWDG1 and IWDG2) are
dedicated to the MPU (Cortex-A7). Thus simply disable the feature
for STM32MP1 family.
Signed-off-by: Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
The stm32mp157c has the particularity to not having flash memory but
only SRAM.
Thus a part of SRAM must be considered as a ROM to flash the firmware
into.
In case of the stm32mp157c, the RETRAM (64kB) is used as ROM and the
4 banks of SRAM (384kB) are used as RAM.
However, as ROM_LEN, RAM_LEN, ROM_START_ADDRESS, RAM_START_ADDRESS and
ROM_OFFSET could be overloaded by user, set them with "?=" operator.
If the ROM_START_ADDRESS and the RAM_START_ADDRESS are not set at the
end of that file, it is a classic stm32 MCU with flash, thus set this
variables with common memory addresses for stm32 MCU family:
ROM_START_ADDR ?= 0x08000000
RAM_START_ADDR ?= 0x20000000
Signed-off-by: Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
In Engineering mode (BOOT0 off and BOOT2 on), only the Cortex-M4
core is running. It means that all clocks have to be setup
by the Cortex-M4 core.
In other modes, the clocks are setup by the Cortex-A7 and then should
not be setup by Cortex-M4.
stm32mp1_eng_mode pseudomodule have to be used in Engineering mode
to ensure clocks configuration with IS_USED(MODULE_STM32MP1_ENG_MODE)
macro.
This macro can also be used in periph_conf.h to define clock source
for each peripheral.
Signed-off-by: Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
STM32_PM_STOP and STM32_PM_STANDBY are always defined in periph_cpu.h,
Thus it is not needed to test them.
Signed-off-by: Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
According to stm32mp157 documentation:
* "The CStop mode is entered for MCU when the SLEEPDEEP bit in the Cortex®-M4 System Control
register is set." Thus set PM_STOP_CONFIG to 0.
* "The CStandby mode applies only to the MPU sub-system."
Set PM_STANDBY_CONFIG to (0) and do not enter standby mode for
stm32mp1.
As PM_STOP_CONFIG is already defined before for CPU_FAM_STM32WB, replace
it with CPU_FAM_STM32MP1.
Signed-off-by: Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
