CS and MODE are a bit too generic macros and may conflict with headers
defined by the CPU, like in the QN908x case.
This patch renames them to BUS_CS and BUS_MODE to keep it consistent
with the other BUS names.
The SPI0 (FLEXCOMM2) is connected to a 2 Mb (256 KB) NAND flash
MX25R2035F in the board. This patch configures the SPI bus with the
CS line used for this flash chip.
This patch implements the basic support the last of the FLEXCOMM modes,
Serial Peripheral Interface, in a simple blocking mode with busy wait,
which is enough to test all the SPI functionality end-to-end.
Tested reading and writing registers on a SPI peripheral, and checked
with the oscilloscope that the frequencies were as expected.
Results from `tests/periph_spi`:
```
> init 0 0 2 -1 0
SPI_DEV(0) initialized: mode: 0, clk: 2, cs_port: -1, cs_pin: 0
> bench
1 - write 1000 times 1 byte: 16002 16009
2 - write 1000 times 2 byte: 18001 18008
3 - write 1000 times 100 byte: 802000 802007
4 - write 1000 times 1 byte to register: 24003 24010
5 - write 1000 times 2 byte to register: 26001 26008
6 - write 1000 times 100 byte to register: 810001 810008
7 - read 1000 times 2 byte: 23003 23009
8 - read 1000 times 100 byte: 807002 807009
9 - read 1000 times 2 byte from register: 32002 32009
10 - read 1000 times 100 byte from register: 816002 816009
11 - transfer 1000 times 2 byte: 23003 23009
12 - transfer 1000 times 100 byte: 807003 807010
13 - transfer 1000 times 2 byte to register: 32003 32009
14 - transfer 1000 times 100 byte to register:816002 816009
15 - acquire/release 1000 times: 7222 7228
-- - SUM: 5059250 5059351
```
The macro was moved from Kconfig to the periph_cpu.h which means that
the macro name needed to be updated to BOARD_HAS_ADC_PA06_CAP instead
of CONFIG_BOARD_HAS_ADC_PA06_CAP.
The QN9080DK board has 6 Analog Input lines in the J6 header, labeled
"A0" to "A5". This configuration enables these lines as ADC lines 0 to 5
as well as some other channel options available as lines 6 and up.
The ADC in the QN908x cpu offers multiple options for ADC conversion
using up to 8 external pins, one external reference pin and some
internal signals like a 1.2V reference, Vss, Vcc and an internal
temperature monitor.
This patch implements support for sampling ADC values from the ADC lines
defined in the board configuration. Some configurations are really
always present and don't require a board configuration, like the Vcc or
internal temperature monitor but to coexist with other board ADC line
options they are only set as part of the board configuration.
RISC-V support semihosting in very similar way as the cortex-m
microcontrollers. The code calls a breakpoint instruction and the
attached debugger reads/writes registers and memory for stdio.
The RISC-V architecture doesn't support a call number with the EBREAK
instruction, to allow the debugger to detect a semihosting break point,
the EBREAK instruction is wrapped in a SLLI and SRAI instruction. These
use x0 as output register, making them NOP instructions.
One caveat when using this is that the RISC-V core traps the EBREAK
instruction with trap code 3 when no debugger is attached. Restarting
the application with the debugger attached avoids this.
