Previous value was 20 K, now it's 80 K. The older family of these MCUs
(cc13x0, cc26x0) had that size, currently for cc13x2 and cc26x2 it's
80 K.
Signed-off-by: Jean Pierre Dudey <jeandudey@hotmail.com>
From the data sheet:
> **Note:** Only in case when a reset occurs and the POR = 0, the BODR bit
indicates if the V DD(DCDC)(3V3) voltage was below 2.6 V or not.
So the value of BODR is undefined if POR is set.
Clear it to bring it to a defined state.
The function would always return `true` after early boot, so it
is not very useful for applications.
Now it will only (but always) return true when we woke from Deep Sleep
*after* early boot. This makes it behave the same ways as the function
of the same name on SAME54.
Rename the existing function to cpu_backup_ram_is_initialized() to better
match it's semantics.
On the MCB2388 plugging the power will result in both the POR and EXTR
bit being set.
Not sure if this is a property of the board, but it means RTC is also
reset after programming, so it behaves just like Backup RAM.
If we woke from Deep Sleep the POR bit will be cleared, so the RTC is not
reset.
RSIR is 0x1 (POR) if we woke from Deep Sleep.
This makes it hard to distinguish between real power-on and waking from
Deep Sleep, which is why the Backup RAM signature was introduced.
However, calling cpu_woke_from_backup() a second time will always return
true, as the signature will have been set up by early boot then.
Thus, clear the POR bit if the signature was already in place.
The result is:
RSIR == 0 -> woke from sleep
RSIR == 1 -> cold boot
Calling localtime() adds considerable overhead.
There are easier ways to set the date to 1970.
For tests/periph_rtc this results in this ROM change:
master:
text data bss dec hex
31328 240 98064 129632 1fa60
with this patch:
text data bss dec hex
20036 140 98168 118344 1ce48
The reboot process for ATmegas is to enable the watchdog timer and loop until
the wdt reboots this MCU. However, this reboot will keep the wdt configuration,
so that the wdt needs to be disabled during boot. This is done in get_mcusr,
but without the attribute "used" it will be optimized out in LTO builds. This
commits adds the attribute "used" to get_mcusr.
Also simplified the backward compatibility with older ATmegas (currently not
supported by RIOT) on outdated versions of avrlibc.
bitarithm.h is not needed for the interface of shed but may cause conflicts
due to different definitions of SETBIT and CLRBIT
common implementations are: (value, offset) xor (value, mask) bitarithm
implements the later
frac.c and nrf52/usbdev.c use bitarithm.h but where missing the include
sam0/rtt.c defined a bit using mask from bitarithm,
changed that to the soulution used in sam0/rtc.c
Instead of hard-coding the peripheral clocks to CLOCK_CORECLOCK
introduce helper functions to return the frequency of the individual
GCLKs and use those for baud-rate calculations.
This requires the GCLK to be part of the peripheral's config struct.
While this is already the case for most peripherals, this also adds
it for those where it wasn't used before.
As it defaults to 0 (CLOCK_CORECLOCK) no change is to be expected.
To simplify board definitions and for unification between samd2x and
newer models, don't use the GCLK bitmask in board definitions.
Instead use the GCLK index and generate the bitmask when needed.
There is size difference for atomic_int_fast8 and atomiic_uint_fast8
on FreeBSD, i.e., they match uint32_t with size of 4 bytes instead of
uint8_t with size of 8. Hence, tests/c11_atomics_cpp_compat buildtest
fails on FreeBSD.
The CC26x2 and CC13x2 share the same register definitions, and both are
treated equally in the TI's technical reference manual. [1]
- To avoid confusions in the future I renamed it to `cc26x2_cc13x2`.
- Documentation was updated.
- The `cc1312-launchpad` board that uses the `cc13x2` MCU was updated.
- The `cc1352-launchpad` board that uses the `cc13x2` MCU was updated.
[1]: https://www.ti.com/lit/ug/swcu185d/swcu185d.pdf
Signed-off-by: Jean Pierre Dudey <jeandudey@hotmail.com>
With the new toolchain version required to fix issue #13133, the compilation of `examples/posix_socket` fails due to a C linkage error in `atomic_base.h`. The reason is that including `drivers/include/mtd.h` in `boards/esp32/board_common.h` inside the `extern C` block finally leads to including `atomic_base.h` inside the `extern C` block which in turn to the C linkage error for the template definitions in this file.
For atmega boards a TX has not actually completed until UDRn is empty
as well as the Transmit Shift Register.
To avoid resetting an UART before a TX has completed we use the TXCn
flash and ISR to set a variables that indicates TX is ongoing. This
allows not reseting the UART while there are ongoing TX pending.
This fixes an issue where part of the last byte is not shifted out
of the TX shift register causing rubish on the first TX following an
uart_init.
The ADC_STATUS_SINGLEACT indicates that an operation is active, while
the ADC_STATUS_SINGLEDV indicates that data is valid.
This fixes ADC returning values of unfinished reads.
Without this change a RIOT application compiled with all-asan will
segfault as RIOT provides its own malloc by default. Add a define for
disabling custom malloc, calloc and realloc implementations and use it
when compiling with all-asan.
ESP32 can be clocked with either a 40 MHz or 26 MHz crystal. Since most boards use a 40 MHz crystal, the configuration was previously fixed to a 40 MHz crystal. This commit changes the crystal from 40 MHz to automatic detection, allowing boards with a 26 MHz crystal like the Sparkfun ESP32 Thing DEV to be used.
- Unecessary definitions are removed.
- Since the 48-bit RTC hardware timer uses a RC oscillator as clock, it is pretty inaccurate and leads to a RTC time deviation of up to 3 seconds per minute. Therefore, a calibration during the boot time determines a correction factor for the 48-bit RTC hardware timer. Function _rtc_time_to_us uses now this correction factor and converts a raw 48-bit RTC time to a corrected time in microseconds. Thus, the 48-bit RTC timer becomes much more accurate, but it can't still reach the accuracy of the PLL driven 64-bit system timer. The Advantage of using RTC over 64-bit sydtem timer is that it also continues in deep sleep mode and after software reset.
- If the 64-bit system timer is used to emulate the RTC timer, it uses the RTC hardware timer to continue its operation after software .
It is possible to use different timers as RTC timer for the periph_rtc module. Either the 48-bit RTC hardware timer is used directly or the PLL driven 64-bit system timer emulates a RTC timer. The latter one is much more accurate. Pseudomodule esp_rtc_timer controlls which timer is used. Only if esp_rtc_timer is enabled explicitly, the 48-bit RTC hardware timer is used. Otherwise the 64-bit sytstem timer is used to emulate the RTC timer.
The explicit call of rtc_init during the CPU start was removed because rtc_init is called within the function periph_init. The display of the system time at startup had to be placed after the call to periph_init.
There is an existing function that returns the system time in us as a 64 bit value. Converting this 64 value in us to a 32 bit value in ms is more easier and uses the complete 32 bit range. Using only the low part of the 64 bit system time in us and dividing it by 1e3 cuts the 32 bit range.
To control the log level and the format of the log output of SDK libraries, a bunch of library-specific printf functions are realized which map the log output from SDK libraries to RIOT's log macros.
The buffer[EHTHERNET_MAX_LEN] used in _esp_wifi_send to convert the iolist of the given packet to a plain buffer for the WiFi interface should not be on the stack to prevent the sending thread's stack from overflowing.
- Using a enum instead of _COUNTER is easier to read
- _COUNTER is also a reserved name; so better not use it to avoid issues
- Split out the pcint code into a static inline function for increased
readability
The bank index and the pin number are not necessarily identical. For all
PCINT banks except for bank 3 bank_idx was used therefore. It was likely
just forgotten to update that for bank 3 as well.
Some ESP8266/ESP8285 modules only work with DOUT SPI flash mode and a SPI flash frequency of 26 MHz. Therefore, these parameters have to be used by default. Otherwise some modules will no boot.
For better compatibility copy most of cortexm_base.ld
and use the same section names.
Only interrupt stacks and the two additional (currently unused)
heap sections are different between the two now.
Both architectures are variants of the ARM architecture and use the same
toolchain.
There is no reason to have such wildly different defaults.
This results in some tests passing that would crash before:
- [x] `tests/pkg_libcose`
- [x] `tests/pkg_qdsa`
- [x] `tests/pkg_relic`
- [x] `tests/pkg_tweetnacl`
- [x] `tests/pthread_tls`
`THREAD_EXTRA_STACKSIZE_PRINTF_FLOAT` is not used anywhere in RIOT
anymore, so just drop it.
