MrKevinWeiss
7a68fb0d5e
*Kconfig*: Remove dep-only Kconfig files
2024-03-26 14:54:22 +01:00
Jason Parker
b5d72d8242
cpu/stm32: add CPU_FAM_STM32C0 support
2024-01-29 14:44:10 -05:00
Gunar Schorcht
337a63ecb5
cpu/stm32/periph: add SDMMC support for F2/F4/F7/L4
2023-12-21 18:37:43 +01:00
Gunar Schorcht
c628486f5f
cpu/stm32: enable HSI48 for periph_usbdev
2023-07-05 09:40:24 +02:00
Gunar Schorcht
4a0b6a0cb2
cpu/stm32: fix RNG clock configuration for STM32U5
...
The RNG can use HSI48, HSI48/2 or HSI16. Using MSI as 48 MHz clock source for RNG is not possible. The clock configuration in `stmclk_u5.c` activates anyway only the MSIS but not the MSIK which could be used for certain peripherals.
Therefore, this commit
- removes the configuration of MSI as 48 MHz clock for RNG and its selection in `RCC->CCIPR1.ICLKSEL`
- enables HSI48 and selects it for RNG.
The HSI48 will also be used in future for certain peripherals such as USB OTG FS and SDMMC.
2023-07-04 18:07:15 +02:00
MrKevinWeiss
17cce015d4
treewide/stm32: Make CLOCK_HS* configurable
2022-11-03 11:37:28 +01:00
Gunar Schorcht
76848492b0
cpu/stm32: add tinyUSB package support
2022-09-30 19:05:51 +02:00
Fabian Hüßler
70d3d647d1
cpu/{cortexm_common, stm32}: add support for backup RAM
2022-01-21 15:53:18 +01:00
deccc720e3
cpu/stm32: add support for LTDC periph
2022-01-07 14:32:24 +01:00
2f0efa8c9e
cpu/stm32: add initial support for stm32u5 family
2021-12-23 11:04:41 +01:00
dylad
f5cd2d1438
cpu/stm32: enable HSI48 when needed for L4/Wx
2021-12-02 14:26:03 +01:00
337b99002a
cpu/stm32/stmclk: enable 48MHz when usbdev is used
2021-12-01 10:15:19 +01:00
16db45f77e
cpu/stm32: fix missing clock configuration defines for g0
2021-11-29 14:12:18 +01:00
Jan Romann
4384795cb9
treewide: Remove excessive newlines
2021-08-13 19:50:38 +02:00
Akshai M
a4bbf0cffc
cpu/stm32 : APB3 and VDDTCXO config
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Add APB3 disable, Enable VDDTCXO for Radio
2021-07-09 11:16:41 +02:00
MrKevinWeiss
02a2de4916
cpu/stm32: Add Kconfig dependency modeling
2021-07-02 15:11:05 +02:00
aidiaz
fc1cd85c76
cpu/stm32/periph_rtt: RTT peripheral support for CPU_FAM_STM32L5
2021-06-15 09:49:55 -04:00
Akshai M
efb86039c6
cpu/stm32wl: Add RTT support
2021-04-20 21:04:36 +02:00
Akshai M
fd8ddd6161
boards: add nucleo-wl55jc
...
Co-authored-by: Kevin "Tristate Tom" Weiss <weiss.kevin604@gmail.com>
2021-04-20 21:04:29 +02:00
Akshai M
c485c774cf
cpu/stm32: add stm32wl
2021-04-20 20:57:48 +02:00
Gilles DOFFE
4bfbb75578
cpu/stm32: add stm32mp1_eng_mode pseudomodule
...
In Engineering mode (BOOT0 off and BOOT2 on), only the Cortex-M4
core is running. It means that all clocks have to be setup
by the Cortex-M4 core.
In other modes, the clocks are setup by the Cortex-A7 and then should
not be setup by Cortex-M4.
stm32mp1_eng_mode pseudomodule have to be used in Engineering mode
to ensure clocks configuration with IS_USED(MODULE_STM32MP1_ENG_MODE)
macro.
This macro can also be used in periph_conf.h to define clock source
for each peripheral.
Signed-off-by: Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
2020-11-13 10:43:08 +01:00
Gilles DOFFE
c3e29bb1fa
cpu/stm32: setup clocks for stm32mp1
...
As stm32mp1 clocks are not configured like for other stm32, do not use
stmclk_common.c
Signed-off-by: Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
2020-11-13 10:43:08 +01:00
Gilles DOFFE
8279e54272
cpu/stm32: add clock configuration for stm32mp1
...
Configure stm32mp1 Cortex-M4 MCU core clock according to board
configuration.
Signed-off-by: Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
2020-11-13 10:43:08 +01:00
ef5897775d
cpu/stm32l4wb: add missing define for PLL HSI source
2020-11-10 09:34:07 +01:00
Francisco
aa79f4da17
Merge pull request #15078 from aabadie/pr/cpu/stm32f0f1f3_mco
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cpu/stm32f0f1f3: add MCO configuration and initialization
2020-11-06 08:56:43 +01:00
afba298bc1
cpu/stm32f0f1f3: configure and initialize MCO
2020-11-05 21:59:00 +01:00
565242f67e
Merge pull request #15073 from aabadie/pr/cpu/stm32l0l1_mco
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cpu/stm32l0l1: add MCO configuration and initialization
2020-11-05 17:03:32 +01:00
f98f5f5b49
Merge pull request #15084 from aabadie/pr/cpu/stm32gx_mco
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cpu/stm32gx: add MCO configuration and initialization
2020-11-05 16:46:04 +01:00
5a2409557f
cpu/stm32gx: configure and initialize MCO
2020-11-05 13:39:19 +01:00
4b316c593a
cpu/stm32l0l1: configure MCO
2020-11-05 13:37:34 +01:00
18b5f417d1
cpu/stm32l4: implement MCO configuration
2020-11-05 13:34:45 +01:00
a416b2793f
cpu/stm32: add basic support for stm32l5
2020-10-23 18:21:50 +02:00
72c17588b9
boards/stm32: remove unused CLOCK_LSE define
2020-10-21 12:11:17 +02:00
9f985e8e56
cpu/stm32: use CONFIG_BOARD_HAS_LSE instead of CLOCK_LSE
2020-10-21 12:10:53 +02:00
84306f1122
cpu/stm32: remove unused CLOCK_HSE define
2020-10-21 10:11:46 +02:00
42f71914a5
cpu/stm32: simplify stmclk_disable_hsi function
...
There is no need to check for CLOCK_HSE or to check if HSI is used as SYSCLK, this is already checked at compile time in the clock initialization code
2020-10-20 22:13:50 +02:00
2f053c90bd
cpu/stm32gx: improve clock initialization sequence
2020-10-20 15:47:21 +02:00
e2ae50258a
cpu/stm32gx: factorize HSE clock activation
2020-10-20 14:29:22 +02:00
2d603269dd
cpu/stm32gx: disable hsi only if unused
2020-10-20 14:29:11 +02:00
20894e47a6
cpu: boards: stm32gx: use IS_ACTIVE macro for clock config
2020-10-20 14:29:11 +02:00
a96ca57f66
cpu/stm32gx: remove useless LSE clock initialization
2020-10-20 14:29:11 +02:00
d78a316139
cpu: boards: stm32gx: compile code for all possible clock modes
2020-10-20 14:29:11 +02:00
d1724d6718
cpu/stm32l4: correctly handle clock freq > 80MHz
2020-10-20 11:37:46 +02:00
00ea7ffa55
cpu/stm32l4wb: cleanup clock initialization
2020-10-20 11:37:46 +02:00
d7d5d9d651
boards/stm32l4: extend clock configuration
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- add PLLQ default value
- better tune default PLLM value depending on HSE value
- ensure CLOCK_PLL_SRC is always defined
2020-10-20 11:37:45 +02:00
b11d65ab70
cpu/stm32l4: enable PLLQ as 48MHz source if possible
2020-10-20 11:37:45 +02:00
e51279b228
cpu/stm32l0: fix clk control register reset
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on stm32l011, RCC_CR_CSSON is not defined
2020-10-15 16:24:33 +02:00
044acf1175
cpu/stm32: enable power overdrive on f4 and f7
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This is only enabled if the HCLK clock is above 168MHz on F4 and 180MHz on f7
2020-10-14 13:36:20 +02:00
0d786e3dbb
cpu: boards: stm32f2/f4/f7: rework clock configuration and init
2020-10-06 16:10:05 +02:00
da9168c652
cpu/stm32: rename stmclk_fx to stmclk_f2f4f7
...
This commit also removes all f0/f1/f3 specific code from this file
2020-09-24 11:27:24 +02:00
