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cpu/stm32: add initial support for stm32u5 family

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This commit is contained in:
Alexandre Abadie 2021-12-15 15:53:53 +01:00
parent d7195cdd1d
commit 2f0efa8c9e
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GPG Key ID: 1C919A403CAE1405
29 changed files with 868 additions and 70 deletions
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1
cpu/stm32/Makefile.cmsis
View File

@ -15,6 +15,7 @@ PKG_VERSION_l0=532d96973e7b2ae5546a2c88cb216429f74f5f5d # v1.9.2
PKG_VERSION_l1=1827333a7f7822282a6a46e4169596b5fb58cf61 # v2.3.2
PKG_VERSION_l4=26ed4846f831f730d852507e178061053e522daf # v1.7.1
PKG_VERSION_l5=fcf61cd086e02c7a1cf7535ffe30622d1f5d36aa # v1.0.4
PKG_VERSION_u5=147947d99f50554101d2a339ad19c2972c3ff161 # v1.0.1
PKG_VERSION_wb=3a801574163338b562f56e7eb503a955818f1a56 # v1.9.0
PKG_VERSION_wl=7bf548678b1132d829072ce86443c8036d538460 # v1.1.0

6
cpu/stm32/Makefile.features
View File

@ -12,12 +12,12 @@ FEATURES_PROVIDED += periph_rtt_overflow
FEATURES_PROVIDED += periph_uart_modecfg
FEATURES_PROVIDED += periph_uart_nonblocking
ifneq (,$(filter $(CPU_FAM),f0 f1 f3 g0 g4 l0 l1 l4 l5 wb wl))
ifneq (,$(filter $(CPU_FAM),f0 f1 f3 g0 g4 l0 l1 l4 l5 u5 wb wl))
FEATURES_PROVIDED += periph_flashpage
FEATURES_PROVIDED += periph_flashpage_pagewise
endif
ifneq (,$(filter $(CPU_FAM),f0 f2 f3 f4 f7 l0 l1 l4 l5 wb wl))
ifneq (,$(filter $(CPU_FAM),f0 f2 f3 f4 f7 l0 l1 l4 l5 u5 wb wl))
CPU_MODELS_WITHOUT_RTC_BKPR += stm32f030% stm32f070%
ifeq (,$(filter $(CPU_MODELS_WITHOUT_RTC_BKPR),$(CPU_MODEL)))
FEATURES_PROVIDED += periph_rtc_mem
@ -41,7 +41,7 @@ endif
# Not all F4 and L0 parts implement a RNG.
CPU_MODELS_WITHOUT_HWRNG = stm32f401% stm32f411% stm32f446% stm32l031% stm32l011%
ifneq (,$(filter $(CPU_FAM),f2 f4 f7 g4 l0 l4 l5 wb))
ifneq (,$(filter $(CPU_FAM),f2 f4 f7 g4 l0 l4 l5 u5 wb))
ifeq (,$(filter $(CPU_MODELS_WITHOUT_HWRNG),$(CPU_MODEL)))
FEATURES_PROVIDED += periph_hwrng
endif

78
cpu/stm32/cpu_common.c
View File

@ -37,15 +37,17 @@ static const uint8_t apbmul[] = {
#if (CLOCK_APB1 < CLOCK_CORECLOCK)
[APB1] = 2,
#if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \
defined(CPU_FAM_STM32G4) || defined(CPU_FAM_STM32L5) || \
defined(CPU_FAM_STM32WL) || defined(CPU_FAM_STM32G0)
defined(CPU_FAM_STM32G0) || defined(CPU_FAM_STM32G4) || \
defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32U5) || \
defined(CPU_FAM_STM32WL)
[APB12] = 2,
#endif
#else
[APB1] = 1,
#if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \
defined(CPU_FAM_STM32G4) || defined(CPU_FAM_STM32L5) || \
defined(CPU_FAM_STM32WL) || defined(CPU_FAM_STM32G0)
defined(CPU_FAM_STM32G0) || defined(CPU_FAM_STM32G4) || \
defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32U5) || \
defined(CPU_FAM_STM32WL)
[APB12] = 1,
#endif
#endif
@ -79,7 +81,7 @@ void periph_clk_en(bus_t bus, uint32_t mask)
case APB1:
#if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \
defined(CPU_FAM_STM32G4) || defined(CPU_FAM_STM32L5) || \
defined(CPU_FAM_STM32WL)
defined(CPU_FAM_STM32U5) || defined(CPU_FAM_STM32WL)
RCC->APB1ENR1 |= mask;
#elif defined(CPU_FAM_STM32G0)
RCC->APBENR1 |= mask;
@ -98,14 +100,14 @@ void periph_clk_en(bus_t bus, uint32_t mask)
#endif
break;
#endif
#if defined(CPU_FAM_STM32WL)
#if defined(CPU_FAM_STM32WL) || defined(CPU_FAM_STM32U5)
case APB3:
RCC->APB3ENR |= mask;
break;
#endif
#if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \
defined(CPU_FAM_STM32G4) || defined(CPU_FAM_STM32L5) || \
defined(CPU_FAM_STM32WL)
defined(CPU_FAM_STM32U5) || defined(CPU_FAM_STM32WL)
case APB12:
RCC->APB1ENR2 |= mask;
break;
@ -129,15 +131,25 @@ void periph_clk_en(bus_t bus, uint32_t mask)
#elif defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4) || \
defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32F7) || \
defined(CPU_FAM_STM32WB) || defined(CPU_FAM_STM32G4) || \
defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32WL)
defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32U5) || \
defined(CPU_FAM_STM32WL)
case AHB1:
RCC->AHB1ENR |= mask;
break;
/* STM32F410 RCC doesn't provide AHB2 and AHB3 */
#if !defined(CPU_LINE_STM32F410Rx)
case AHB2:
#if defined(CPU_FAM_STM32U5)
RCC->AHB2ENR1 |= mask;
#else
RCC->AHB2ENR |= mask;
#endif
break;
#if defined(CPU_FAM_STM32U5)
case AHB22:
RCC->AHB2ENR2 |= mask;
break;
#endif
case AHB3:
RCC->AHB3ENR |= mask;
break;
@ -162,7 +174,7 @@ void periph_clk_dis(bus_t bus, uint32_t mask)
case APB1:
#if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \
defined(CPU_FAM_STM32G4) || defined(CPU_FAM_STM32L5) || \
defined(CPU_FAM_STM32WL)
defined(CPU_FAM_STM32U5) || defined(CPU_FAM_STM32WL)
RCC->APB1ENR1 &= ~(mask);
#elif defined(CPU_FAM_STM32G0)
RCC->APBENR1 &= ~(mask);
@ -182,14 +194,14 @@ void periph_clk_dis(bus_t bus, uint32_t mask)
#endif
break;
#endif
#if defined(CPU_FAM_STM32WL)
#if defined(CPU_FAM_STM32WL) || defined(CPU_FAM_STM32U5)
case APB3:
RCC->APB3ENR &= ~(mask);
break;
#endif
#if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \
defined(CPU_FAM_STM32G4) || defined(CPU_FAM_STM32L5) || \
defined(CPU_FAM_STM32WL)
defined(CPU_FAM_STM32U5) || defined(CPU_FAM_STM32WL)
case APB12:
RCC->APB1ENR2 &= ~(mask);
break;
@ -213,15 +225,25 @@ void periph_clk_dis(bus_t bus, uint32_t mask)
#elif defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4) || \
defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32F7) || \
defined(CPU_FAM_STM32WB) || defined(CPU_FAM_STM32G4) || \
defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32WL)
defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32U5) || \
defined(CPU_FAM_STM32WL)
case AHB1:
RCC->AHB1ENR &= ~(mask);
break;
/* STM32F410 RCC doesn't provide AHB2 and AHB3 */
#if !defined(CPU_LINE_STM32F410Rx)
case AHB2:
#if defined(CPU_FAM_STM32U5)
RCC->AHB2ENR1 &= ~(mask);
#else
RCC->AHB2ENR &= ~(mask);
#endif
break;
#if defined(CPU_FAM_STM32U5)
case AHB22:
RCC->AHB2ENR2 &= ~(mask);
break;
#endif
case AHB3:
RCC->AHB3ENR &= ~(mask);
break;
@ -239,25 +261,34 @@ void periph_clk_dis(bus_t bus, uint32_t mask)
}
#if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32G4) || \
defined(CPU_FAM_STM32L5)
defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32U5)
void periph_lpclk_en(bus_t bus, uint32_t mask)
{
switch (bus) {
case APB1:
RCC->APB1SMENR1 |= mask;
break;
case APB2:
RCC->APB2SMENR |= mask;
break;
case APB12:
RCC->APB1SMENR2 |= mask;
break;
case APB2:
RCC->APB2SMENR |= mask;
break;
case AHB1:
RCC->AHB1SMENR |= mask;
break;
case AHB2:
#if defined(CPU_FAM_STM32U5)
RCC->AHB2SMENR1 |= mask;
#else
RCC->AHB2SMENR |= mask;
#endif
break;
#if defined(CPU_FAM_STM32U5)
case AHB22:
RCC->AHB2SMENR2 |= mask;
break;
#endif
case AHB3:
RCC->AHB3SMENR |= mask;
break;
@ -273,18 +304,27 @@ void periph_lpclk_dis(bus_t bus, uint32_t mask)
case APB1:
RCC->APB1SMENR1 &= ~(mask);
break;
case APB2:
RCC->APB2SMENR &= ~(mask);
break;
case APB12:
RCC->APB1SMENR2 &= ~(mask);
break;
case APB2:
RCC->APB2SMENR &= ~(mask);
break;
case AHB1:
RCC->AHB1SMENR &= ~(mask);
break;
case AHB2:
#if defined(CPU_FAM_STM32U5)
RCC->AHB2SMENR1 &= ~(mask);
#else
RCC->AHB2SMENR &= ~(mask);
#endif
break;
#if defined(CPU_FAM_STM32U5)
case AHB22:
RCC->AHB2SMENR2 &= ~(mask);
break;
#endif
case AHB3:
RCC->AHB3SMENR &= ~(mask);
break;

4
cpu/stm32/cpu_init.c
View File

@ -336,7 +336,9 @@ void cpu_init(void)
/* initialize the Cortex-M core */
cortexm_init();
/* enable PWR module */
#if !defined(CPU_FAM_STM32WB) && !defined(CPU_FAM_STM32MP1) && \
#if defined(CPU_FAM_STM32U5)
periph_clk_en(AHB3, RCC_AHB3ENR_PWREN);
#elif !defined(CPU_FAM_STM32WB) && !defined(CPU_FAM_STM32MP1) && \
!defined(CPU_FAM_STM32WL)
periph_clk_en(APB1, BIT_APB_PWREN);
#endif

2
cpu/stm32/dist/irqs/gen_irqs.py vendored
View File

@ -52,6 +52,8 @@ def list_cpu_lines(cmsis_dir, cpu_fam):
headers.remove("Templates")
if "partition_stm32l5xx.h" in headers:
headers.remove("partition_stm32l5xx.h")
if "partition_stm32u5xx.h" in headers:
headers.remove("partition_stm32u5xx.h")
headers.remove("stm32{}xx.h".format(cpu_fam))
headers.remove("system_stm32{}xx.h".format(cpu_fam))
return sorted([header.split(".")[0] for header in headers])

8
cpu/stm32/include/clk/cfg_clock_common_lx_wx.h → cpu/stm32/include/clk/cfg_clock_common_lx_u5_wx.h
View File

@ -13,15 +13,15 @@
* @{
*
* @file
* @brief Base STM32Lx/Wx clock configuration
* @brief Base STM32Lx/U5/Wx clock configuration
*
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
* @author Vincent Dupont <vincent@otakeys.com>
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
*/
#ifndef CLK_CFG_CLOCK_COMMON_LX_WX_H
#define CLK_CFG_CLOCK_COMMON_LX_WX_H
#ifndef CLK_CFG_CLOCK_COMMON_LX_U5_WX_H
#define CLK_CFG_CLOCK_COMMON_LX_U5_WX_H
#ifdef __cplusplus
extern "C" {
@ -88,5 +88,5 @@ extern "C" {
}
#endif
#endif /* CLK_CFG_CLOCK_COMMON_LX_WX_H */
#endif /* CLK_CFG_CLOCK_COMMON_LX_U5_WX_H */
/** @} */

6
cpu/stm32/include/clk/clk_conf.h
View File

@ -29,8 +29,8 @@
defined(CPU_FAM_STM32MP1)
#include "cfg_clock_common_fx_gx_mp1.h"
#else /* CPU_FAM_STM32L0 || CPU_FAM_STM32L1 || CPU_FAM_STM32L4 ||
* CPU_FAM_STM32L5 || CPU_FAM_STM32WB */
#include "cfg_clock_common_lx_wx.h"
* CPU_FAM_STM32L5 || CPU_FAM_STM32U5 || CPU_FAM_STM32WB */
#include "cfg_clock_common_lx_u5_wx.h"
#endif
#if defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F1) || \
@ -46,6 +46,8 @@
#elif defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32L5) || \
defined(CPU_FAM_STM32WB) || defined(CPU_FAM_STM32WL)
#include "l4l5wx/cfg_clock_default.h"
#elif defined(CPU_FAM_STM32U5)
#include "u5/cfg_clock_default.h"
#elif defined(CPU_FAM_STM32MP1)
#include "mp1/cfg_clock_default.h"
#else

130
cpu/stm32/include/clk/u5/cfg_clock_default.h Normal file
View File

@ -0,0 +1,130 @@
/*
* Copyright (C) 2021 Inria
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup cpu_stm32
* @{
*
* @file
* @brief Default STM32U5 clock configuration
*
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
*/
#ifndef CLK_U5_CFG_CLOCK_DEFAULT_H
#define CLK_U5_CFG_CLOCK_DEFAULT_H
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name U5 clock system configuration
* @{
*/
#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE < MHZ(4) || CLOCK_HSE > MHZ(48))
#error "HSE clock frequency must be between 4MHz and 48MHz"
#endif
/* The following parameters configure a 80MHz system clock with PLL as input clock */
#ifndef CONFIG_CLOCK_PLL_SRC_MSI
#if IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_HSE) || IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_HSI) || \
IS_ACTIVE(CONFIG_BOARD_HAS_HSE)
#define CONFIG_CLOCK_PLL_SRC_MSI 0
#else
#define CONFIG_CLOCK_PLL_SRC_MSI 1 /* Use MSI as input clock by default */
#endif
#endif /* CONFIG_CLOCK_PLL_SRC_MSI */
#ifndef CONFIG_CLOCK_PLL_SRC_HSE
#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && \
!IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_HSI) && !IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_MSI)
#define CONFIG_CLOCK_PLL_SRC_HSE 1
#else
#define CONFIG_CLOCK_PLL_SRC_HSE 0
#endif
#endif
#ifndef CONFIG_CLOCK_PLL_SRC_HSI
#define CONFIG_CLOCK_PLL_SRC_HSI 0
#endif
#if IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_MSI)
#define CLOCK_PLL_SRC (CONFIG_CLOCK_MSI)
#elif IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_HSE)
#define CLOCK_PLL_SRC (CLOCK_HSE)
#else /* CONFIG_CLOCK_PLL_SRC_ */
#define CLOCK_PLL_SRC (CLOCK_HSI)
#endif
#ifndef CONFIG_CLOCK_PLL_M
#if IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_MSI)
#define CONFIG_CLOCK_PLL_M (6) /* MSI at 48MHz */
#else
#define CONFIG_CLOCK_PLL_M (2) /* HSI/HSE at 16MHz */
#endif
#endif
#ifndef CONFIG_CLOCK_PLL_N
#define CONFIG_CLOCK_PLL_N (40)
#endif
#ifndef CONFIG_CLOCK_PLL_Q
#define CONFIG_CLOCK_PLL_Q (2)
#endif
#ifndef CONFIG_CLOCK_PLL_R
#define CONFIG_CLOCK_PLL_R (2)
#endif
#if IS_ACTIVE(CONFIG_USE_CLOCK_HSI)
#define CLOCK_CORECLOCK (CLOCK_HSI)
#elif IS_ACTIVE(CONFIG_USE_CLOCK_HSE)
#define CLOCK_CORECLOCK (CLOCK_HSE)
#elif IS_ACTIVE(CONFIG_USE_CLOCK_MSI)
#define CLOCK_CORECLOCK (CONFIG_CLOCK_MSI)
#elif IS_ACTIVE(CONFIG_USE_CLOCK_PLL)
/* PLL configuration: make sure your values are legit!
*
* compute by: CORECLOCK = (((PLL_IN / M) * N) / R)
* with:
* PLL_IN: input clock, HSE or MSI
* M: pre-divider, allowed range: [1:8]
* N: multiplier, allowed range: [5:512]
* R: post-divider, allowed range: [2:8]
*
* Also the following constraints need to be met:
* (PLL_IN / M) -> [4MHz:16MHz]
* (PLL_IN / M) * N -> [64MHz:344MHz]
* CORECLOCK -> 64MHz, 80MHZ or 120MHz MAX!
*/
#define CLOCK_CORECLOCK \
((CLOCK_PLL_SRC / CONFIG_CLOCK_PLL_M) * CONFIG_CLOCK_PLL_N) / CONFIG_CLOCK_PLL_R
/* Set max allowed sysclk */
#define CLOCK_CORECLOCK_MAX MHZ(160)
#if CLOCK_CORECLOCK > CLOCK_CORECLOCK_MAX
#error "SYSCLK cannot exceed 160MHz"
#endif /* CLOCK_CORECLOCK > CLOCK_CORECLOCK_MAX */
#endif /* CONFIG_USE_CLOCK_PLL */
#define CLOCK_AHB CLOCK_CORECLOCK /* HCLK, max: 160MHz */
#ifndef CONFIG_CLOCK_APB1_DIV
#define CONFIG_CLOCK_APB1_DIV (4)
#endif
#define CLOCK_APB1 (CLOCK_AHB / CONFIG_CLOCK_APB1_DIV) /* PCLK1, max: 160MHz */
#ifndef CONFIG_CLOCK_APB2_DIV
#define CONFIG_CLOCK_APB2_DIV (2)
#endif
#define CLOCK_APB2 (CLOCK_AHB / CONFIG_CLOCK_APB2_DIV) /* PCLK1, max: 160MHz */
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* CLK_U5_CFG_CLOCK_DEFAULT_H */
/** @} */

13
cpu/stm32/include/cpu_conf.h
View File

@ -64,6 +64,9 @@
#elif CPU_FAM_STM32L5
#include "stm32l5xx.h"
#include "irqs/l5/irqs.h"
#elif CPU_FAM_STM32U5
#include "stm32u5xx.h"
#include "irqs/u5/irqs.h"
#elif CPU_FAM_STM32WB
#include "stm32wbxx.h"
#include "irqs/wb/irqs.h"
@ -100,7 +103,9 @@ extern "C" {
* @brief Flash page configuration
* @{
*/
#if defined(CPU_FAM_STM32WB)
#if defined(CPU_FAM_STM32U5)
#define FLASHPAGE_SIZE (8192U)
#elif defined(CPU_FAM_STM32WB)
#define FLASHPAGE_SIZE (4096U)
#elif defined(CPU_LINE_STM32F091xC) || defined(CPU_LINE_STM32F072xB) \
|| defined(CPU_LINE_STM32F030xC) || defined(CPU_LINE_STM32F103xE) \
@ -196,7 +201,8 @@ extern "C" {
*/
#if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \
defined(CPU_FAM_STM32G4) || defined(CPU_FAM_STM32G0) || \
defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32WL)
defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32U5) || \
defined(CPU_FAM_STM32WL)
#define FLASHPAGE_WRITE_BLOCK_SIZE (8U)
typedef uint64_t stm32_flashpage_block_t;
#elif defined(CPU_FAM_STM32L0) || defined(CPU_FAM_STM32L1) || \
@ -211,7 +217,8 @@ typedef uint16_t stm32_flashpage_block_t;
#if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \
defined(CPU_FAM_STM32G4) || defined(CPU_FAM_STM32G0) || \
defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32WL)
defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32U5) || \
defined(CPU_FAM_STM32WL)
#define FLASHPAGE_WRITE_BLOCK_ALIGNMENT (8U)
#else
/* Writing should be always 4 bytes aligned */

5
cpu/stm32/include/cpu_conf_stm32_common.h
View File

@ -32,7 +32,7 @@ extern "C" {
defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32L4) || \
defined(CPU_FAM_STM32WB) || defined(CPU_FAM_STM32G4) || \
defined(CPU_FAM_STM32G0) || defined(CPU_FAM_STM32L5) || \
defined(CPU_FAM_STM32WL)
defined(CPU_FAM_STM32U5) || defined(CPU_FAM_STM32WL)
/**
* @brief Timing register settings
@ -43,7 +43,8 @@ static const i2c_timing_param_t timing_params[] = {
#if defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F7) || \
defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \
defined(CPU_FAM_STM32G4) || defined(CPU_FAM_STM32G0) || \
defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32WL)
defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32U5) || \
defined(CPU_FAM_STM32WL)
[ I2C_SPEED_NORMAL ] = {
.presc = 0xB,
.scll = 0x13, /* t_SCLL = 5.0us */

42
cpu/stm32/include/periph/u5/periph_cpu.h Normal file
View File

@ -0,0 +1,42 @@
/*
* Copyright (C) 2021 Inria
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup cpu_stm32
* @{
*
* @file
* @brief STM32U5 CPU specific definitions for internal peripheral handling
*
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
*
*/
#ifndef PERIPH_U5_PERIPH_CPU_H
#define PERIPH_U5_PERIPH_CPU_H
#ifdef __cplusplus
extern "C" {
#endif
#ifndef DOXYGEN
/**
* @brief Starting address of the ROM bootloader
* see application note AN2606
*/
#define STM32_BOOTLOADER_ADDR (0x0BF90000)
#endif /* ndef DOXYGEN */
#ifdef __cplusplus
}
#endif
#endif /* PERIPH_U5_PERIPH_CPU_H */
/** @} */

26
cpu/stm32/include/periph_cpu.h
View File

@ -50,6 +50,8 @@
#include "periph/l4/periph_cpu.h"
#elif defined(CPU_FAM_STM32L5)
#include "periph/l5/periph_cpu.h"
#elif defined(CPU_FAM_STM32U5)
#include "periph/u5/periph_cpu.h"
#elif defined(CPU_FAM_STM32WB)
#include "periph/wb/periph_cpu.h"
#elif defined(CPU_FAM_STM32WL)
@ -72,7 +74,8 @@ extern "C" {
defined(CPU_FAM_STM32F7) || defined(CPU_FAM_STM32L4) || \
defined(CPU_FAM_STM32WB) || defined(CPU_FAM_STM32G4) || \
defined(CPU_FAM_STM32G0) || defined(CPU_FAM_STM32L5) || \
defined(CPU_FAM_STM32MP1) || defined(CPU_FAM_STM32WL)
defined(CPU_FAM_STM32U5) || defined(CPU_FAM_STM32MP1) || \
defined(CPU_FAM_STM32WL)
#define CLOCK_LSI (32000U)
#else
#error "error: LSI clock speed not defined for your target CPU"
@ -172,12 +175,13 @@ extern "C" {
typedef enum {
APB1, /**< APB1 bus */
APB2, /**< APB2 bus */
#if defined(CPU_FAM_STM32WL)
#if defined(CPU_FAM_STM32WL) || defined(CPU_FAM_STM32U5)
APB3,
#endif
#if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \
defined(CPU_FAM_STM32G4) || defined(CPU_FAM_STM32G0) || \
defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32WL)
defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32U5) || \
defined(CPU_FAM_STM32WL)
APB12, /**< AHB1 bus, second register */
#endif
#if defined(CPU_FAM_STM32L0) || defined(CPU_FAM_STM32G0)
@ -189,9 +193,13 @@ typedef enum {
#elif defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4) || \
defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32F7) || \
defined(CPU_FAM_STM32WB) || defined(CPU_FAM_STM32G4) || \
defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32WL)
defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32U5) || \
defined(CPU_FAM_STM32WL)
AHB1, /**< AHB1 bus */
AHB2, /**< AHB2 bus */
#if defined(CPU_FAM_STM32U5)
AHB22, /**< AHB2 bus, second register */
#endif
AHB3, /**< AHB3 bus */
#elif defined(CPU_FAM_STM32MP1)
AHB1, /**< AHB1 bus */
@ -671,8 +679,8 @@ typedef struct {
#endif
#if defined(CPU_FAM_STM32L0) || defined(CPU_FAM_STM32L4) || \
defined(CPU_FAM_STM32WB) || defined(CPU_FAM_STM32G4) || \
defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32MP1) || \
defined(CPU_FAM_STM32WL)
defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32U5) || \
defined(CPU_FAM_STM32MP1) || defined(CPU_FAM_STM32WL)
uart_type_t type; /**< hardware module type (USART or LPUART) */
uint32_t clk_src; /**< clock source used for UART */
#endif
@ -725,7 +733,8 @@ typedef enum {
defined(CPU_FAM_STM32F7) || defined(CPU_FAM_STM32L0) || \
defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \
defined(CPU_FAM_STM32G4) || defined(CPU_FAM_STM32G0) || \
defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32WL)
defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32U5) || \
defined(CPU_FAM_STM32WL)
I2C_SPEED_FAST_PLUS, /**< fast plus mode: ~1Mbit/s */
#endif
} i2c_speed_t;
@ -761,7 +770,8 @@ typedef struct {
defined(CPU_FAM_STM32F7) || defined(CPU_FAM_STM32L0) || \
defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \
defined(CPU_FAM_STM32G4) || defined(CPU_FAM_STM32G0) || \
defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32WL)
defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32U5) || \
defined(CPU_FAM_STM32WL)
/**
* @brief Structure for I2C timing register settings
*

BIN
cpu/stm32/include/vendor/patches/u5/0001-stm32u5xx-remove-ErrorStatus.patch vendored Normal file
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4
cpu/stm32/kconfigs/Kconfig.clk
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@ -367,7 +367,7 @@ endif # CPU_FAM_L0 || CPU_FAM_L1 || CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB
choice
bool "APB1 prescaler (division factor of HCLK to produce PCLK1)"
default CLOCK_APB1_DIV_4 if CPU_FAM_F2 || (CPU_FAM_F4 && CLOCK_MAX_180MHZ) || CPU_FAM_F7 || CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB
default CLOCK_APB1_DIV_4 if CPU_FAM_F2 || (CPU_FAM_F4 && CLOCK_MAX_180MHZ) || CPU_FAM_F7 || CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_U5 || CPU_FAM_WB
default CLOCK_APB1_DIV_2 if CPU_FAM_F1 || CPU_FAM_F3 || CPU_FAM_F4
default CLOCK_APB1_DIV_1
@ -399,7 +399,7 @@ config CLOCK_APB1_DIV
choice
bool "APB2 prescaler (division factor of HCLK to produce PCLK2)"
depends on !CPU_FAM_G0 && !CPU_FAM_F0
default CLOCK_APB2_DIV_2 if CPU_FAM_F2 || (CPU_FAM_F4 && CLOCK_MAX_180MHZ) || CPU_FAM_F7 || CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB
default CLOCK_APB2_DIV_2 if CPU_FAM_F2 || (CPU_FAM_F4 && CLOCK_MAX_180MHZ) || CPU_FAM_F7 || CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_U5 || CPU_FAM_WB
default CLOCK_APB2_DIV_1
config CLOCK_APB2_DIV_1

26
cpu/stm32/kconfigs/u5/Kconfig Normal file
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@ -0,0 +1,26 @@
# Copyright (c) 2021 Inria
#
# This file is subject to the terms and conditions of the GNU Lesser
# General Public License v2.1. See the file LICENSE in the top level
# directory for more details.
#
config CPU_FAM_U5
bool
select CPU_STM32
select CPU_CORE_CORTEX_M33
select HAS_CPU_STM32U5
select HAS_PERIPH_FLASHPAGE
select HAS_PERIPH_FLASHPAGE_PAGEWISE
select HAS_PERIPH_HWRNG
select HAS_PERIPH_RTC_MEM
select HAS_PERIPH_WDT
select HAS_BOOTLOADER_STM32
config CPU_FAM
default "u5" if CPU_FAM_U5
config HAS_CPU_STM32U5
bool
help
Indicates that the cpu being used belongs to the 'stm32u5' family.

19
cpu/stm32/kconfigs/u5/Kconfig.lines Normal file
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@ -0,0 +1,19 @@
# Copyright (c) 2021 Inria
#
# This file is subject to the terms and conditions of the GNU Lesser
# General Public License v2.1. See the file LICENSE in the top level
# directory for more details.
#
# This file was auto-generated from ST ProductsList.xlsx sheet using the
# script in cpu/stm32/dist/kconfig/gen_kconfig.py
# See cpu/stm32/dist/kconfig/README.md for details
# CPU lines
config CPU_LINE_STM32U575XX
bool
select CPU_FAM_U5
config CPU_LINE_STM32U585XX
bool
select CPU_FAM_U5

120
cpu/stm32/kconfigs/u5/Kconfig.models Normal file
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@ -0,0 +1,120 @@
# Copyright (c) 2021 Inria
#
# This file is subject to the terms and conditions of the GNU Lesser
# General Public License v2.1. See the file LICENSE in the top level
# directory for more details.
#
# This file was auto-generated from ST ProductsList.xlsx sheet using the
# script in cpu/stm32/dist/kconfig/gen_kconfig.py
# See cpu/stm32/dist/kconfig/README.md for details
# CPU models
config CPU_MODEL_STM32U575AG
bool
select CPU_LINE_STM32U575XX
config CPU_MODEL_STM32U575AI
bool
select CPU_LINE_STM32U575XX
config CPU_MODEL_STM32U575CG
bool
select CPU_LINE_STM32U575XX
config CPU_MODEL_STM32U575CI
bool
select CPU_LINE_STM32U575XX
config CPU_MODEL_STM32U575OG
bool
select CPU_LINE_STM32U575XX
config CPU_MODEL_STM32U575OI
bool
select CPU_LINE_STM32U575XX
config CPU_MODEL_STM32U575QG
bool
select CPU_LINE_STM32U575XX
config CPU_MODEL_STM32U575QI
bool
select CPU_LINE_STM32U575XX
config CPU_MODEL_STM32U575RG
bool
select CPU_LINE_STM32U575XX
config CPU_MODEL_STM32U575RI
bool
select CPU_LINE_STM32U575XX
config CPU_MODEL_STM32U575VG
bool
select CPU_LINE_STM32U575XX
config CPU_MODEL_STM32U575VI
bool
select CPU_LINE_STM32U575XX
config CPU_MODEL_STM32U575ZG
bool
select CPU_LINE_STM32U575XX
config CPU_MODEL_STM32U575ZI
bool
select CPU_LINE_STM32U575XX
config CPU_MODEL_STM32U585AI
bool
select CPU_LINE_STM32U585XX
config CPU_MODEL_STM32U585CI
bool
select CPU_LINE_STM32U585XX
config CPU_MODEL_STM32U585OI
bool
select CPU_LINE_STM32U585XX
config CPU_MODEL_STM32U585QI
bool
select CPU_LINE_STM32U585XX
config CPU_MODEL_STM32U585RI
bool
select CPU_LINE_STM32U585XX
config CPU_MODEL_STM32U585VI
bool
select CPU_LINE_STM32U585XX
config CPU_MODEL_STM32U585ZI
bool
select CPU_LINE_STM32U585XX
# Configure CPU model
config CPU_MODEL
default "stm32u575ag" if CPU_MODEL_STM32U575AG
default "stm32u575ai" if CPU_MODEL_STM32U575AI
default "stm32u575cg" if CPU_MODEL_STM32U575CG
default "stm32u575ci" if CPU_MODEL_STM32U575CI
default "stm32u575og" if CPU_MODEL_STM32U575OG
default "stm32u575oi" if CPU_MODEL_STM32U575OI
default "stm32u575qg" if CPU_MODEL_STM32U575QG
default "stm32u575qi" if CPU_MODEL_STM32U575QI
default "stm32u575rg" if CPU_MODEL_STM32U575RG
default "stm32u575ri" if CPU_MODEL_STM32U575RI
default "stm32u575vg" if CPU_MODEL_STM32U575VG
default "stm32u575vi" if CPU_MODEL_STM32U575VI
default "stm32u575zg" if CPU_MODEL_STM32U575ZG
default "stm32u575zi" if CPU_MODEL_STM32U575ZI
default "stm32u585ai" if CPU_MODEL_STM32U585AI
default "stm32u585ci" if CPU_MODEL_STM32U585CI
default "stm32u585oi" if CPU_MODEL_STM32U585OI
default "stm32u585qi" if CPU_MODEL_STM32U585QI
default "stm32u585ri" if CPU_MODEL_STM32U585RI
default "stm32u585vi" if CPU_MODEL_STM32U585VI
default "stm32u585zi" if CPU_MODEL_STM32U585ZI

2
cpu/stm32/periph/Makefile
View File

@ -2,7 +2,7 @@ MODULE = periph
# Select the specific implementation for `periph_i2c`
ifneq (,$(filter periph_i2c,$(USEMODULE)))
ifneq (,$(filter $(CPU_FAM),f0 f3 f7 g0 g4 l0 l4 l5 wb wl))
ifneq (,$(filter $(CPU_FAM),f0 f3 f7 g0 g4 l0 l4 l5 u5 wb wl))
SRC += i2c_1.c
else ifneq (,$(filter $(CPU_FAM),f1 f2 f4 l1))
SRC += i2c_2.c

11
cpu/stm32/periph/flash_common.c
View File

@ -31,13 +31,19 @@
#define CNTRL_REG (FLASH->PECR)
#define CNTRL_REG_LOCK (FLASH_PECR_PELOCK)
#define KEY_REG (FLASH->PEKEYR)
#elif defined(CPU_FAM_STM32L5)
#elif defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32U5)
#define FLASH_KEY1 ((uint32_t)0x45670123)
#define FLASH_KEY2 ((uint32_t)0xCDEF89AB)
#define CNTRL_REG (FLASH->NSCR)
#if defined(CPU_FAM_STM32U5)
#define CNTRL_REG_LOCK (FLASH_NSCR_LOCK)
#define KEY_REG (FLASH->NSKEYR)
#define FLASH_SR_EOP (FLASH_NSSR_EOP)
#else
#define CNTRL_REG_LOCK (FLASH_NSCR_NSLOCK)
#define KEY_REG (FLASH->NSKEYR)
#define FLASH_SR_EOP (FLASH_NSSR_NSEOP)
#endif
#else
#if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \
defined(CPU_FAM_STM32G4) || defined(CPU_FAM_STM32G0) || \
@ -58,6 +64,9 @@
#if defined(CPU_FAM_STM32L5)
#define FLASH_SR_BSY (FLASH_NSSR_NSBSY)
#define FLASH_SR_REG (FLASH->NSSR)
#elif defined(CPU_FAM_STM32U5)
#define FLASH_SR_BSY (FLASH_NSSR_BSY)
#define FLASH_SR_REG (FLASH->NSSR)
#else
#define FLASH_SR_REG (FLASH->SR)
#endif

20
cpu/stm32/periph/flashpage.c
View File

@ -47,6 +47,15 @@
#define FLASH_CR_PER (FLASH_NSCR_NSPER)
#define FLASH_CR_BKER (FLASH_NSCR_NSBKER)
#define FLASH_CR_PG (FLASH_NSCR_NSPG)
#elif defined(CPU_FAM_STM32U5)
#define CNTRL_REG (FLASH->NSCR)
#define CNTRL_REG_LOCK (FLASH_NSCR_LOCK)
#define FLASH_CR_PNB (FLASH_NSCR_PNB)
#define FLASH_CR_PNB_Pos (FLASH_NSCR_PNB_Pos)
#define FLASH_CR_STRT (FLASH_NSCR_STRT)
#define FLASH_CR_PER (FLASH_NSCR_PER)
#define FLASH_CR_BKER (FLASH_NSCR_BKER)
#define FLASH_CR_PG (FLASH_NSCR_PG)
#elif defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4) || \
defined(CPU_FAM_STM32F7)
#define FLASHPAGE_DIV (4U)
@ -63,7 +72,8 @@ extern void _lock(void);
extern void _unlock(void);
extern void _wait_for_pending_operations(void);
#if defined(CPU_FAM_STM32G4) || defined(CPU_FAM_STM32L5)
#if defined(CPU_FAM_STM32G4) || defined(CPU_FAM_STM32L5) || \
defined(CPU_FAM_STM32U5)
#define MAX_PAGES_PER_BANK (128)
#else /* CPU_FAM_STM32L4 */
#define MAX_PAGES_PER_BANK (256)
@ -111,7 +121,7 @@ static void _erase_page(void *page_addr)
defined(CPU_FAM_STM32G4) || defined(CPU_FAM_STM32G0) || \
defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32F2) || \
defined(CPU_FAM_STM32F4) || defined(CPU_FAM_STM32F7) || \
defined(CPU_FAM_STM32WL)
defined(CPU_FAM_STM32U5) || defined(CPU_FAM_STM32WL)
DEBUG("[flashpage] erase: setting the page address\n");
uint8_t pn;
#if (FLASHPAGE_NUMOF <= MAX_PAGES_PER_BANK) || defined(CPU_FAM_STM32WB) || \
@ -262,7 +272,8 @@ void flashpage_write(void *target_addr, const void *data, size_t len)
defined(CPU_FAM_STM32WB) || defined(CPU_FAM_STM32G4) || \
defined(CPU_FAM_STM32G0) || defined(CPU_FAM_STM32L5) || \
defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4) || \
defined(CPU_FAM_STM32F7) || defined(CPU_FAM_STM32WL)
defined(CPU_FAM_STM32F7) || defined(CPU_FAM_STM32U5) || \
defined(CPU_FAM_STM32WL)
/* set PG bit and program page to flash */
CNTRL_REG |= FLASH_CR_PG;
#endif
@ -282,7 +293,8 @@ void flashpage_write(void *target_addr, const void *data, size_t len)
defined(CPU_FAM_STM32WB) || defined(CPU_FAM_STM32G4) || \
defined(CPU_FAM_STM32G0) || defined(CPU_FAM_STM32L5) || \
defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4) || \
defined(CPU_FAM_STM32F7) || defined(CPU_FAM_STM32WL)
defined(CPU_FAM_STM32F7) || defined(CPU_FAM_STM32U5) || \
defined(CPU_FAM_STM32WL)
CNTRL_REG &= ~(FLASH_CR_PG);
#endif
DEBUG("[flashpage_raw] write: done writing data\n");

30
cpu/stm32/periph/gpio_all.c
View File

@ -46,7 +46,8 @@ static gpio_isr_ctx_t isr_ctx[EXTI_NUMOF];
#if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \
defined(CPU_FAM_STM32G4) || defined(CPU_FAM_STM32G0) || \
defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32WL)
defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32U5) || \
defined(CPU_FAM_STM32WL)
#define EXTI_REG_RTSR (EXTI->RTSR1)
#define EXTI_REG_FTSR (EXTI->FTSR1)
#define EXTI_REG_PR (EXTI->PR1)
@ -101,10 +102,14 @@ static inline void port_init_clock(GPIO_TypeDef *port, gpio_t pin)
periph_clk_en(AHB, (RCC_AHBENR_GPIOAEN << _port_num(pin)));
#elif defined (CPU_FAM_STM32L0) || defined(CPU_FAM_STM32G0)
periph_clk_en(IOP, (RCC_IOPENR_GPIOAEN << _port_num(pin)));
#elif defined (CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \
defined (CPU_FAM_STM32G4) || defined(CPU_FAM_STM32L5) || \
defined (CPU_FAM_STM32WL)
#elif defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \
defined(CPU_FAM_STM32G4) || defined(CPU_FAM_STM32L5) || \
defined(CPU_FAM_STM32U5) || defined (CPU_FAM_STM32WL)
#if defined(CPU_FAM_STM32U5)
periph_clk_en(AHB2, (RCC_AHB2ENR1_GPIOAEN << _port_num(pin)));
#else
periph_clk_en(AHB2, (RCC_AHB2ENR_GPIOAEN << _port_num(pin)));
#endif
#ifdef PWR_CR2_IOSV
if (port == GPIOG) {
/* Port G requires external power supply */
@ -170,10 +175,12 @@ void gpio_init_analog(gpio_t pin)
periph_clk_en(AHB, (RCC_AHBENR_GPIOAEN << _port_num(pin)));
#elif defined (CPU_FAM_STM32L0) || defined(CPU_FAM_STM32G0)
periph_clk_en(IOP, (RCC_IOPENR_GPIOAEN << _port_num(pin)));
#elif defined (CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \
defined (CPU_FAM_STM32G4) || defined(CPU_FAM_STM32L5) || \
#elif defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \
defined(CPU_FAM_STM32G4) || defined(CPU_FAM_STM32L5) || \
defined (CPU_FAM_STM32WL)
periph_clk_en(AHB2, (RCC_AHB2ENR_GPIOAEN << _port_num(pin)));
#elif defined(CPU_FAM_STM32U5)
periph_clk_en(AHB2, (RCC_AHB2ENR1_GPIOAEN << _port_num(pin)));
#elif defined(CPU_FAM_STM32MP1)
periph_clk_en(AHB4, (RCC_MC_AHB4ENSETR_GPIOAEN << _port_num(pin)));
#else
@ -244,6 +251,8 @@ int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank,
periph_clk_en(APB2, RCC_APB2ENR_SYSCFGCOMPEN);
#elif defined(CPU_FAM_STM32G0)
periph_clk_en(APB12, RCC_APBENR2_SYSCFGEN);
#elif defined(CPU_FAM_STM32U5)
periph_clk_en(APB3, RCC_APB3ENR_SYSCFGEN);
#else
periph_clk_en(APB2, RCC_APB2ENR_SYSCFGEN);
#endif
@ -253,7 +262,7 @@ int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank,
gpio_init(pin, mode);
/* enable global pin interrupt */
#if defined(CPU_FAM_STM32L5)
#if defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32U5)
NVIC_EnableIRQ(EXTI0_IRQn + pin_num);
#elif defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32L0) || \
defined(CPU_FAM_STM32G0)
@ -308,7 +317,8 @@ int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank,
EXTI_REG_FTSR &= ~(1 << pin_num);
EXTI_REG_FTSR |= ((flank >> 1) << pin_num);
#if defined(CPU_FAM_STM32G0) || defined(CPU_FAM_STM32L5)
#if defined(CPU_FAM_STM32G0) || defined(CPU_FAM_STM32L5) || \
defined(CPU_FAM_STM32U5)
/* enable specific pin as exti sources */
EXTI->EXTICR[pin_num >> 2] &= ~(0xf << ((pin_num & 0x03) * 8));
EXTI->EXTICR[pin_num >> 2] |= (port_num << ((pin_num & 0x03) * 8));
@ -323,7 +333,7 @@ int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank,
#endif
#if defined(CPU_FAM_STM32G0) || defined(CPU_FAM_STM32L5) || \
defined(CPU_FAM_STM32MP1)
defined(CPU_FAM_STM32U5) || defined(CPU_FAM_STM32MP1)
/* clear any pending requests */
EXTI->RPR1 = (1 << pin_num);
EXTI->FPR1 = (1 << pin_num);
@ -340,7 +350,7 @@ int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank,
void isr_exti(void)
{
#if defined(CPU_FAM_STM32G0) || defined(CPU_FAM_STM32L5) || \
defined(CPU_FAM_STM32MP1)
defined(CPU_FAM_STM32U5) || defined(CPU_FAM_STM32MP1)
/* get all interrupts handled by this ISR */
uint32_t pending_rising_isr = (EXTI->RPR1 & EXTI_MASK);
uint32_t pending_falling_isr = (EXTI->FPR1 & EXTI_MASK);

4
cpu/stm32/periph/hwrng.c
View File

@ -45,6 +45,8 @@ void hwrng_read(void *buf, unsigned int num)
periph_clk_en(AHB, RCC_AHBENR_RNGEN);
#elif defined(CPU_FAM_STM32WB)
periph_clk_en(AHB3, RCC_AHB3ENR_RNGEN);
#elif defined(CPU_FAM_STM32U5)
periph_clk_en(AHB2, RCC_AHB2ENR1_RNGEN);
#else
periph_clk_en(AHB2, RCC_AHB2ENR_RNGEN);
#endif
@ -71,6 +73,8 @@ void hwrng_read(void *buf, unsigned int num)
periph_clk_dis(AHB, RCC_AHBENR_RNGEN);
#elif defined(CPU_FAM_STM32WB)
periph_clk_dis(AHB3, RCC_AHB3ENR_RNGEN);
#elif defined(CPU_FAM_STM32U5)
periph_clk_dis(AHB2, RCC_AHB2ENR1_RNGEN);
#else
periph_clk_dis(AHB2, RCC_AHB2ENR_RNGEN);
#endif

7
cpu/stm32/periph/pm.c
View File

@ -56,6 +56,8 @@
#define PM_STOP_CONFIG (PWR_CR1_LPDS | PWR_CR1_FPDS | PWR_CR1_LPUDS)
#elif defined(CPU_FAM_STM32MP1)
#define PM_STOP_CONFIG (0)
#elif defined(CPU_FAM_STM32U5)
#define PM_STOP_CONFIG (0)
#else
#define PM_STOP_CONFIG (PWR_CR_LPDS | PWR_CR_FPDS)
#endif
@ -79,6 +81,8 @@
#define PM_STANDBY_CONFIG (PWR_CR1_PDDS | PWR_CR1_CSBF)
#elif defined(CPU_FAM_STM32MP1)
#define PM_STANDBY_CONFIG (0)
#elif defined(CPU_FAM_STM32U5)
#define PM_STANDBY_CONFIG (0)
#else
#define PM_STANDBY_CONFIG (PWR_CR_PDDS | PWR_CR_CWUF | PWR_CR_CSBF)
#endif
@ -86,7 +90,8 @@
#if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \
defined(CPU_FAM_STM32G4) || defined(CPU_FAM_STM32G0) || \
defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32WL)
defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32U5) || \
defined(CPU_FAM_STM32WL)
#define PWR_CR_REG PWR->CR1
#define PWR_WUP_REG PWR->CR3
/* Allow overridable SRAM2 retention mode using CFLAGS */

15
cpu/stm32/periph/uart.c
View File

@ -35,7 +35,8 @@
#include "pm_layered.h"
#if defined(CPU_LINE_STM32L4R5xx) || defined(CPU_FAM_STM32G0) || \
defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32WL)
defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32U5) || \
defined(CPU_FAM_STM32WL)
#define ISR_REG ISR
#define ISR_TXE USART_ISR_TXE_TXFNF
#define ISR_RXNE USART_ISR_RXNE_RXFNE
@ -62,7 +63,8 @@
#endif
#if defined(CPU_LINE_STM32L4R5xx) || defined(CPU_FAM_STM32G0) || \
defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32WL)
defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32U5) || \
defined(CPU_FAM_STM32WL)
#define RXENABLE (USART_CR1_RE | USART_CR1_RXNEIE_RXFNEIE)
#else
#define RXENABLE (USART_CR1_RE | USART_CR1_RXNEIE)
@ -98,7 +100,8 @@ static inline USART_TypeDef *dev(uart_t uart)
static inline void uart_init_usart(uart_t uart, uint32_t baudrate);
#if defined(CPU_FAM_STM32L0) || defined(CPU_FAM_STM32L4) || \
defined(CPU_FAM_STM32WB) || defined(CPU_FAM_STM32G4) || \
defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32WL)
defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32U5) || \
defined(CPU_FAM_STM32WL)
#ifdef MODULE_PERIPH_LPUART
static inline void uart_init_lpuart(uart_t uart, uint32_t baudrate);
#endif
@ -192,7 +195,8 @@ int uart_init(uart_t uart, uint32_t baudrate, uart_rx_cb_t rx_cb, void *arg)
#if defined(CPU_FAM_STM32L0) || defined(CPU_FAM_STM32L4) || \
defined(CPU_FAM_STM32WB) || defined(CPU_FAM_STM32G4) || \
defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32WL)
defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32U5) || \
defined(CPU_FAM_STM32WL)
switch (uart_config[uart].type) {
case STM32_USART:
uart_init_usart(uart, baudrate);
@ -322,7 +326,8 @@ static inline void uart_init_usart(uart_t uart, uint32_t baudrate)
#if defined(CPU_FAM_STM32L0) || defined(CPU_FAM_STM32L4) || \
defined(CPU_FAM_STM32WB) || defined(CPU_FAM_STM32G4) || \
defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32WL)
defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32U5) || \
defined(CPU_FAM_STM32WL)
#ifdef CPU_FAM_STM32L5
#define RCC_CCIPR_LPUART1SEL_0 RCC_CCIPR1_LPUART1SEL_0
#define RCC_CCIPR_LPUART1SEL_1 RCC_CCIPR1_LPUART1SEL_1

4
cpu/stm32/stm32_info.mk
View File

@ -8,7 +8,7 @@
# - STM32_PINCOUNT: R (64)
# - STM32_ROMSIZE: G (1024K)
CPU_MODEL_UPPERCASE = $(call uppercase,$(CPU_MODEL))
STM32_INFO := $(shell echo $(CPU_MODEL_UPPERCASE) | sed -E -e 's/^STM32(F|L|W|G|MP)([0-7]|B|L)([A-Z0-9])([0-9])(.)(.)?(_A)?/\1 \2 \2\3\4 \3 \4 \5 \6 \7/')
STM32_INFO := $(shell echo $(CPU_MODEL_UPPERCASE) | sed -E -e 's/^STM32(F|L|W|G|MP|U)([0-7]|B|L)([A-Z0-9])([0-9])(.)(.)?(_A)?/\1 \2 \2\3\4 \3 \4 \5 \6 \7/')
STM32_TYPE = $(word 1, $(STM32_INFO))
STM32_FAMILY = $(word 2, $(STM32_INFO))
STM32_MODEL = $(word 3, $(STM32_INFO))
@ -42,7 +42,7 @@ else ifeq (f7,$(CPU_FAM))
CPU_CORE = cortex-m7
else ifneq (,$(filter $(CPU_FAM),g0 l0))
CPU_CORE = cortex-m0plus
else ifneq (,$(CPU_FAM),l5)
else ifneq (,$(filter $(CPU_FAM),l5 u5))
CPU_CORE = cortex-m33
else
$(error Not supported CPU family: 'stm32$(CPU_FAM)')

6
cpu/stm32/stm32_mem_lengths.mk
View File

@ -266,6 +266,12 @@ else ifeq ($(STM32_TYPE), L)
RAM_LEN = 256K
endif
endif
else ifeq ($(STM32_TYPE), U)
ifeq ($(STM32_FAMILY), 5)
ifneq (, $(filter $(STM32_MODEL2), 7 8))
RAM_LEN = 768K
endif
endif
else ifeq ($(STM32_TYPE), W)
ifeq ($(STM32_FAMILY), B)
ifeq ($(STM32_MODEL), B55)

2
cpu/stm32/stmclk/Makefile
View File

@ -14,6 +14,8 @@ else ifneq (,$(filter $(CPU_FAM),l4 wb wl))
SRC += stmclk_l4wx.c
else ifneq (,$(filter $(CPU_FAM),l5))
SRC += stmclk_l5.c
else ifneq (,$(filter $(CPU_FAM),u5))
SRC += stmclk_u5.c
else ifneq (,$(filter $(CPU_FAM),g0 g4))
SRC += stmclk_gx.c
else ifneq (,$(filter $(CPU_FAM),mp1))

13
cpu/stm32/stmclk/stmclk_common.c
View File

@ -29,6 +29,9 @@
defined(CPU_FAM_STM32WL)
#define REG_PWR_CR CR1
#define BIT_CR_DBP PWR_CR1_DBP
#elif defined(CPU_FAM_STM32U5)
#define REG_PWR_CR DBPR
#define BIT_CR_DBP PWR_DBPR_DBP
#else
#define REG_PWR_CR CR
#define BIT_CR_DBP PWR_CR_DBP
@ -50,7 +53,12 @@
#define RCC_CSR_LSIRDY RCC_CSR_LSI1RDY
#endif
#if defined(CPU_FAM_STM32L5)
#if defined (CPU_FAM_STM32U5)
#define RCC_CSR_LSION RCC_BDCR_LSION
#define RCC_CSR_LSIRDY RCC_BDCR_LSIRDY
#endif
#if defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32U5)
#define RCC_CFGR_SWS_HSI RCC_CFGR_SWS_0
#endif
@ -74,7 +82,8 @@ void stmclk_enable_lfclk(void)
/* Set LSE system clock enable bit. This is required if LSE is to be used by
USARTx, LPUARTx, LPTIMx, TIMx, RNG, system LSCO, MCO, MSI PLL mode */
#if defined(CPU_FAM_STM32WL) || defined (CPU_FAM_STM32L5)
#if defined(CPU_FAM_STM32WL) || defined (CPU_FAM_STM32L5) || \
defined(CPU_FAM_STM32U5)
RCC->BDCR |= RCC_BDCR_LSESYSEN;
while (!(RCC->BDCR & RCC_BDCR_LSESYSRDY)) {}
#endif

334
cpu/stm32/stmclk/stmclk_u5.c Normal file
View File

@ -0,0 +1,334 @@
/*
* Copyright (C) 2021 Inria
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup cpu_stm32
* @{
*
* @file
* @brief Implementation of STM32 clock configuration for U5 family
*
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
* @}
*/
#include "cpu.h"
#include "stmclk.h"
#include "periph_conf.h"
#define RCC_CFGR1_SW_MSI (0x00000000U)
#define RCC_CFGR1_SW_HSI (RCC_CFGR1_SW_0)
#define RCC_CFGR1_SW_HSE (RCC_CFGR1_SW_1)
#define RCC_CFGR1_SW_PLL (RCC_CFGR1_SW_1 | RCC_CFGR1_SW_0)
#define RCC_CFGR1_SWS_MSI (0x00000000U)
#define RCC_CFGR1_SWS_HSI (RCC_CFGR1_SWS_0)
#define RCC_CFGR1_SWS_HSE (RCC_CFGR1_SWS_1)
#define RCC_CFGR1_SWS_PLL (RCC_CFGR1_SWS_1 | RCC_CFGR1_SWS_0)
/* PLL configuration */
/* figure out which input to use */
#if IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_MSI)
#define PLL_SRC (RCC_PLL1CFGR_PLL1SRC_0)
#elif IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_HSE) && IS_ACTIVE(CONFIG_BOARD_HAS_HSE)
#define PLL_SRC (RCC_PLL1CFGR_PLL1SRC_1 | RCC_PLL1CFGR_PLL1SRC_0)
#elif IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_HSI)
#define PLL_SRC (RCC_PLL1CFGR_PLL1SRC_1)
#else
#define PLL_SRC 0
#endif
/* check configuration and get the corresponding bitfields */
#if (CONFIG_CLOCK_PLL_M < 1 || CONFIG_CLOCK_PLL_M > 16)
#error "PLL configuration: PLL M value is out of range"
#endif
#define PLL_M ((CONFIG_CLOCK_PLL_M - 1) << RCC_PLL1CFGR_PLL1M_Pos)
#if (CONFIG_CLOCK_PLL_N < 4 || CONFIG_CLOCK_PLL_N > 512)
#error "PLL configuration: PLL N value is out of range"
#endif
#define PLL_N ((CONFIG_CLOCK_PLL_N - 1) << RCC_PLL1DIVR_PLL1N_Pos)
#if (CONFIG_CLOCK_PLL_R < 1 || CONFIG_CLOCK_PLL_R > 128)
#error "PLL configuration: PLL R value is out of range"
#endif
#define PLL_R ((CONFIG_CLOCK_PLL_R - 1) << RCC_PLL1DIVR_PLL1R_Pos)
#if (CONFIG_CLOCK_PLL_Q < 1 || CONFIG_CLOCK_PLL_Q > 128)
#error "PLL configuration: PLL Q value is out of range"
#endif
#define PLL_Q ((CONFIG_CLOCK_PLL_Q - 1) << RCC_PLL1DIVR_PLL1Q_Pos)
/* Define MSI range bitfields */
#if CONFIG_CLOCK_MSI == KHZ(100)
#define CLOCK_MSIRANGE (RCC_ICSCR1_MSISRANGE_3 | RCC_ICSCR1_MSISRANGE_2 | RCC_ICSCR1_MSISRANGE_1 | RCC_ICSCR1_MSISRANGE_0)
#elif CONFIG_CLOCK_MSI == KHZ(133)
#define CLOCK_MSIRANGE (RCC_ICSCR1_MSISRANGE_3 | RCC_ICSCR1_MSISRANGE_2 | RCC_ICSCR1_MSISRANGE_1)
#elif CONFIG_CLOCK_MSI == KHZ(200)
#define CLOCK_MSIRANGE (RCC_ICSCR1_MSISRANGE_3 | RCC_ICSCR1_MSISRANGE_2 | RCC_ICSCR1_MSISRANGE_0)
#elif CONFIG_CLOCK_MSI == KHZ(400)
#define CLOCK_MSIRANGE (RCC_ICSCR1_MSISRANGE_3 | RCC_ICSCR1_MSISRANGE_2)
#elif CONFIG_CLOCK_MSI == KHZ(768)
#define CLOCK_MSIRANGE (RCC_ICSCR1_MSISRANGE_3 | RCC_ICSCR1_MSISRANGE_1 | RCC_ICSCR1_MSISRANGE_0)
#elif CONFIG_CLOCK_MSI == MHZ(1)
#define CLOCK_MSIRANGE (RCC_ICSCR1_MSISRANGE_2 | RCC_ICSCR1_MSISRANGE_1 | RCC_ICSCR1_MSISRANGE_0)
#elif CONFIG_CLOCK_MSI == KHZ(1024)
#define CLOCK_MSIRANGE (RCC_ICSCR1_MSISRANGE_3 | RCC_ICSCR1_MSISRANGE_1)
#elif CONFIG_CLOCK_MSI == KHZ(1330)
#define CLOCK_MSIRANGE (RCC_ICSCR1_MSISRANGE_2 | RCC_ICSCR1_MSISRANGE_1)
#elif CONFIG_CLOCK_MSI == KHZ(1536)
#define CLOCK_MSIRANGE (RCC_ICSCR1_MSISRANGE_3 | RCC_ICSCR1_MSISRANGE_0)
#elif CONFIG_CLOCK_MSI == MHZ(2)
#define CLOCK_MSIRANGE (RCC_ICSCR1_MSISRANGE_2 | RCC_ICSCR1_MSISRANGE_0)
#elif CONFIG_CLOCK_MSI == KHZ(3072)
#define CLOCK_MSIRANGE (RCC_ICSCR1_MSISRANGE_3)
#elif CONFIG_CLOCK_MSI == MHZ(4)
#define CLOCK_MSIRANGE (RCC_ICSCR1_MSISRANGE_2)
#elif CONFIG_CLOCK_MSI == MHZ(12)
#define CLOCK_MSIRANGE (RCC_ICSCR1_MSISRANGE_1 | RCC_ICSCR1_MSISRANGE_0)
#elif CONFIG_CLOCK_MSI == MHZ(16)
#define CLOCK_MSIRANGE (RCC_ICSCR1_MSISRANGE_1)
#elif CONFIG_CLOCK_MSI == MHZ(24)
#define CLOCK_MSIRANGE (RCC_ICSCR1_MSISRANGE_0)
#elif CONFIG_CLOCK_MSI == MHZ(48)
#define CLOCK_MSIRANGE (0)
#else
#error "Invalid MSI clock"
#endif
/* Configure 48MHz clock source */
#define CLOCK_PLLQ ((CLOCK_PLL_SRC / CONFIG_CLOCK_PLL_M) * CONFIG_CLOCK_PLL_N) / CONFIG_CLOCK_PLL_Q
#if CLOCK_PLLQ == MHZ(48)
#define CLOCK48MHZ_USE_PLLQ 1
#elif CONFIG_CLOCK_MSI == MHZ(48)
#define CLOCK48MHZ_USE_MSI 1
#else
#define CLOCK48MHZ_USE_PLLQ 0
#define CLOCK48MHZ_USE_MSI 0
#endif
#if IS_ACTIVE(CLOCK48MHZ_USE_PLLQ)
#define CLOCK48MHZ_SELECT (RCC_CCIPR1_CLK48MSEL_1)
#elif IS_ACTIVE(CLOCK48MHZ_USE_MSI)
#define CLOCK48MHZ_SELECT (RCC_CCIPR1_CLK48MSEL_1 | RCC_CCIPR1_CLK48MSEL_0)
#else
#define CLOCK48MHZ_SELECT (0)
#endif
/* Configure the AHB and APB buses prescalers */
#define CLOCK_AHB_DIV (0)
#if CONFIG_CLOCK_APB1_DIV == 1
#define CLOCK_APB1_DIV (0)
#elif CONFIG_CLOCK_APB1_DIV == 2
#define CLOCK_APB1_DIV (RCC_CFGR2_PPRE1_2)
#elif CONFIG_CLOCK_APB1_DIV == 4
#define CLOCK_APB1_DIV (RCC_CFGR2_PPRE1_2 | RCC_CFGR2_PPRE1_0)
#elif CONFIG_CLOCK_APB1_DIV == 8
#define CLOCK_APB1_DIV (RCC_CFGR2_PPRE1_2 | RCC_CFGR2_PPRE1_1)
#elif CONFIG_CLOCK_APB1_DIV == 16
#define CLOCK_APB1_DIV (RCC_CFGR2_PPRE1_2 | RCC_CFGR2_PPRE1_1 | RCC_CFGR2_PPRE1_0)
#endif
#if CONFIG_CLOCK_APB2_DIV == 1
#define CLOCK_APB2_DIV (0)
#elif CONFIG_CLOCK_APB2_DIV == 2
#define CLOCK_APB2_DIV (RCC_CFGR2_PPRE2_2)
#elif CONFIG_CLOCK_APB2_DIV == 4
#define CLOCK_APB2_DIV (RCC_CFGR2_PPRE2_2 | RCC_CFGR2_PPRE2_0)
#elif CONFIG_CLOCK_APB2_DIV == 8
#define CLOCK_APB2_DIV (RCC_CFGR2_PPRE2_2 | RCC_CFGR2_PPRE2_1)
#elif CONFIG_CLOCK_APB2_DIV == 16
#define CLOCK_APB2_DIV (RCC_CFGR2_PPRE2_2 | RCC_CFGR2_PPRE2_1 | RCC_CFGR2_PPRE2_0)
#endif
/* Only periph_hwrng requires 48MHz for the moment */
#if IS_USED(MODULE_PERIPH_HWRNG)
#if !IS_ACTIVE(CLOCK48MHZ_USE_PLLQ) && !IS_ACTIVE(CLOCK48MHZ_USE_MSI)
#error "No 48MHz clock source available, HWRNG cannot work"
#endif
#define CLOCK_ENABLE_48MHZ 1
#else
#define CLOCK_ENABLE_48MHZ 0
#endif
/* Check if PLL is required
- When used as system clock
- When PLLQ is used as 48MHz clock source
*/
#if IS_ACTIVE(CONFIG_USE_CLOCK_PLL) || \
(IS_ACTIVE(CLOCK_ENABLE_48MHZ) && IS_ACTIVE(CLOCK48MHZ_USE_PLLQ))
#define CLOCK_ENABLE_PLL 1
#else
#define CLOCK_ENABLE_PLL 0
#endif
/* Check if HSE is required:
- When used as system clock
- When used as PLL input clock
*/
#if IS_ACTIVE(CONFIG_USE_CLOCK_HSE) || \
(IS_ACTIVE(CLOCK_ENABLE_PLL) && IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_HSE))
#define CLOCK_ENABLE_HSE 1
#else
#define CLOCK_ENABLE_HSE 0
#endif
/* HSE cannot be enabled if not provided by the board */
#if IS_ACTIVE(CLOCK_ENABLE_HSE) && !IS_ACTIVE(CONFIG_BOARD_HAS_HSE)
#error "HSE is required by the clock configuration but is not provided by the board."
#endif
/* Check if HSI is required:
- When used as system clock
- When used as PLL input clock
*/
#if IS_ACTIVE(CONFIG_USE_CLOCK_HSI) || \
(IS_ACTIVE(CLOCK_ENABLE_PLL) && IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_HSI))
#define CLOCK_ENABLE_HSI 1
#else
#define CLOCK_ENABLE_HSI 0
#endif
/* Check if MSI is required
- When used as system clock
- When used as PLL input clock
*/
#if IS_ACTIVE(CONFIG_USE_CLOCK_MSI) || \
(IS_ACTIVE(CLOCK_ENABLE_PLL) && IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_MSI)) || \
(IS_ACTIVE(CLOCK_ENABLE_48MHZ) && IS_ACTIVE(CLOCK48MHZ_USE_MSI))
#define CLOCK_ENABLE_MSI 1
#else
#define CLOCK_ENABLE_MSI 0
#endif
/* Deduct the needed flash wait states from the core clock frequency */
#if CLOCK_AHB <= MHZ(32)
#define FLASH_WAITSTATES FLASH_ACR_LATENCY_0WS
#elif CLOCK_AHB <= MHZ(64)
#define FLASH_WAITSTATES FLASH_ACR_LATENCY_1WS
#elif CLOCK_AHB <= MHZ(96)
#define FLASH_WAITSTATES FLASH_ACR_LATENCY_2WS
#elif CLOCK_AHB <= MHZ(128)
#define FLASH_WAITSTATES FLASH_ACR_LATENCY_3WS
#elif CLOCK_AHB <= MHZ(160)
#define FLASH_WAITSTATES FLASH_ACR_LATENCY_4WS
#endif
void stmclk_init_sysclk(void)
{
/* disable any interrupts. Global interrupts could be enabled if this is
* called from some kind of bootloader... */
unsigned is = irq_disable();
RCC->CIER = 0;
/* select 1-way cache */
ICACHE->CR &= ~ICACHE_CR_WAYSEL;
ICACHE->CR |= ICACHE_CR_EN;
/* enable HSI clock for the duration of initialization */
stmclk_enable_hsi();
/* use HSI as system clock while we do any further configuration and
* configure the AHB and APB clock dividers as configured by the board */
RCC->CFGR1 = RCC_CFGR1_SW_HSI;
while ((RCC->CFGR1 & RCC_CFGR1_SWS) != RCC_CFGR1_SWS_HSI) {}
RCC->CFGR2 = (CLOCK_AHB_DIV | CLOCK_APB1_DIV | CLOCK_APB2_DIV);
/* Select the Voltage Range 1 */
PWR->VOSR = (PWR_VOSR_VOS_1 | PWR_VOSR_VOS_0);
/* Wait Until the Voltage Regulator is ready */
while (!(PWR->VOSR & PWR_VOSR_VOSRDY)) {}
/* Switch to SMPS regulator instead of LDO */
PWR->CR3 |= PWR_CR3_REGSEL;
while (!(PWR->SVMSR & PWR_SVMSR_REGS)) {}
/* configure flash wait states */
FLASH->ACR = FLASH_WAITSTATES;
/* disable all active clocks except HSI -> resets the clk configuration */
RCC->CR = RCC_CR_HSION;
/* Enable the HSE clock only when it's used */
if (IS_ACTIVE(CLOCK_ENABLE_HSE)) {
RCC->CR |= (RCC_CR_HSEON);
while (!(RCC->CR & RCC_CR_HSERDY)) {}
}
/* Enable the MSI clock only when it's used */
if (IS_ACTIVE(CLOCK_ENABLE_MSI)) {
RCC->ICSCR1 = RCC_ICSCR1_MSIRGSEL;
RCC->ICSCR1 |= CLOCK_MSIRANGE;
RCC->CR |= (RCC_CR_MSISON | RCC_CR_MSIPLLSEL | RCC_CR_MSIPLLFAST);
while (!(RCC->CR & RCC_CR_MSISRDY)) {}
}
/* Enable the PLL clock only when it's used */
if (IS_ACTIVE(CLOCK_ENABLE_PLL)) {
if (IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_MSI) && IS_ACTIVE(CONFIG_BOARD_HAS_LSE)) {
/* configure the low speed clock domain */
stmclk_enable_lfclk();
/* now we can enable the MSI PLL mode to enhance accuracy of the MSI */
RCC->CR |= RCC_CR_MSIPLLEN;
while (!(RCC->CR & RCC_CR_MSISRDY)) {}
}
/* configure and start the PLL */
RCC->PLL1CFGR = (PLL_SRC | PLL_M | RCC_PLL1CFGR_PLL1RGE_1 | RCC_PLL1CFGR_PLL1RGE_0);
if (IS_ACTIVE(CONFIG_USE_CLOCK_PLL)) {
/* Enable PLLCLK if PLL is used as system clock */
RCC->PLL1CFGR |= RCC_PLL1CFGR_PLL1REN;
}
if (IS_ACTIVE(CLOCK48MHZ_USE_PLLQ)) {
/* Enable PLLQ if PLL is used as 48MHz source clock */
RCC->PLL1CFGR |= RCC_PLL1CFGR_PLL1QEN;
}
RCC->PLL1DIVR = (PLL_N | PLL_R | PLL_Q);
RCC->PLL1FRACR = 0;
RCC->CR |= RCC_CR_PLL1ON;
while (!(RCC->CR & RCC_CR_PLL1RDY)) {}
}
/* Configure SYSCLK */
if (!IS_ACTIVE(CONFIG_USE_CLOCK_HSI)) {
RCC->CFGR1 &= ~RCC_CFGR1_SW;
}
if (IS_ACTIVE(CONFIG_USE_CLOCK_HSE)) {
/* Select HSE as system clock */
RCC->CFGR1 |= RCC_CFGR1_SW_HSE;
while ((RCC->CFGR1 & RCC_CFGR1_SWS) != RCC_CFGR1_SWS_HSE) {}
}
else if (IS_ACTIVE(CONFIG_USE_CLOCK_MSI)) {
/* Select MSI as system clock */
RCC->CFGR1 |= RCC_CFGR1_SW_MSI;
while ((RCC->CFGR1 & RCC_CFGR1_SWS) != RCC_CFGR1_SWS_MSI) {}
}
else if (IS_ACTIVE(CONFIG_USE_CLOCK_PLL)) {
/* Select main PLL as system clock */
RCC->CFGR1 |= RCC_CFGR1_SW_PLL;
while ((RCC->CFGR1 & RCC_CFGR1_SWS) != RCC_CFGR1_SWS_PLL) {}
}
if (!IS_ACTIVE(CLOCK_ENABLE_HSI)) {
/* Disable HSI only if not used */
stmclk_disable_hsi();
}
if (IS_ACTIVE(CLOCK_ENABLE_48MHZ)) {
/* configure the clock used for the 48MHz clock tree (USB, RNG) */
RCC->CCIPR1 = CLOCK48MHZ_SELECT;
}
irq_restore(is);
}