RIOT-OS/RIOT
RIOT-OS/RIOT
1
0
Fork 0
mirror of https://github.com/RIOT-OS/RIOT.git synced 2024-12-29 04:50:03 +01:00
Code Releases Activity
46,823 Commits 40 Branches 189 Tags 262 MiB
af89824cfd
Commit Graph

294 Commits

Author SHA1 Message Date
Benjamin Valentin
bfb3d52a63 cpu/sam0_common: implement periph/dac 
The sam0 MCUs all have a DAC peripheral.
The DAC has a resulution of 10 or 12 bits and can have one or two
output channels.

The output pins are always hard-wired to PA2 for DAC0 and PA5 for DAC1
if it exists.

On the same54-xpro I would only get a max value of ~1V when using the
internal reference, so I configured it to use an external voltage reference.

The external reference pin is hard-wired to PA3, so you'll have to connect
that to 3.3V to get results.
 2020-05-02 18:31:55 +02:00
Benjamin Valentin
da89f6ac5f cpu/samd21: don't hard-code number of channels 
Each TCC can have 8 PWM channels, so don't hard-code
3 channels/TCC.
 2020-04-26 22:26:01 +02:00
Benjamin Valentin
4d90a9c6b5 cpu/samd21: pwm: fix GCLK_ID & APBCMASK calculation 
GCLK_ID and APBCMASK entries are not always uniform.
The previous hack would already break for TCC3.

Just explosively write down the cases, there are only 5 at most.
 2020-04-08 15:24:05 +02:00
Benjamin Valentin
01c573c612 cpu/samd21: pwm: allow to use channels > 3 
Channels 4…7 are on the CCB register.
 2020-04-03 01:02:38 +02:00
Benjamin Valentin
5d123cbb22 cpu/sam0_common: distribute PM_NUM_MODES among siblings 
Also adapt the defines to the documentation

 - CPUs define up to 4 power modes (from zero, the lowest power mode,
   to PM_NUM_MODES-1, the highest)
 - >> there is an implicit extra idle mode (which has the number PM_NUM_MODES) <<

Previously on saml21 this would always generate pm_set(3) which is an illegal state.
Now pm_layered will correctly generate pm_set(2) for IDLE modes.

Idle power consumption dropped from 750µA to 368µA and wake-up from standby is also
possible. (Before it would just enter STANDBY again as the mode register was never
written with the illegal value.)
 2020-04-01 18:10:23 +02:00
Dylan Laduranty
6bba4188fc
Merge pull request #13764 from benpicco/cpu/saml11/use_buck_converter 
cpu/saml1x: select buck voltage regulator when possible
 2020-04-01 14:47:47 +02:00
Benjamin Valentin
895eb943d8 cpu/sam0_common: add cpu_pm_cb_enter()/leave() 
This allows to implement needed work-arounds surrounding sleep on
a per-MCU basis.
 2020-03-31 17:18:58 +02:00
Leandro Lanzieri
c43543c21a
cpu/samd21: Add Kconfig file 2020-03-31 13:39:40 +02:00
Benjamin Valentin
51fa5afef7 cpu/samd21: default 1kHz clock to same source as 32kHz clock 
The split between GEN2_ULP32K and GEN3_ULP32K was introduced to fix
a failure in tests/periph_wdt when the external oscillator was used.

By not running the external oscillator on demand, the failure can no
longer be observed, so default GEN3_ULP32K to GEN2_ULP32K.
 2020-02-27 16:01:44 +01:00
Benjamin Valentin
2d7bc9e467 cpu/samd21: don't run XOSC32K on demand 
This significantly reduces start-up time.
The XOSC32K is only configured when needed anyway.
 2020-02-27 15:59:10 +01:00
benpicco
0edfd13df0
Merge pull request #13310 from benpicco/sam0-exti-common 
cpu/sam0_common: use generic exti_config
 2020-02-26 08:40:49 +01:00
Juergen Fitschen
1265efc785 cpu/sam0*: Wrap cortexm_sleep call 2020-02-24 11:48:13 +01:00
Benjamin Valentin
fd9a247200 cpu/sam0_common: use generic exti_config 
Creating an `exti_config` array for a new MCU manually is tedious and error prone.
Luckiely all information is already availiable in the vendor files.

Credit for this discovery & method goes to @Sizurka

The file was generated with

```C

int main(void) {
        puts("static const int8_t exti_config[PORT_GROUPS][32] = {");

        for (unsigned port = 1; port < 5; ++port) {
                printf("#if PORT_GROUPS >= %d\n{\n", port);
                for (unsigned pin = 0; pin < 32; ++pin) {
                        printf("#ifdef PIN_P%c%02uA_EIC_EXTINT_NUM\n", '@' + port, pin);
                        printf("    PIN_P%c%02uA_EIC_EXTINT_NUM,\n", '@' + port, pin);
                        printf("#else\n    -1,\n#endif\n");
                }
                printf("},\n#endif\n\n");
        }

        puts("};");

        return 0;
}
```

No changes in generated code are expected, but this makes adding new members
of the sam0 CPU families much easier.
 2020-02-20 11:23:51 +01:00
Alexandre Abadie
d7c0102115
cpu/cortexm: move CPU_ARCH/FAM to Makefile.features 2020-02-17 16:02:48 +01:00
Kaspar Schleiser
1a75f26133 cpu/*: update to PM_BLOCKER_INITIAL as single value 2020-02-14 12:06:05 +01:00
Dylan Laduranty
03b6658721
Merge pull request #13313 from benpicco/samd21-asf 
cpu/sam0_common: update samd21 vendor files to version 1.3.395
 2020-02-11 21:50:56 +01:00
benpicco
33291ad675
Merge pull request #13306 from fjmolinas/pr_samr21_use_xosc 
boards/sam[r/d]21-xpro: prefer XOSC32K for RTC/RTT (GCLK2)
 2020-02-11 15:18:36 +01:00
Benjamin Valentin
e03780c8ca cpu/sam0_common: update samd21 vendor files to version 1.3.395 
This release adds EXTINT defines compatible with later versions of
the sam0 series of MCUs.
 2020-02-08 03:28:14 +01:00
Francisco Molina
238d56e474
cpu/samd21/cpu: reset GCLK before configuring them 2020-02-07 16:11:42 +01:00
Francisco Molina
2e542a2488
cpu/samd21: cleanup XOSC32K initialization 2020-02-07 15:54:56 +01:00
Francisco Molina
9ab22b6926
cpu/samd21: add GEN3_ULP32K selector 2020-02-07 15:53:32 +01:00
Benjamin Valentin
bd1953dd80 cpu/sam0_common: use vendor files to dispatch MCU headers 
Instead of manually re-creating the files from ASF, just use
the vendor provided dispatch headers and ease the maintainance
burden.
 2020-02-06 19:52:05 +01:00
Benjamin Valentin
38b6ee56f3 cpu/sam0: use defines for GCLK IDs 
Give the clocks explicit names to better identify their meaning.
 2020-02-04 21:16:54 +01:00
Benjamin Valentin
df33ffd0d3 cpu/samd21: only configure one 32kHz GCLK 
Use the same 32 kHz GCLK to feed the PLL and the RTT, etc.
 2020-02-04 21:16:54 +01:00
Benjamin Valentin
1496149bba cpu/sam0: don't hard-code peripheral clocks 
Instead of hard-coding the peripheral clocks to CLOCK_CORECLOCK
introduce helper functions to return the frequency of the individual
GCLKs and use those for baud-rate calculations.

This requires the GCLK to be part of the peripheral's config struct.
While this is already the case for most peripherals, this also adds
it for those where it wasn't used before.

As it defaults to 0 (CLOCK_CORECLOCK) no change is to be expected.
 2020-02-04 21:06:21 +01:00
Alexandre Abadie
925445d0ff
cpu/sam0: factorize dependencies in Makefile.dep 2020-01-28 13:18:39 +01:00
Benjamin Valentin
0d977b3b3c cpu/sam0_common/periph/uart: implement buffered write 
Implement interrupt based uart_write() using a tsrb for the TX buffer.

To enable it, add

    USEMODULE += periph_uart_nonblocking

to your Makefile.
 2019-11-27 19:01:00 +01:00
Francois Berder
4a31f94cfc many typo fixes 
Signed-off-by: Francois Berder <18538310+francois-berder@users.noreply.github.com>
 2019-11-23 22:39:07 +01:00
Yegor Yefremov
5b0252b150 doxygen/ADC: don't include overridden typedefs 
Add missing #ifndefs to overridden ADC resolution typedefs.

Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
 2019-11-15 10:35:32 +01:00
Benjamin Valentin
d92c079a90 cpu/samd21: configure GCLK4 with 1024 Hz 
Both WDT and RTC expect a 1 kHz clock.
Source it from the same generator as the 32 kHz GCLK2.
 2019-11-12 11:29:17 +01:00
Francisco Molina
347a0fc804 cpu/ boards/: remove exports for CPU_FAM 2019-10-18 08:55:33 +02:00
Francisco Molina
5e9b92a326 cpu: remove CPU_ARCH exports 2019-10-18 08:55:33 +02:00
Marian Buschsieweke
df27dbef7a
cpu: Moved stdio_init() into cpu_init() 
- Removed stdio_init() from newlib's _init(), as this is too late in the boot
  process to allow DEBUG()ing during periph_init()
- Added stdio_init() to the various cpu_init() routines of the ARM CPUs just
  before periph_init()
 2019-09-06 16:54:23 +02:00
Benjamin Valentin
b8c4ab5b69 cpu: make use of ARRAY_SIZE macro 2019-08-06 19:43:54 +02:00
Benjamin Valentin
d6b8df1ff7 cpu/samd21: allow to use XOSC32K for GCLK2 
GCLK2 is needed by RTC/RTT, so make it possible to configure it with
XOSC32K as source.
 2019-06-18 13:20:04 +02:00
Benjamin Valentin
849dd4cdce sam0_common: make Timer implementation common across all sam0 MCUs 
The currently supported SAM0 MCUs (samd21, saml21, saml1x) share the same
Timer peripheral, yet each of them carries it's own copy of the Timer
driver.

This introduces a new timer driver that is common for all sam0 MCUs and
uses structs for configuration instead of defines.
 2019-05-21 11:47:59 +02:00
Benjamin Valentin
077056b949 sam0_common: make RTT implementation common across all sam0 MCUs 
The currently supported SAM0 MCUs (samd21, saml21, saml1x) share the
same RTC peripheral, yet each of them carries it's own copy of the RTT
driver.

Unify the drivers and move them to sam0_common.
 2019-05-09 20:54:00 +02:00
Benjamin Valentin
9aa8c619c1 sam0_common: make RTC implementation common across all sam0 MCUs 
The currently supported SAM0 MCUs (samd21, saml21, saml1x) share the
same RTC peripheral, yet each of them carries it's own copy of the RTC
driver.

Unify the drivers and move them to sam0_common.
 2019-04-15 22:25:47 +02:00
Koen Zandberg
ca5b5a6d0f
samd21: Expose numerical PM states 2019-03-18 13:44:26 +01:00
Benjamin Valentin
5b0e427a52 samd21: enable idle modes 
tested on samr21-xpro, UART and 802.15.4 still work as before, but
current draw drops from 12mA to 8mA.
 2019-02-27 11:20:49 +01:00
PeterKietzmann
347b972538 cpu/samd21: add SRAM based random seed 2018-07-04 17:55:20 +02:00
Joakim Nohlgård
dfa342b5f8 cpu/samd21: Avoid clearing interrupt bits unintentionally 
The INTENSET, INTENCLR, INTFLAG registers are write-1-to-confirm
registers, so writing zeroes will not affect anything, on the other
hand, a compiler generated read-modify-write cycle may unintentionally
affect more bits than the one being set. Avoid by using direct
assignment instead of or-assignment (|=) or bitfield writes (.bit.xxx=).
 2018-03-27 07:54:18 +02:00
Dan Evans
0f011d53de samd21/cpu DFLL lock loop error 2018-01-26 09:59:59 -07:00
smlng
e381317fbf make: fix sign-compare errors 
cpu, nrf5x_common: fix sign-compare in periph/flashpage
    drivers, periph_common: fix sign-compare in flashpage
    cpu, sam0_common: fix sign-compare error in periph/gpio
    cpu, cc2538: fix sign-compare in periph/timer
    cpu, sam3: fix sign-compare in periph/gpio
    cpu, stm32_common: fix sign-compare in periph/pwm
    cpu, stm32_common: fix sign-compare in periph/timer
    cpu, stm32_common: fix sign-compare in periph/flashpage
    cpu, nrf5x_common: fix sign-compare in radio/nrfmin
    cpu, samd21: fix sign-compare in periph/pwm
    cpu, ezr32wg: fix sign-compare in periph/gpio
    cpu, ezr32wg: fix sign-compare in periph/timer
    drivers, ethos: fix sign-compare
    sys, net: fix sign-compare
    cpu, atmega_common: fix sign-compare error
    cpu, msp430fxyz: fix sign-compare in periph/gpio
    boards, msb-430-common: fix sign-compare in board_init
    driver, cc2420: fix sign-compared
    sys/net: fix sign-compare in gnrc_tftp
    driver, pcd8544: fix sign-compare
    driver, pn532: fix sign-compare
    driver, sdcard_spi: fix sign-compare
    tests: fix sign_compare
    sys/net, lwmac: fix sign_compare
    pkg, lwip: fix sign-compare
    boards, waspmote: make CORECLOCK unsigned long to fix sign_compare error
    tests, sock_ip: fix sign compare
    tests, msg_avail: fix sign compare
    tests, sock_udp: fix sign compare
    boards: fix sign-compare for calliope and microbit matrix
 2017-11-28 11:55:48 +01:00
Hauke Petersen
89db77710f
Merge pull request #7963 from dylad/opt_sam0_gpio 
cpu/sam0: share GPIO configuration
 2017-11-13 14:58:56 +01:00
Joakim Nohlgård
e3d5a70e0c cpu/cortexm: Remove leftover _estack declarations 
These are leftovers from before the Cortex-M common ISR vectors were
split into vectors_cortexm.c
 2017-11-10 15:38:14 +01:00
dylad
a06ace7904 cpu/sam0: share GPIO configuration 
Signed-off-by: dylad <dylan.laduranty@mesotic.com>
 2017-11-10 10:43:08 +01:00
Hauke Petersen
b3962f8d2c cpu/sam0: removed guards form periph drivers 2017-11-09 12:57:02 +01:00
Kaspar Schleiser
3ec8126c84 cpu: cortexm: provide periph_pm for all cortexm 2017-11-06 12:01:19 +01:00
Kaspar Schleiser
a20745b6c5 cpu: make use of Makefile.periph 2017-11-06 12:01:19 +01:00
Kaspar Schleiser
93246dbedd cpu: sam0: reorganize Makefile.features 2017-11-02 12:59:45 +01:00
Alexandre Abadie
6be74db22b cpu/samd21: skip pwm if not defined in board config 2017-10-12 12:07:41 +02:00
Hauke Petersen
b75672628a Merge pull request #7632 from smlng/cpu/sam0_common/vendor_header 
cpu, sam0_common: update vendor headers
 2017-10-09 10:45:36 +02:00
Dan Evans
a59714b02c samd21:add prescaler option for rtt.c 2017-10-02 20:35:07 -07:00
Hauke Petersen
938ba0b3c5 Merge pull request #7535 from haukepetersen/opt_cortexm_vectordefs 
cpu: use shared Cortex-M base vector table
 2017-10-01 21:46:17 +02:00
dylad
1e5262506d cpu/sam0: merge GPIO driver 2017-10-01 14:48:12 +02:00
smlng
700793e1ce cpu, samd21: adapt periph drivers for rtt and timer to updated vendor headers 2017-09-20 17:12:10 +02:00
Hauke Petersen
3ede8e9d95 cpu: force size of CPU specific vector table 2017-09-04 15:13:43 +02:00
Hauke Petersen
1a20ef8223 cpu: unified cortex-m base interrupt vector 2017-09-04 15:13:32 +02:00
dylad
89c885ea40 sam0/uart: merge samd21 & saml21 uart driver 
Signed-off-by: dylad <dylan.laduranty@mesotic.com>
 2017-08-29 21:26:42 +02:00
Thomas Eichinger
f286f2a276 Merge pull request #7492 from Hyungsin/forupstream_samr21_uart 2017-08-29 08:58:08 -07:00
Hyungsin
5dac8fc263 cpu/samd21: include uart driver only when UART_NUMOF is defined 2017-08-29 08:51:10 -07:00
Alexandre Abadie
24a1aacca2 cpu/sam0: add missing doxygen group definition + cleanup 2017-08-24 14:54:47 +02:00
Alexandre Abadie
4d54dc43fc Merge pull request #7359 from photonthunder/samd21_DFLL_fix 
samd21:DFLL bug
 2017-08-16 18:18:26 +02:00
Alexandre Abadie
03caac8951 Merge pull request #7307 from Hyungsin/forupstream_gpio_fix 
samd21: gpio support samr21e18a
 2017-08-15 19:44:27 +02:00
Hyungsin
e8e06949eb cpu/samd21: add gpio support for samr21e18a 2017-08-15 09:43:18 -07:00
Francisco Acosta
f2efd88f98 Merge pull request #7129 from haukepetersen/opt_periph_sharetimerset 
cpu: add and use shared code for timer_set()
 2017-08-01 15:09:48 +02:00
Dan Evans
354803110d samd21:DFLL bug 2017-07-13 13:09:42 -06:00
Dan Evans
08224bd85a samd21/clock: add xosc32/DFLL option 2017-06-26 10:42:23 -06:00
smlng
692cf96297 doc: fix doxygen grouping of cpu periph drivers 2017-06-26 14:42:11 +02:00
Alexandre Abadie
1d062a93d7 Merge pull request #7125 from kbumsik/mkr-fix 
cpu/samd21: Added CPU_MODEL_SAMD21G18A interrupt config
 2017-06-22 16:00:39 +02:00
biboc
0e41861db0 Change my email address: 
<baptiste.clenet@xsoen.com>
to
<bapclenet@gmail.com>
 2017-06-19 10:38:16 +02:00
Hauke Petersen
a1499f4190 cpu: add and use shared code for timer_set() 2017-06-02 12:21:56 +02:00
Bumsik Kim
ab7ab168fb samd21: Added CPU_MODEL_SAMD21G18A interrupt config 2017-06-01 15:40:07 -04:00
Kaspar Schleiser
0fcc7d3834 cleanup: apply headerguard script output 2017-05-24 17:54:02 +02:00
Kaspar Schleiser
8501a03cbc cleanup: apply enable_debug_false.cocci to codebase (coccinelle) 
Skipped sys/cbor/cbor.c, examples/microcoap_server/microcoap_sock.c,
as they use different semantics.
 2017-05-15 18:45:43 +02:00
Hauke Petersen
de4611f830 Merge pull request #6989 from photonthunder/samd21_waitstates 
samd21/cpu:waitstates for low voltage
 2017-05-15 11:48:39 +02:00
Alexandre Abadie
6b0cf6a728 Merge pull request #7027 from dylad/saml21_adc 
saml21/adc: initial support
 2017-05-12 23:33:47 +02:00
Dan Evans
7a8551574b samd21/cpu:waitstates for low voltage 2017-05-12 14:13:09 -07:00
dylad
44dd56c3e8 sam0/adc: merged samd21 & saml21 adc driver 
Signed-off-by: dylad <dylan.laduranty@mesotic.com>
 2017-05-12 21:02:17 +02:00
Kaspar Schleiser
8f239e4c61 Merge pull request #6812 from haukepetersen/fix_cortexm_usecommonsleep 
cpu/sam0|stm32: use common cortexm_sleep()
 2017-05-11 14:44:05 +02:00
Bumsik Kim
dfba4394c6 cpu/samd21: move adc channel struct definition to periph_cpu.h 2017-05-05 10:19:39 -04:00
Travis Griggs
828a47dd6a samd21/adc: initial implementation 2017-04-27 14:54:29 -07:00
Alexandre Abadie
524ba8f55a Merge pull request #6885 from dylad/saml21_exti_pb00 
cpu/sam0: fix or add missing EXTI on GPIO
 2017-04-26 09:56:58 +02:00
dylad
0bb43529b3 cpu/samd21: do the difference between samr21 and samd21 EXTI 
Signed-off-by: dylad <dylan.laduranty@mesotic.com>
 2017-04-25 21:47:54 +02:00
dylad
2b1a1e70c3 cpu/samd21: fix NVM wait states 
Signed-off-by: dylad <dylan.laduranty@mesotic.com>
 2017-04-12 20:23:51 +02:00
dylad
e5ef668ac1 cpu/samd21: fix or add missing EXTI on GPIO 
Signed-off-by: dylad <dylan.laduranty@mesotic.com>
 2017-04-10 21:03:16 +02:00
Joakim Nohlgård
339a4da9dc Makefiles: move to new directory /makefiles 2017-04-04 15:11:54 +02:00
Hauke Petersen
190f319066 cpu/sam0|stm32: use common cortexm_sleep() 2017-03-28 20:00:03 +02:00
Hauke Petersen
5c7ed2228d pm_layerd: fix initial value for PM_BLOCKER_INITIAL 
the current value was a debugging left-over and should
actually be 0.
 2017-03-28 19:32:32 +02:00
Hauke Petersen
8064bd9fa9 periph/pwm: remove pwm_(start|stop) + doc 
- joined start/stop and poweron/poweroff
- added general documentation
 2017-02-13 09:37:31 +01:00
Hauke Petersen
4bfce892d3 drivers/periph&cpu: add and use common periph_init() 2017-01-25 16:46:46 +01:00
Hauke Petersen
ea07a6817c cpu/sam0+boards: adapted to new SPI API 
- adapted the SPI driver
- merged SPI driver for samr21 and saml21
- adapted all boards using the CPU
 2017-01-25 16:46:45 +01:00
Kaspar Schleiser
865008ea7e cpu: samd21: make isr vector table -pedantic safe 2017-01-25 10:22:02 +01:00
Kaspar Schleiser
9ec39de1d0 cpu: samd21: misc Wextra fixes 2017-01-25 10:10:47 +01:00
Alexandre Abadie
245f60edfa cpu: fix typo in author email 2017-01-19 21:45:23 +01:00
Oleg Hahm
d0316fa7ae periph timer: remove timer_irq_(en|dis)able 2017-01-14 15:34:53 +01:00
Kaspar Schleiser
db823679aa board: samr21-xpro: move periph_pm to cpu/samd21/Makefile.features 2017-01-12 16:26:02 +01:00
Kaspar Schleiser
f42e5381ee cpu: samd21: add periph/pm support 2017-01-12 16:26:01 +01:00
Kaspar Schleiser
0194091673 remove obsolete lpm code 2017-01-12 11:24:15 +01:00