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cpu: force size of CPU specific vector table

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This commit is contained in:
Hauke Petersen 2017-08-29 22:35:46 +02:00
parent 1a20ef8223
commit 3ede8e9d95
24 changed files with 50 additions and 57 deletions
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2
cpu/cc2538/vectors.c
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@ -65,7 +65,7 @@ WEAK_DEFAULT void isr_dma(void);
WEAK_DEFAULT void isr_dmaerr(void);
/* CPU specific interrupt vector table */
ISR_VECTOR(1) const isr_t vector_cpu[] = {
ISR_VECTOR(1) const isr_t vector_cpu[CPU_IRQ_NUMOF] = {
isr_gpioa, /* 16 GPIO Port A */
isr_gpiob, /* 17 GPIO Port B */
isr_gpioc, /* 18 GPIO Port C */

2
cpu/cc26x0/vectors.c
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@ -67,7 +67,7 @@ WEAK_DEFAULT void isr_adc(void);
WEAK_DEFAULT void isr_trng(void);
/* CPU specific interrupt vector table */
ISR_VECTOR(1) const isr_t vector_cpu[] = {
ISR_VECTOR(1) const isr_t vector_cpu[CPU_IRQ_NUMOF] = {
isr_edge, /* 16 AON edge detect */
isr_i2c, /* 17 I2C */
isr_rfc_cpe1, /* 18 RF Command and Packet Engine 1 */

2
cpu/cortexm_common/include/vectors_cortexm.h
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@ -23,6 +23,8 @@
extern "C" {
#endif
#include "cpu_conf.h"
/**
* @brief Use this macro to make interrupt functions overridable with the
* dummy_handler as fallback in case they are not implemented

2
cpu/ezr32wg/vectors.c
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@ -72,7 +72,7 @@ WEAK_DEFAULT void isr_emu(void);
WEAK_DEFAULT void isr_fpueh(void);
/* CPU specific interrupt vector table */
ISR_VECTOR(1) const isr_t vector_cpu[] = {
ISR_VECTOR(1) const isr_t vector_cpu[CPU_IRQ_NUMOF] = {
isr_dma, /* 0 - DMA */
isr_gpio_even, /* 1 - GPIO_EVEN */
isr_timer0, /* 2 - TIMER0 */

2
cpu/k22f/vectors.c
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@ -21,7 +21,7 @@
#include "vectors_kinetis.h"
/* CPU specific interrupt vector table */
ISR_VECTOR(1) const isr_t vector_cpu[] = {
ISR_VECTOR(1) const isr_t vector_cpu[CPU_IRQ_NUMOF] = {
isr_dma0, /* DMA channel 0 transfer complete */
isr_dma1, /* DMA channel 1 transfer complete */
isr_dma2, /* DMA channel 2 transfer complete */

2
cpu/k60/vectors.c
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@ -30,7 +30,7 @@
#include "vectors_kinetis.h"
/* CPU specific interrupt vector table */
ISR_VECTOR(1) const isr_t vector_cpu[] = {
ISR_VECTOR(1) const isr_t vector_cpu[CPU_IRQ_NUMOF] = {
isr_dma0,
isr_dma1,
isr_dma2,

2
cpu/k64f/vectors.c
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@ -23,7 +23,7 @@
#include "vectors_kinetis.h"
/* CPU specific interrupt vector table */
ISR_VECTOR(1) const isr_t vector_cpu[] = {
ISR_VECTOR(1) const isr_t vector_cpu[CPU_IRQ_NUMOF] = {
isr_dma0, /* DMA channel 0 transfer complete */
isr_dma1, /* DMA channel 1 transfer complete */
isr_dma2, /* DMA channel 2 transfer complete */

2
cpu/kw2xd/vectors.c
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@ -23,7 +23,7 @@
#include "vectors_kinetis.h"
/* CPU specific interrupt vector table */
ISR_VECTOR(1) const isr_t vector_cpu[] = {
ISR_VECTOR(1) const isr_t vector_cpu[CPU_IRQ_NUMOF] = {
isr_dma0, /* DMA channel 0 transfer complete */
isr_dma1, /* DMA channel 1 transfer complete */
isr_dma2, /* DMA channel 2 transfer complete */

2
cpu/lm4f120/include/cpu_conf.h
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@ -56,7 +56,7 @@ extern "C" {
* @{
*/
#define CPU_DEFAULT_IRQ_PRIO (1U)
#define CPU_IRQ_NUMOF (48U)
#define CPU_IRQ_NUMOF (139U)
#define CPU_FLASH_BASE FLASH_BASE
/** @} */

2
cpu/lm4f120/vectors.c
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@ -100,7 +100,7 @@ WEAK_DEFAULT void isr_wtimer5b(void);
WEAK_DEFAULT void isr_sysex(void);
/* CPU specific interrupt vector table */
ISR_VECTOR(1) const isr_t vector_cpu[] = {
ISR_VECTOR(1) const isr_t vector_cpu[CPU_IRQ_NUMOF] = {
isr_gpio_porta, /* GPIO Port A 16 */
isr_gpio_portb, /* GPIO Port B 17 */
isr_gpio_portc, /* GPIO Port C 18 */

2
cpu/lpc1768/vectors.c
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@ -66,7 +66,7 @@ WEAK_DEFAULT void isr_qei(void);
WEAK_DEFAULT void isr_pll1(void);
/* CPU specific interrupt vector table */
ISR_VECTOR(1) const isr_t vector_cpu[] = {
ISR_VECTOR(1) const isr_t vector_cpu[CPU_IRQ_NUMOF] = {
isr_wdt, /* watchdog timer */
isr_timer0, /* timer0 */
isr_timer1, /* timer1 */

59
cpu/nrf51/vectors.c
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@ -70,37 +70,30 @@ WEAK_DEFAULT void isr_swi4(void);
WEAK_DEFAULT void isr_swi5(void);
/* CPU specific interrupt vector table */
ISR_VECTOR(1) const isr_t vector_cpu[] = {
isr_power_clock, /* power_clock */
isr_radio, /* radio */
isr_uart0, /* uart0 */
isr_spi0_twi0, /* spi0_twi0 */
isr_spi1_twi1, /* spi1_twi1 */
(0UL), /* reserved */
isr_gpiote, /* gpiote */
isr_adc, /* adc */
isr_timer0, /* timer0 */
isr_timer1, /* timer1 */
isr_timer2, /* timer2 */
isr_rtc0, /* rtc0 */
isr_temp, /* temp */
isr_rng, /* rng */
isr_ecb, /* ecb */
isr_ccm_aar, /* ccm_aar */
isr_wdt, /* wdt */
isr_rtc1, /* rtc1 */
isr_qdec, /* qdec */
isr_lpcomp, /* lpcomp */
isr_swi0, /* swi0 */
isr_swi1, /* swi1 */
isr_swi2, /* swi2 */
isr_swi3, /* swi3 */
isr_swi4, /* swi4 */
isr_swi5, /* swi5 */
(0UL), /* reserved */
(0UL), /* reserved */
(0UL), /* reserved */
(0UL), /* reserved */
(0UL), /* reserved */
(0UL), /* reserved */
ISR_VECTOR(1) const isr_t vector_cpu[CPU_IRQ_NUMOF] = {
[ 0] = isr_power_clock, /* power_clock */
[ 1] = isr_radio, /* radio */
[ 2] = isr_uart0, /* uart0 */
[ 3] = isr_spi0_twi0, /* spi0_twi0 */
[ 4] = isr_spi1_twi1, /* spi1_twi1 */
[ 6] = isr_gpiote, /* gpiote */
[ 7] = isr_adc, /* adc */
[ 8] = isr_timer0, /* timer0 */
[ 9] = isr_timer1, /* timer1 */
[10] = isr_timer2, /* timer2 */
[11] = isr_rtc0, /* rtc0 */
[12] = isr_temp, /* temp */
[13] = isr_rng, /* rng */
[14] = isr_ecb, /* ecb */
[15] = isr_ccm_aar, /* ccm_aar */
[16] = isr_wdt, /* wdt */
[17] = isr_rtc1, /* rtc1 */
[18] = isr_qdec, /* qdec */
[19] = isr_lpcomp, /* lpcomp */
[20] = isr_swi0, /* swi0 */
[21] = isr_swi1, /* swi1 */
[22] = isr_swi2, /* swi2 */
[23] = isr_swi3, /* swi3 */
[24] = isr_swi4, /* swi4 */
[25] = isr_swi5, /* swi5 */
};

2
cpu/nrf52/vectors.c
View File

@ -100,7 +100,7 @@ extern void SWI2_EGU2_IRQHandler(void);
#endif
/* CPU specific interrupt vector table */
ISR_VECTOR(1) const isr_t vector_cpu[] = {
ISR_VECTOR(1) const isr_t vector_cpu[CPU_IRQ_NUMOF] = {
isr_power_clock, /* power_clock */
isr_radio, /* radio */
isr_uart0, /* uart0 */

2
cpu/sam3/vectors.c
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@ -78,7 +78,7 @@ WEAK_DEFAULT void isr_can0(void);
WEAK_DEFAULT void isr_can1(void);
/* CPU specific interrupt vector table */
ISR_VECTOR(1) const isr_t vector_cpu[] = {
ISR_VECTOR(1) const isr_t vector_cpu[CPU_IRQ_NUMOF] = {
isr_supc, /* 0 supply controller */
isr_rstc, /* 1 reset controller */
isr_rtc, /* 2 real time clock */

4
cpu/samd21/vectors.c
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@ -20,8 +20,6 @@
*/
#include <stdint.h>
#include "cpu_conf.h"
#include "vectors_cortexm.h"
/* get the start of the ISR stack as defined in the linkerscript */
@ -64,7 +62,7 @@ WEAK_DEFAULT void isr_ptc(void);
WEAK_DEFAULT void isr_i2c(void);
/* CPU specific interrupt vector table */
ISR_VECTOR(1) const isr_t vector_cpu[] = {
ISR_VECTOR(1) const isr_t vector_cpu[CPU_IRQ_NUMOF] = {
isr_pm, /* 0 Power Manager */
isr_sysctrl, /* 1 System Control */
isr_wdt, /* 2 Watchdog Timer */

2
cpu/saml21/vectors.c
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@ -65,7 +65,7 @@ WEAK_DEFAULT void isr_aes(void);
WEAK_DEFAULT void isr_trng(void);
/* CPU specific interrupt vector table */
ISR_VECTOR(1) const isr_t vector_cpu[] = {
ISR_VECTOR(1) const isr_t vector_cpu[CPU_IRQ_NUMOF] = {
(void*) isr_pm, /* 0 Power Manager */
(void*) isr_wdt, /* 1 Watchdog Timer */
(void*) isr_rtc, /* 2 Real-Time Counter */

2
cpu/stm32f0/vectors.c
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@ -63,7 +63,7 @@ WEAK_DEFAULT void isr_cec(void);
WEAK_DEFAULT void isr_usb(void);
/* CPU specific interrupt vector table */
ISR_VECTOR(1) const isr_t vector_cpu[] = {
ISR_VECTOR(1) const isr_t vector_cpu[CPU_IRQ_NUMOF] = {
isr_wwdg, /* [0] windowed watchdog */
#if defined(CPU_MODEL_STM32F030R8)
(0UL), /* [1] reserved */

2
cpu/stm32f1/vectors.c
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@ -88,7 +88,7 @@ WEAK_DEFAULT void isr_dma2_ch3(void);
WEAK_DEFAULT void isr_dma2_ch4_5(void);
/* CPU specific interrupt vector table */
ISR_VECTOR(1) const isr_t vector_cpu[] = {
ISR_VECTOR(1) const isr_t vector_cpu[CPU_IRQ_NUMOF] = {
isr_wwdg, /* [0] Window WatchDog Interrupt */
isr_pvd, /* [1] PVD through EXTI Line detection Interrupt */
isr_tamper, /* [2] Tamper Interrupt */

2
cpu/stm32f2/vectors.c
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@ -113,7 +113,7 @@ WEAK_DEFAULT void isr_cryp(void);
WEAK_DEFAULT void isr_hash_rng(void);
/* CPU specific interrupt vector table */
ISR_VECTOR(1) const isr_t vector_cpu[] = {
ISR_VECTOR(1) const isr_t vector_cpu[CPU_IRQ_NUMOF] = {
isr_wwdg, /* [0] Window WatchDog */
isr_pvd, /* [1] PVD through EXTI Line detection */
isr_tamp_stamp, /* [2] Tamper and TimeStamps through the EXTI line */

2
cpu/stm32f3/vectors.c
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@ -109,7 +109,7 @@ WEAK_DEFAULT void isr_fpu(void);
WEAK_DEFAULT void isr_spi4(void);
/* CPU specific interrupt vector table */
ISR_VECTOR(1) const isr_t vector_cpu[] = {
ISR_VECTOR(1) const isr_t vector_cpu[CPU_IRQ_NUMOF] = {
isr_wwdg, /* [0] Window WatchDog Interrupt */
isr_pvd, /* [1] PVD through EXTI Line detection Interrupt */
isr_tamp_stamp, /* [2] Tamper and TimeStamp interrupts through the EXTI line 19 */

2
cpu/stm32f4/vectors.c
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@ -138,7 +138,7 @@ WEAK_DEFAULT void isr_ltdc_er(void);
WEAK_DEFAULT void isr_dma2d(void);
/* CPU specific interrupt vector table */
ISR_VECTOR(1) const isr_t vector_cpu[] = {
ISR_VECTOR(1) const isr_t vector_cpu[CPU_IRQ_NUMOF] = {
isr_wwdg, /* [0] Window WatchDog */
isr_pvd, /* [1] PVD through EXTI Line detection */
isr_tamp_stamp, /* [2] Tamper and TimeStamps through the EXTI line */

2
cpu/stm32f7/vectors.c
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@ -141,7 +141,7 @@ WEAK_DEFAULT void isr_sdmmc2(void);
#endif
/* CPU specific interrupt vector table */
ISR_VECTOR(1) const isr_t vector_cpu[] = {
ISR_VECTOR(1) const isr_t vector_cpu[CPU_IRQ_NUMOF] = {
isr_wwdg, /* [0] Window WatchDog Interrupt */
isr_pvd, /* [1] PVD through EXTI Line detection Interrupt */
isr_tamp_stamp, /* [2] Tamper and TimeStamp interrupts through the EXTI line */

2
cpu/stm32l0/vectors.c
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@ -65,7 +65,7 @@ WEAK_DEFAULT void isr_lcd(void);
WEAK_DEFAULT void isr_usb(void);
/* CPU specific interrupt vector table */
ISR_VECTOR(1) const isr_t vector_cpu[] = {
ISR_VECTOR(1) const isr_t vector_cpu[CPU_IRQ_NUMOF] = {
isr_wwdg, /* [0] windowed watchdog */
isr_pvd, /* [1] power control */
isr_rtc, /* [2] real time clock */

2
cpu/stm32l1/vectors.c
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@ -85,7 +85,7 @@ WEAK_DEFAULT void isr_aes(void);
WEAK_DEFAULT void isr_comp_acq(void);
/* CPU specific interrupt vector table */
ISR_VECTOR(1) const isr_t vector_cpu[] = {
ISR_VECTOR(1) const isr_t vector_cpu[CPU_IRQ_NUMOF] = {
isr_wwdg, /* [0] Window WatchDog Interrupt */
isr_pvd, /* [1] PVD through EXTI Line detection Interrupt */
isr_tamper_stamp, /* [2] Tamper and Time Stamp through EXTI Line Interrupts */