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256 lines
13 KiB
C
256 lines
13 KiB
C
/*
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* Copyright (C) 2014-2015 Freie Universität Berlin
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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/**
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* @ingroup cpu_stm32f0
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* @{
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*
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* @file
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* @brief Interrupt vector definitions
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*
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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*
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* @}
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*/
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#include <stdint.h>
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#include "vectors_cortexm.h"
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/* get the start of the ISR stack as defined in the linkerscript */
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extern uint32_t _estack;
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/* define a local dummy handler as it needs to be in the same compilation unit
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* as the alias definition */
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void dummy_handler(void) {
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dummy_handler_default();
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}
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/* STM32F0 specific interrupt vectors */
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WEAK_DEFAULT void isr_wwdg(void);
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WEAK_DEFAULT void isr_pvd(void);
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WEAK_DEFAULT void isr_rtc(void);
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WEAK_DEFAULT void isr_flash(void);
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WEAK_DEFAULT void isr_rcc(void);
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WEAK_DEFAULT void isr_exti(void);
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WEAK_DEFAULT void isr_ts(void);
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WEAK_DEFAULT void isr_dma1_ch1(void);
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WEAK_DEFAULT void isr_dma1_ch2_3(void);
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WEAK_DEFAULT void isr_dma1_ch4_5(void);
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WEAK_DEFAULT void isr_adc1_comp(void);
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WEAK_DEFAULT void isr_tim1_brk_up_trg_com(void);
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WEAK_DEFAULT void isr_tim1_cc(void);
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WEAK_DEFAULT void isr_tim2(void);
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WEAK_DEFAULT void isr_tim3(void);
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WEAK_DEFAULT void isr_tim6_dac(void);
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WEAK_DEFAULT void isr_tim7(void);
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WEAK_DEFAULT void isr_tim14(void);
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WEAK_DEFAULT void isr_tim15(void);
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WEAK_DEFAULT void isr_tim16(void);
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WEAK_DEFAULT void isr_tim17(void);
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WEAK_DEFAULT void isr_i2c1(void);
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WEAK_DEFAULT void isr_i2c2(void);
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WEAK_DEFAULT void isr_spi1(void);
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WEAK_DEFAULT void isr_spi2(void);
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WEAK_DEFAULT void isr_usart1(void);
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WEAK_DEFAULT void isr_usart2(void);
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WEAK_DEFAULT void isr_usart3_8(void);
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WEAK_DEFAULT void isr_cec(void);
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WEAK_DEFAULT void isr_usb(void);
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/* CPU specific interrupt vector table */
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ISR_VECTOR(1) const isr_t vector_cpu[CPU_IRQ_NUMOF] = {
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isr_wwdg, /* [0] windowed watchdog */
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#if defined(CPU_MODEL_STM32F030R8)
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(0UL), /* [1] reserved */
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isr_rtc, /* [2] real time clock */
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isr_flash, /* [3] flash memory controller */
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isr_rcc, /* [4] reset and clock control */
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isr_exti, /* [5] external interrupt lines 0 and 1 */
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isr_exti, /* [6] external interrupt lines 2 and 3 */
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isr_exti, /* [7] external interrupt lines 4 to 15 */
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(0UL), /* [8] reserved */
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isr_dma1_ch1, /* [9] direct memory access controller 1, channel 1*/
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isr_dma1_ch2_3, /* [10] direct memory access controller 1, channel 2 and 3*/
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isr_dma1_ch4_5, /* [11] direct memory access controller 1, channel 4 and 5*/
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isr_adc1_comp, /* [12] analog digital converter */
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isr_tim1_brk_up_trg_com, /* [13] timer 1 break, update, trigger and communication */
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isr_tim1_cc, /* [14] timer 1 capture compare */
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isr_tim2, /* [15] timer 2 */
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isr_tim3, /* [16] timer 3 */
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isr_tim6_dac, /* [17] timer 6 and digital to analog converter */
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(0UL), /* [18] reserved */
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isr_tim14, /* [19] timer 14 */
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isr_tim15, /* [20] timer 15 */
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isr_tim16, /* [21] timer 16 */
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isr_tim17, /* [22] timer 17 */
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isr_i2c1, /* [23] I2C 1 */
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isr_i2c2, /* [24] I2C 2 */
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isr_spi1, /* [25] SPI 1 */
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isr_spi2, /* [26] SPI 2 */
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isr_usart1, /* [27] USART 1 */
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isr_usart2 /* [28] USART 2 */
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#elif defined(CPU_MODEL_STM32F031K6)
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isr_pvd, /* [1] power control */
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isr_rtc, /* [2] real time clock */
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isr_flash, /* [3] flash memory controller */
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isr_rcc, /* [4] reset and clock control */
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isr_exti, /* [5] external interrupt lines 0 and 1 */
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isr_exti, /* [6] external interrupt lines 2 and 3 */
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isr_exti, /* [7] external interrupt lines 4 to 15 */
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(0UL), /* [8] reserved */
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isr_dma1_ch1, /* [9] direct memory access controller 1, channel 1*/
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isr_dma1_ch2_3, /* [10] direct memory access controller 1, channel 2 and 3*/
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isr_dma1_ch4_5, /* [11] direct memory access controller 1, channel 4 and 5*/
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isr_adc1_comp, /* [12] analog digital converter */
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isr_tim1_brk_up_trg_com, /* [13] timer 1 break, update, trigger and communication */
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isr_tim1_cc, /* [14] timer 1 capture compare */
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isr_tim2, /* [15] timer 2 */
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isr_tim3, /* [16] timer 3 */
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(0UL), /* [17] reserved */
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(0UL), /* [18] reserved */
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isr_tim14, /* [19] timer 14 */
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(0UL), /* [20] reserved */
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isr_tim16, /* [21] timer 16 */
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isr_tim17, /* [22] timer 17 */
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isr_i2c1, /* [23] I2C 1 */
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(0UL), /* [24] reserved */
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isr_spi1, /* [25] SPI 1 */
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(0UL), /* [26] reserved */
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isr_usart1 /* [27] USART 1 */
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#elif defined(CPU_MODEL_STM32F042K6)
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isr_pvd, /* [1] power control */
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isr_rtc, /* [2] real time clock */
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isr_flash, /* [3] flash memory controller */
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isr_rcc, /* [4] reset and clock control */
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isr_exti, /* [5] external interrupt lines 0 and 1 */
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isr_exti, /* [6] external interrupt lines 2 and 3 */
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isr_exti, /* [7] external interrupt lines 4 to 15 */
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isr_ts, /* [8] touch sensing input*/
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isr_dma1_ch1, /* [9] direct memory access controller 1, channel 1*/
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isr_dma1_ch2_3, /* [10] direct memory access controller 1, channel 2 and 3*/
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isr_dma1_ch4_5, /* [11] direct memory access controller 1, channel 4 and 5*/
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isr_adc1_comp, /* [12] analog digital converter */
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isr_tim1_brk_up_trg_com, /* [13] timer 1 break, update, trigger and communication */
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isr_tim1_cc, /* [14] timer 1 capture compare */
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isr_tim2, /* [15] timer 2 */
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isr_tim3, /* [16] timer 3 */
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(0UL), /* [17] reserved */
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(0UL), /* [18] reserved */
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isr_tim14, /* [19] timer 14 */
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(0UL), /* [20] reserved */
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isr_tim16, /* [21] timer 16 */
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isr_tim17, /* [22] timer 17 */
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isr_i2c1, /* [23] I2C 1 */
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(0UL), /* [24] reserved */
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isr_spi1, /* [25] SPI 1 */
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isr_spi2, /* [26] SPI 2 */
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isr_usart1, /* [27] USART 1 */
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isr_usart2, /* [28] USART 2 */
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(0UL), /* [29] reserved */
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isr_cec, /* [30] consumer electronics control */
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isr_usb /* [31] USB global Interrupts & EXTI Line18 Interrup */
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#elif defined(CPU_MODEL_STM32F051R8)
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isr_pvd, /* [1] power control */
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isr_rtc, /* [2] real time clock */
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isr_flash, /* [3] flash memory controller */
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isr_rcc, /* [4] reset and clock control */
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isr_exti, /* [5] external interrupt lines 0 and 1 */
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isr_exti, /* [6] external interrupt lines 2 and 3 */
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isr_exti, /* [7] external interrupt lines 4 to 15 */
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isr_ts, /* [8] touch sensing input*/
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isr_dma1_ch1, /* [9] direct memory access controller 1, channel 1*/
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isr_dma1_ch2_3, /* [10] direct memory access controller 1, channel 2 and 3*/
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isr_dma1_ch4_5, /* [11] direct memory access controller 1, channel 4 and 5*/
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isr_adc1_comp, /* [12] analog digital converter */
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isr_tim1_brk_up_trg_com, /* [13] timer 1 break, update, trigger and communication */
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isr_tim1_cc, /* [14] timer 1 capture compare */
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isr_tim2, /* [15] timer 2 */
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isr_tim3, /* [16] timer 3 */
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isr_tim6_dac, /* [17] timer 6 and digital to analog converter */
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(0UL), /* [18] reserved */
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isr_tim14, /* [19] timer 14 */
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isr_tim15, /* [20] timer 15 */
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isr_tim16, /* [21] timer 16 */
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isr_tim17, /* [22] timer 17 */
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isr_i2c1, /* [23] I2C 1 */
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isr_i2c2, /* [24] I2C 2 */
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isr_spi1, /* [25] SPI 1 */
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isr_spi2, /* [26] SPI 2 */
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isr_usart1, /* [27] USART 1 */
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isr_usart2, /* [28] USART 2 */
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(0UL), /* [29] reserved */
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isr_cec, /* [30] consumer electronics control */
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#elif defined(CPU_MODEL_STM32F070RB)
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(0UL), /* [1] reserved */
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isr_rtc, /* [2] real time clock */
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isr_flash, /* [3] flash memory controller */
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isr_rcc, /* [4] reset and clock control */
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isr_exti, /* [5] external interrupt lines 0 and 1 */
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isr_exti, /* [6] external interrupt lines 2 and 3 */
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isr_exti, /* [7] external interrupt lines 4 to 15 */
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isr_ts, /* [8] touch sensing input*/
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isr_dma1_ch1, /* [9] direct memory access controller 1, channel 1*/
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isr_dma1_ch2_3, /* [10] direct memory access controller 1, channel 2 and 3*/
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isr_dma1_ch4_5, /* [11] direct memory access controller 1, channel 4 and 5*/
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isr_adc1_comp, /* [12] analog digital converter */
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isr_tim1_brk_up_trg_com, /* [13] timer 1 break, update, trigger and communication */
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isr_tim1_cc, /* [14] timer 1 capture compare */
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(0UL), /* [15] reserved */
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isr_tim3, /* [16] timer 3 */
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isr_tim6_dac, /* [17] timer 6 and digital to analog converter */
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isr_tim7, /* [18] timer 7 */
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isr_tim14, /* [19] timer 14 */
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isr_tim15, /* [20] timer 15 */
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isr_tim16, /* [21] timer 16 */
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isr_tim17, /* [22] timer 17 */
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isr_i2c1, /* [23] I2C 1 */
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isr_i2c2, /* [24] I2C 2 */
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isr_spi1, /* [25] SPI 1 */
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isr_spi2, /* [26] SPI 2 */
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isr_usart1, /* [27] USART 1 */
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isr_usart2, /* [28] USART 2 */
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isr_usart3_8, /* [29] USART 3 to 8 */
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(0UL), /* [30] reserved */
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isr_usb /* [31] USB global Interrupts & EXTI Line18 Interrup */
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#else /* CPU_MODEL_STM32_F072RB, CPU_MODEL_STM32F091RC*/
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isr_pvd, /* [1] power control */
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isr_rtc, /* [2] real time clock */
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isr_flash, /* [3] flash memory controller */
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isr_rcc, /* [4] reset and clock control */
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isr_exti, /* [5] external interrupt lines 0 and 1 */
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isr_exti, /* [6] external interrupt lines 2 and 3 */
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isr_exti, /* [7] external interrupt lines 4 to 15 */
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isr_ts, /* [8] touch sensing input*/
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isr_dma1_ch1, /* [9] direct memory access controller 1, channel 1*/
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isr_dma1_ch2_3, /* [10] direct memory access controller 1, channel 2 and 3*/
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isr_dma1_ch4_5, /* [11] direct memory access controller 1, channel 4 and 5*/
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isr_adc1_comp, /* [12] analog digital converter */
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isr_tim1_brk_up_trg_com, /* [13] timer 1 break, update, trigger and communication */
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isr_tim1_cc, /* [14] timer 1 capture compare */
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isr_tim2, /* [15] timer 2 */
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isr_tim3, /* [16] timer 3 */
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isr_tim6_dac, /* [17] timer 6 and digital to analog converter */
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isr_tim7, /* [18] timer 7 */
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isr_tim14, /* [19] timer 14 */
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isr_tim15, /* [20] timer 15 */
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isr_tim16, /* [21] timer 16 */
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isr_tim17, /* [22] timer 17 */
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isr_i2c1, /* [23] I2C 1 */
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isr_i2c2, /* [24] I2C 2 */
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isr_spi1, /* [25] SPI 1 */
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isr_spi2, /* [26] SPI 2 */
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isr_usart1, /* [27] USART 1 */
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isr_usart2, /* [28] USART 2 */
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isr_usart3_8, /* [29] USART 3 to 8 */
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isr_cec, /* [30] consumer electronics control */
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#if defined(CPU_MODEL_STM32F072RB)
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isr_usb /* [31] USB global Interrupts & EXTI Line18 Interrup */
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#endif
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#endif
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};
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