With the change from using archive files to using object files in PR #14754, the module `esp_wifi_enterprise` was no longer compilable. The reason for this was that the file `bignum.c` was present in two different vendor sub-directories and created two identical object files, which then led to a symbol conflict when linking. This commit removes one of these identical files. The one that is used in all `esp_wifi` variants is kept, the one that is only used in `esp_wifi_enterprise` is dropped.
The IRAM is much faster, while the IROM is much slower and can only be accessed via a cache, which is also sometimes disabled, e.g. by the WiFi module or when writing to the flash. Therefore, time-critical code as well as code that has to work even when the cache is disabled must be placed in the IRAM.
Checksumming flash is not supported on xtensa platform:
Warn : not implemented yet
make: *** [.../RIOT/examples/saul/../../Makefile.include:796: flash] Error 1
https://github.com/espressif/openocd-esp32 is needed.
Example config (when compiled from source):
export OPENOCD="~/esp/openocd-esp32/src/openocd -s ~/esp/openocd-esp32/tcl"
If esp_idf_heap is not used, implement calloc through a custom wrapper
function on top of malloc to add overflow detection, which is not
present in the newlib forks with xtensa support yet.
The RTT overflow callback is not available on all RTT implementations.
This means it is either a no-op or `rtt_set_overflow_cb()` is a no-op
or it will overwrite the alarm set with `rtt_set_alarm()`.
This adds a feature to indicate that proper overflow reporting is available.
Some periph_rtt implementations do not provide `rtt_set_counter()`. This
adds `periph_rtt_set_counter` as feature to allow testing for its
availability. The feature is provided at CPU level if periph_rtt is
provided by the board for all CPUs implementing `rtt_set_counter()`.
Some periph_rtt implementations do not provide `rtt_set_counter()`. This
adds `periph_rtt_set_counter` as feature to allow testing for its
availability. The feature is provided at CPU level if periph_rtt is
provided by the board for all CPUs implementing `rtt_set_counter()`.
If there is an event to be handled by _esp_eth_isr(), don't
overwrite it if a new packet has been received.
In my testing, all SYSTEM_EVENT_ETH_CONNECTED events except the first
are immediately followed by at least one SYSTEM_EVENT_ETH_RX_DONE event.
This causes the SYSTEM_EVENT_ETH_CONNECTED to not get handled, and the
IP stack will not be notified of the new link state.
Protect the other events by dropping the packet instead. If an earlier
unhandled SYSTEM_EVENT_ETH_RX_DONE event exists, overwrite it with the
newer packet.
I only saw this happen with lwIP and not with GNRC - I am not sure why.
But it still is a race waiting to happen. The nice long term solution
is probably to have a queue of unhandled events, allowing them all to
be processed once there is time.
This is an implementation of the ESP32 SoftAP mode using the
`esp_wifi_ap` pseudomodule.
Signed-off-by: Jean Pierre Dudey <jeandudey@hotmail.com>
Co-authored-by: Gunar Schorcht <gunar@schorcht.net>
Add `TARGET_ARCH_<ARCH>` for each architecture (e.g. `TARGET_ARCH_CORTEX` for
Cortex M) to allow users to overwrite the target triple for a specific arch
from ~/.profile or ~/.bashrc (or the like) without overwriting it for all others
as well.
Since former ESP32 toolchain versions used POSIX threads, module `pthread` was required. The built-in `cxa_ctor_guards` had to be replaced since they used the `pthread_once` function for singleton objects initialization where the parameter `once` was of incompatible type with that provided by RIOT's `pthread` module. The current ESP32 toolchain version no longer uses POSIX threads. The dependency on module `pthread` as well as according C++ hacks can be removed.
In #12955 optimization was switched to O2 because with the '-Os'
option, the ESP32 hangs sporadically in 'tests/bench*' if
interrupts where disabled too early by benchmark tests.
Since it hasn't been reproduced since and in #13196 O2 was causing
un-explained hardfaults, since the aforementioned issue could not
be reproduced we switch back to Os by removing O2, as Os will be
used by default.
GPIO32 and GPIO33 are used during boot to start an 32.768 kHz XTAL if it is connected to these GPIOs. If the 32.768 kHz XTAL is not connected, these pins can be used digital IO. However, the 32.678 kHz XTAL has to be disabled explicitly in this case. Furthermore, the handling of GPIOs greater than GPIO31 had to be fixed in I2C software implementation.
When entering a sleep mode, all wake-up sources should first be disabled before the wake-up sources required for the sleep mode are then stepwise enabled again. Otherwise, an wake-up configuration of one sleep mode may affect the wake-up within another sleep mode.
The WiFi interface should be stopped before reboot or sleep. But stopping the WiFi interface disconnects an existing connection. Usually, esp_wifi_netdev tries to reconnect on an disconnect event. However, trying reconnect with a stopped WiFi interface may lead to a crash. Therefore, the stop event has to be handled.
Now, where the vendor files for light/deep sleep mode are added, function `pm_off` does not need to implement this mode by itself. Instead the existing deep sleep with disabled wakeup sources is used for pm_off.
`rtc_init` is used after light sleep to update the system time from RTC timer. The fix corrects a small difference of about 230 ms which would sum up with each wakeup from light sleep.
By using a custom EPOCH for the RTC implementation, we can extend the
range of the 32 bit counter based RTC by 118 years.
It also reduces the code size compared to the stdlib based POSIX functions.
To be able to define common configurations for all ESP CPUs, the CPU specific configuration cpu_conf.h has to include a common configuration. For that purpose cpu_conf.h in cpu/esp_common is renamed to cpu_conf_common.h and included in CPU specific configurations.
During the write access to the SPI flash, the IROM cache is not available and only code from the IRAM can be executed. Therefore, the code of file system implementations which access the SPI flash must reside in IRAM.
