Functions that are used by ADC and DAC peripherals are moved to a new submodule periph_adc_ctrl. This is necessary to compile separate submodules for ADC and DAC.
`top_of_stack` isn't aligned down to the previous 16 byte aligned address. Furthermore, `top_of_stack` as well as `XT_CP_SIZE` are used unaligned in `cpu/esp_common/vendor/xtensa/portasm.S` in the address computation for the coprocessor save area, .
Aligning pointer `p` down to the previous 16 byte aligned address results in a wrong address of the coprocessor save area during the initialization of the thread context. This leads to wrong values and wrong positions of these values in the coprocessor save area in inital thread context.
Since ESP8266 doesn't have a coprocessor, this bug affects only ESP32.
Functions marked with __atribute__((naked)) may only use basic inline assembly
and must not use any c code. The functions __enter_thread_mode() and
cpu_switch_context_exit() are using C code, so they must not be marked as
naked.
Previously the compiler was allowed to reorder access to the interrupt control
registers in regard to memory access not marked as `volatile` (at least some
people - most notably some compiler developers - read the C standard this way).
In practise this did not happen as irq_disable(), irq_restore(), irq_enable()
are part of a separate compilation unit: Calls to external functions unknown to
the compiler are treated as if they were memory barriers. But if link time
optimization (LTO) is enabled, this no longer would work: The compiler could
inline the code accessing the interrupt control registers and reorder the memory
accesses wrapped in irq_disable() and irq_restore() outside of their protection.
This commit adds the "memory" clobber to the inline assembly accessing the
interrupt control registers. This makes those accesses explicit compiler memory
barriers. The machine code generated without LTO enabled should not differ in
any way by this commit. But the use of irq_*() should now be safe with LTO.
During the flash step esptool.py gives the following warning:
WARNING: Flash size arguments in megabits like '16m' are deprecated.
Please use the equivalent size '2MB'.
Megabit arguments may be removed in a future release.
esptool.py v2.7-dev
This patch replaces '16m' with '2MB' to enable future compatibility.
Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
The currently supported SAM0 MCUs (samd21, saml21, saml1x) share the
same RTC peripheral, yet each of them carries it's own copy of the RTC
driver.
Unify the drivers and move them to sam0_common.
Usually, the access to the IROM (flash) memory requires 32-bit word aligned reads. Attempts to access data in the IROM (flash) memory less than 32 bits in size triggers a LoadStoreError exception. With the exception handler from esp-open-rtos it becomes possible to access data in IROM (flash) with a size of less than 32 bits and thus to place .rodata sections in the IROM (flash).
Fix of #11354: Function '_write_r' of ESP32's newlibc does not write the output of function 'write(STDIO_FILENO, ...)' to the UART interface. To fix this problem, module 'newlib_syscalls_default' is now used by default. Function '_write_r' of module 'newlib_syscalls_default' uses 'stdio_write' which in turn uses 'uart_write' if module 'stdio_uart' is used which is now the default case for ESP32.
This commit cleans up magic number and defines bitfields.
Adds error codes for ADDR/DATA NACK and ARBLOSS
Adds error handling, it corrects when an error occurs
Protects from flags that could lockup the bus
For this purpose, adapted AVR libc functions are used. When used, malloc and free functions require 304 additional bytes of code compared to the oneway_malloc module.
This driver is compliant with the candev interface. It has been tested
with STM32F0 and STM32F2 and STM32F413 ONLY at this time but should be
compliant with other STM32Fx devices
The GPIO for RX has to be initialized as input before the GPIO for TX can be initialized as output. Otherwise it could lead to creash if RX GPIO was used as output before.
Function uart_set_baudrate which is only used internally was made static and renamed to _uart_set_baudrate to indicate that it is an internal function. Furthermore, an additional waiting for flushed TX FIFO added. The reconfiguration is now handled as critical section.
An additional _ for static symbols has been added by mistake and should be removed. This will make future merging with the reimplementation of ESP8266 easier.
There is an error when the start byte NACKs
The nack sets the stop bit twice which keeps the stop bit high the next time
When the stop bit is high it creates a timeout when trying to use
This commit fixes so when a NACK occures on the address it doesn't stop twice
It must be evaluated in `cortexm_common` without a shell context.
The `K` is correctly handled by both the linker and `cortexm_common`.
Co-authored-by: Gaëtan Harter <gaetan.harter@fu-berlin.de>
The build system contains several instances of
INCLUDES += -I$(RIOTBASE)/sys/posix/include
This is bypassing the module management system, by directly accesing
headers without depending on a module. The module is the posix module.
That line is also added when one of the posix_* modules is requested.
According to the docs, the posix module provides headers only, but in
reality there is also inet.c.
This patch:
- Moves `inet.c` into `posix_inet`, leaving `posix` as a headers-only
module.
- Rename `posix` as `posix_headers` to make it clear the module only
includes headers.
- Makes `posix_*` modules depend on `posix_headers`, thus removing the
explicit `INCLUDES+=...` in `sys/Makefile.include`.
- Ocurrences of `INCLUDES+=...` are replaced by an explicit dependency
on `posix_headers`.
USART_CR1_M combines both USART_CR1_M0 and USART_CR1_M1 macros
affecting bits 12 and 28 on 7 data bits capable UARTs. Whereas
for other UARTs USART_CR1_M macro affects only bit 12.
This patch fixes wrong data bits usage on 7 data bits capable
UARTs with using USART_CR1_M0 macro for modes 8-E-x and 8-O-x.
It also simplifies bits unsetting as USART_CR1_M macro clears
all data bits related bits for both UART types.
Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
The timer_clear function doesn't clear the hardware timer counter, but
is designed to clear the allocation of the channel. The consequence is
that the IFS timer here is not set to zero in the callback, but only
stopped at the current value. When the timer is started again, it has to
count the full timer range until it matches the timeout value again.
This commit fixes this issue by using timer_set instead of
timer_set_absolute. This way the current timer value (when the timer is
stopped) is read and the IFS timeout value is added to the current timer
value.
ieee802.15.4 specifies 40 symbols as LIFS value and 12 symbols as SIFS
value. Furthermore, the 2.4Ghz DSSS mode has a symbol rate of
62.5Ksymbols/s. To have the LIFS and SIFS in the code match the timings
from the specification, the TIMER_FREQ must match the symbol rate of
62.5Ksymbol/s such that one tick of the timer equals one symbol in time.
If the GPIO is in an output state, gpio_init() can return 0 without bad
consequences.
-1 was return until now.
Signed-off-by: Gilles DOFFE <g.doffe@gmail.com>
Calling the initialization function ensures that the dummy lwIP library is used instead of the real lwIP, even if the esp_wifi module for esp8266 is not used.
The documentation had to be changed due to the relation of module `esp_now` to `esp_wifi` module. In addition, a number of corrections have been made. In the case of documentation, it is impossible to do this in various commits.
