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can stm32: add a driver for STM32 bxCAN peripheral
This driver is compliant with the candev interface. It has been tested with STM32F0 and STM32F2 and STM32F413 ONLY at this time but should be compliant with other STM32Fx devices
This commit is contained in:
Vincent Dupont
parent
14f47bf220
commit
ae95137f95
138
cpu/stm32_common/include/can_params.h
Normal file
138
cpu/stm32_common/include/can_params.h
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@ -0,0 +1,138 @@
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/*
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* Copyright (C) 2016 OTA keys S.A.
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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/**
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* @ingroup candev_stm32
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* @{
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*
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* @file
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* @brief STM32 CAN controller driver (bxCAN) default parameters
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*
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* @author Vincent Dupont <vincent@otakeys.com>
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* @}
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*/
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#ifndef CANDEV_STM32_PARAMS_H
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#define CANDEV_STM32_PARAMS_H
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#include "can/device.h"
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#include "periph/can.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** Default STM32 CAN devices config */
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static const can_conf_t candev_conf[] = {
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{
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#if defined(CPU_FAM_STM32F0)
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.can = CAN,
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.rcc_mask = RCC_APB1ENR_CANEN,
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.rx_pin = GPIO_PIN(PORT_A, 11),
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.tx_pin = GPIO_PIN(PORT_A, 12),
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.af = GPIO_AF4,
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.irqn = CEC_CAN_IRQn,
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#else
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.can = CAN1,
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.rcc_mask = RCC_APB1ENR_CAN1EN,
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.can_master = CAN1,
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.master_rcc_mask = RCC_APB1ENR_CAN1EN,
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.first_filter = 0,
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.nb_filters = 14,
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#ifndef CPU_FAM_STM32F1
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.rx_pin = GPIO_PIN(PORT_D, 0),
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.tx_pin = GPIO_PIN(PORT_D, 1),
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.af = GPIO_AF9,
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#else
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.rx_pin = GPIO_PIN(PORT_A, 11),
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.tx_pin = GPIO_PIN(PORT_A, 12),
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#endif
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.tx_irqn = CAN1_TX_IRQn,
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.rx0_irqn = CAN1_RX0_IRQn,
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.rx1_irqn = CAN1_RX1_IRQn,
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.sce_irqn = CAN1_SCE_IRQn,
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#endif
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.ttcm = 0,
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.abom = 1,
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.awum = 1,
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.nart = 0,
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.rflm = 0,
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.txfp = 0,
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},
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#if (CANDEV_STM32_CHAN_NUMOF >= 2) && (CAN_DLL_NUMOF >= 2)
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{
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.can = CAN2,
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.rcc_mask = RCC_APB1ENR_CAN2EN,
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.can_master = CAN1,
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.master_rcc_mask = RCC_APB1ENR_CAN1EN,
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.first_filter = 14,
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.nb_filters = 14,
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.rx_pin = GPIO_PIN(PORT_B, 5),
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.tx_pin = GPIO_PIN(PORT_B, 6),
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#ifndef CPU_FAM_STM32F1
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.af = GPIO_AF9,
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#endif
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.tx_irqn = CAN2_TX_IRQn,
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.rx0_irqn = CAN2_RX0_IRQn,
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.rx1_irqn = CAN2_RX1_IRQn,
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.sce_irqn = CAN2_SCE_IRQn,
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.ttcm = 0,
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.abom = 1,
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.awum = 1,
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.nart = 0,
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.rflm = 0,
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.txfp = 0,
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},
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#endif
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#if (CANDEV_STM32_CHAN_NUMOF >= 3) && (CAN_DLL_NUMOF >= 3)
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{
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.can = CAN3,
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.rcc_mask = RCC_APB1ENR_CAN3EN,
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.can_master = CAN3,
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.master_rcc_mask = RCC_APB1ENR_CAN3EN,
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.first_filter = 0,
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.nb_filters = 14,
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.rx_pin = GPIO_PIN(PORT_B, 3),
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.tx_pin = GPIO_PIN(PORT_B, 4),
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.af = GPIO_AF11,
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.tx_irqn = CAN3_TX_IRQn,
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.rx0_irqn = CAN3_RX0_IRQn,
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.rx1_irqn = CAN3_RX1_IRQn,
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.sce_irqn = CAN3_SCE_IRQn,
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.ttcm = 0,
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.abom = 1,
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.awum = 1,
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.nart = 0,
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.rflm = 0,
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.txfp = 0,
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},
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#endif
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};
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/** Default STM32 CAN devices parameters */
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static const candev_params_t candev_params[] = {
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{
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.name = "can_stm32_0",
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},
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#if (CANDEV_STM32_CHAN_NUMOF >= 2) && (CAN_DLL_NUMOF >= 2)
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{
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.name = "can_stm32_1",
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},
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#endif
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#if (CANDEV_STM32_CHAN_NUMOF >= 3) && (CAN_DLL_NUMOF >= 3)
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{
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.name = "can_stm32_2",
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},
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#endif
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};
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#ifdef __cplusplus
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}
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#endif
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#endif /* CANDEV_STM32_PARAMS_H */
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193
cpu/stm32_common/include/candev_stm32.h
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193
cpu/stm32_common/include/candev_stm32.h
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@ -0,0 +1,193 @@
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/*
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* Copyright (C) 2016 OTA keys S.A.
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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/**
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* @ingroup cpu_stm32_common
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* @ingroup drivers_can
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* @defgroup candev_stm32 STM32 CAN controller
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* @brief STM32 CAN controller driver (bxCAN)
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*
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* The STM32Fx microcontroller can have an integrated CAN controller (bxCAN)
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*
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* This driver has been tested with a STM32F0,STM32F2 and STM32F4 MCU
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* but should work on others
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* @{
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*
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* @file
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* @brief bxCAN specific definitions
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*
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* @author Vincent Dupont <vincent@otakeys.com>
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* @}
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*/
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#ifndef CANDEV_STM32_H
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#define CANDEV_STM32_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include "can/candev.h"
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#if defined(CPU_LINE_STM32F413xx) || defined(CPU_LINE_STM32F423xx)
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#define CANDEV_STM32_CHAN_NUMOF 3
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#elif defined(CPU_FAM_STM32F1) || defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4)
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#define CANDEV_STM32_CHAN_NUMOF 2
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#elif defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F3) || DOXYGEN
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/** Number of channels in the device (up to 3) */
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#define CANDEV_STM32_CHAN_NUMOF 1
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#else
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#error "CAN STM32: CPU not supported"
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#endif
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#if defined(CPU_FAM_STM32F1)
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#define ISR_CAN1_TX isr_usb_hp_can1_tx
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#define ISR_CAN1_RX0 isr_usb_lp_can1_rx0
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#define ISR_CAN1_RX1 isr_can1_rx1
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#define ISR_CAN1_SCE isr_can1_sce
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#else
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#define ISR_CAN1_TX isr_can1_tx
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#define ISR_CAN1_RX0 isr_can1_rx0
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#define ISR_CAN1_RX1 isr_can1_rx1
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#define ISR_CAN1_SCE isr_can1_sce
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#define ISR_CAN2_TX isr_can2_tx
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#define ISR_CAN2_RX0 isr_can2_rx0
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#define ISR_CAN2_RX1 isr_can2_rx1
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#define ISR_CAN2_SCE isr_can2_sce
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#define ISR_CAN3_TX isr_can3_tx
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#define ISR_CAN3_RX0 isr_can3_rx0
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#define ISR_CAN3_RX1 isr_can3_rx1
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#define ISR_CAN3_SCE isr_can3_sce
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#endif
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#if CANDEV_STM32_CHAN_NUMOF > 1 || DOXYGEN
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/** The maximum number of filters: 28 for dual channel, 14 for single channel */
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#define CAN_STM32_NB_FILTER 28
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#else
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#define CAN_STM32_NB_FILTER 14
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#endif
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#ifndef CANDEV_STM32_DEFAULT_BITRATE
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/** Default bitrate */
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#define CANDEV_STM32_DEFAULT_BITRATE 500000U
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#endif
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#ifndef CANDEV_STM32_DEFAULT_SPT
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/** Default sampling-point */
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#define CANDEV_STM32_DEFAULT_SPT 875
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#endif
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/** bxCAN device configuration */
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typedef struct {
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CAN_TypeDef *can; /**< CAN device */
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uint32_t rcc_mask; /**< RCC mask to enable clock */
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gpio_t rx_pin; /**< RX pin */
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gpio_t tx_pin; /**< TX pin */
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#ifndef CPU_FAM_STM32F1
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gpio_af_t af; /**< Alternate pin function to use */
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#endif
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#if CANDEV_STM32_CHAN_NUMOF > 1 || defined(DOXYGEN)
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CAN_TypeDef *can_master; /**< Master CAN device */
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uint32_t master_rcc_mask; /**< Master device RCC mask */
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/** First filter in the bank. For a master channel it must be 0.
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* For a slave channel, it is used without checking with the master channel,
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* beware bot to overwrite the master config. */
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uint8_t first_filter;
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/** Number of filters to use. Must be less or equal
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* to CAN_STM32_NB_FILTER - first_filter */
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uint8_t nb_filters;
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#endif
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#if defined(CPU_FAM_STM32F0)
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uint8_t irqn; /**< CAN common IRQ channel */
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#else
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uint8_t tx_irqn; /**< TX IRQ channel */
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uint8_t rx0_irqn; /**< RX0 IRQ channel */
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uint8_t rx1_irqn; /**< RX1 IRQ channel */
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uint8_t sce_irqn; /**< SCE IRQ channel */
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#endif
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uint8_t ttcm : 1; /**< Time triggered communication mode */
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uint8_t abom : 1; /**< Automatic bus-off management */
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uint8_t awum : 1; /**< Automatic wakeup mode */
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uint8_t nart : 1; /**< No automatic retransmission */
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uint8_t rflm : 1; /**< Receive FIFO locked mode */
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uint8_t txfp : 1; /**< Transmit FIFO priority */
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uint8_t lbkm : 1; /**< Loopback mode */
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uint8_t silm : 1; /**< Silent mode */
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} can_conf_t;
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#define HAVE_CAN_CONF_T
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/** The number of transmit mailboxes */
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#define CAN_STM32_TX_MAILBOXES 3
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/** The number of receive FIFO */
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#define CAN_STM32_RX_MAILBOXES 2
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#ifndef CAN_STM32_RX_MAIL_FIFO
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/** This is the maximum number of frame the driver can receive simultaneously */
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#define CAN_STM32_RX_MAIL_FIFO 12
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#endif
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/** bxCAN candev descriptor */
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typedef struct can can_t;
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#define HAVE_CAN_T
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/** This structure holds anything related to the receive part */
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typedef struct candev_stm32_rx_fifo {
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struct can_frame frame[CAN_STM32_RX_MAIL_FIFO]; /**< Receive FIFO */
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int write_idx; /**< Write index in the receive FIFO */
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int read_idx; /**< Read index in the receive FIFO*/
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int is_full; /**< Flag set when the FIFO is full */
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} candev_stm32_rx_fifo_t;
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/** Internal interrupt flags */
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typedef struct candev_stm32_isr {
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int isr_tx : 3; /**< Tx mailboxes interrupt */
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int isr_rx : 2; /**< Rx FIFO interrupt */
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int isr_wkup : 1; /**< Wake up interrupt */
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} candev_stm32_isr_t;
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/** STM32 CAN device descriptor */
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struct can {
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candev_t candev; /**< Common candev struct */
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const can_conf_t *conf; /**< Configuration */
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gpio_t rx_pin; /**< RX pin */
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gpio_t tx_pin; /**< TX pin */
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gpio_af_t af; /**< Alternate pin function to use */
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/** Tx mailboxes */
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const struct can_frame *tx_mailbox[CAN_STM32_TX_MAILBOXES];
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candev_stm32_rx_fifo_t rx_fifo; /**< Rx FIFOs */
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candev_stm32_isr_t isr_flags; /**< ISR flags */
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};
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#ifndef CPU_FAM_STM32F1
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/**
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* @brief Set the pins of an stm32 CAN device
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*
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* @param[in,out] dev the device to set pins
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* @param[in] tx_pin tx pin
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* @param[in] rx_pin rx pin
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* @param[in] af alternate function
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*/
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void candev_stm32_set_pins(can_t *dev, gpio_t tx_pin, gpio_t rx_pin,
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gpio_af_t af);
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#else
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/**
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* @brief Set the pins of an stm32 CAN device
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*
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* @param[in,out] dev the device to set pins
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* @param[in] tx_pin tx pin
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* @param[in] rx_pin rx pin
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*/
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void candev_stm32_set_pins(can_t *dev, gpio_t tx_pin, gpio_t rx_pin);
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#endif
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#ifdef __cplusplus
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}
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#endif
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#endif /* CANDEV_STM32_H */
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@ -704,6 +704,10 @@ int dma_configure(dma_t dma, int chan, const volatile void *src, volatile void *
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#endif /* MODULE_PERIPH_DMA */
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#ifdef MODULE_PERIPH_CAN
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#include "candev_stm32.h"
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#endif
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#ifdef __cplusplus
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}
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#endif
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1263
cpu/stm32_common/periph/can.c
Normal file
1263
cpu/stm32_common/periph/can.c
Normal file
File diff suppressed because it is too large
Load Diff
57
drivers/include/periph/can.h
Normal file
57
drivers/include/periph/can.h
Normal file
@ -0,0 +1,57 @@
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/*
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* Copyright (C) 2018 OTA keys S.A.
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @defgroup drivers_periph_can CAN
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* @ingroup drivers_periph
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* @brief Low-level CAN peripheral driver interface
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*
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* This is a basic abstract peripheral to be used with candev.
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*
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* The @p can_t type should be compatible with @p candev_t to be used by the
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* candev interface.
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*
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* See auto init for more details how the can_t is used.
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*
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* @{
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*
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* @file
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* @brief Low-level CAN peripheral driver interface definitions
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*
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* @author Vincent Dupont <vincent@otakeys.com>
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*/
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#ifndef PERIPH_CAN_H
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#define PERIPH_CAN_H
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#include "periph_cpu.h"
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#include "can/candev.h"
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#ifndef HAVE_CAN_T
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/**
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* @brief CAN device descriptor identifier
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*/
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typedef candev_t can_t;
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#endif
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#ifndef HAVE_CAN_CONF_T
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/**
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* @brief CAN configuration identifier
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*/
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typedef void can_conf_t;
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#endif
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/**
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* @brief Initialize a periph CAN device with the given configuration
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*
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* @param[in,out] dev device descriptor
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* @param[in] conf device vonfiguration
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*/
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void can_init(can_t *dev, const can_conf_t *conf);
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#endif /* PERIPH_CAN_H */
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@ -54,8 +54,18 @@ void auto_init_candev(void)
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auto_init_can_native();
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#endif
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#ifdef MODULE_PERIPH_CAN
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extern void auto_init_periph_can(void);
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auto_init_periph_can();
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#endif
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#ifdef MODULE_ESP_CAN
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extern void auto_init_esp_can(void);
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auto_init_esp_can();
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#endif
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#ifdef MODULE_CAN_STM32
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extern void auto_init_can_stm32(void);
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auto_init_can_stm32();
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#endif
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}
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57
sys/auto_init/can/auto_init_periph_can.c
Normal file
57
sys/auto_init/can/auto_init_periph_can.c
Normal file
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/*
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* Copyright (C) 2016-2018 OTA keys S.A.
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*
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* This file is subject to the terms and conditions of the GNU Lesser
|
||||
* General Public License v2.1. See the file LICENSE in the top level
|
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* directory for more details.
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*/
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/**
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* @ingroup auto_init
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* @{
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* @file
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* @brief initializes periph_can devices
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*
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* @author Vincent Dupont <vincent@otakeys.com>
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* @}
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*/
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#ifdef MODULE_PERIPH_CAN
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#include "can/device.h"
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#include "can_params.h"
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||||
#define CANDEV_NUMOF ((sizeof(candev_params) / sizeof(candev_params[0])))
|
||||
|
||||
#ifndef CANDEV_STACKSIZE
|
||||
#define CANDEV_STACKSIZE (THREAD_STACKSIZE_DEFAULT + THREAD_EXTRA_STACKSIZE_PRINTF)
|
||||
#endif
|
||||
|
||||
#ifndef CANDEV_BASE_PRIORITY
|
||||
#define CANDEV_BASE_PRIORITY (THREAD_PRIORITY_MAIN - CANDEV_NUMOF - 2)
|
||||
#endif
|
||||
|
||||
static candev_dev_t candev_dev[CANDEV_NUMOF];
|
||||
static char _can_stacks[CANDEV_NUMOF][CANDEV_STACKSIZE];
|
||||
static can_t candev[CANDEV_NUMOF];
|
||||
|
||||
void auto_init_periph_can(void) {
|
||||
|
||||
for (size_t i = 0; i < CANDEV_NUMOF; i++) {
|
||||
can_init(&candev[i], &candev_conf[i]);
|
||||
candev_dev[i].dev = (candev_t *)&candev[i];
|
||||
candev_dev[i].name = candev_params[i].name;
|
||||
#ifdef MODULE_CAN_TRX
|
||||
candev_dev[i].trx = candev_params[i].trx;
|
||||
#endif
|
||||
#ifdef MODULE_CAN_PM
|
||||
candev_dev[i].rx_inactivity_timeout = candev_params[i].rx_inactivity_timeout;
|
||||
candev_dev[i].tx_wakeup_timeout = candev_params[i].tx_wakeup_timeout;
|
||||
#endif
|
||||
|
||||
can_device_init(_can_stacks[i], CANDEV_STACKSIZE, CANDEV_BASE_PRIORITY + i,
|
||||
candev_params[i].name, &candev_dev[i]);
|
||||
}
|
||||
}
|
||||
#else
|
||||
typedef int dont_be_pedantic;
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user