stm32eth: Move to stm32_common periph
cpu/stm32_periph_eth: Rebase to current master branch
- Update DMA to use new vendor headers
- Update send to use iolist. It looks like the packet headers are now transfered as seperate iolist entries which results in the eth periph sending each header as own packet. To fix this a rather ugly workaround is used where the whole iolist content is first copied to a static buffer. This will be fixed soon in another commit
- If MAC is set to zero use luid to generate one
- Small code style fixes
cpu/stm312f7: Add periph config for on-board ethernet
boards/nucleo-f767zi: Add config for on board ethernet
tests/stm32_eth_lwip: Remove board restriction
boards/common/nucleo: Add luid module if stm32 ethernet is used
tests/stm32_eth_gnrc: Add Testcase for gnrc using the stm32 eth periph
stm32_eth: Rework netdev driver layour
tests/stm32_eth_*: Use netdev driver header file for prototypes
stm32_eth: Add auto init for stm32 eth netdev driver
boards/stm32: Enable ethernet conf for nucleo boards
stm32_eth_auto_init: Add dont be pendantic flag
stm32_eth: Remove dma specific stuff from periph_cpu.h
Looks like this was implemented in PR #9171 and 021697ae94 with the same interface.
stm32_eth: Remove eth feature from stm32f4discovery boards
stm32_eth: Migrate to stm32 DMA API
stm32_eth: Add iolist to module deps
stm32_eth: Rework send function to use iolist
stm32_eth: Fix ci build warnings
stm32_eth: Fix bug introduced with iolist usage
stm32_eth: Remove redundant static buffer
stm32_eth: Fix feature dependencies
stm32_eth: Fix wrong header guard name
stm32_eth: Implement correct l2 netstats interface
stm32_eth: Rename public functions to stm32_eth_*
stm32_eth: Fix doccheck
stm32_eth: Move register DEFINE to appropriate header file
stm32_eth: remove untested configuration for f446ze boards
stm32_eth: Move periph configuration struct to stm32_common
stm32_eth: Fix naming of eth_phy_read and eth_phy_write
stm32_eth: Remove obsolete test applications
- EOP bit is cleared by writing 1 to the register.
- Guard EOP bit clear for STM32F2, STM32F4, STM32F7
and STM32L4 EOP bit is only set if EOPIE is enabled.
Since this is not the case for any platform we exclude
it when not needed.
- With this PR, On start up all GPIOs are configured as AIN. For stm32l0/4
this is done by default. Doing this saves the consumption of the input Schmitt
trigger in STOP mode which can reduce the consumption in at least 70%
from current master.
- The PNB in FLASH_CR wasn't cleared before every erase operation
and the new value was just stacked on top. After a couple of erase
the PNB written was overlapping with old ones failing to erase the
correct page.
This commit fixes the clearing of a error condition after read.
This causes the incorrect errorcodes if the register is read
then an error occurs, then it is cleared.
By clearing only after the error is processed the bug is fixed.
This can be tested by reading a i2c slave that is not there.
- Before, HSI was enabled as the default case when it is only
used for stm32f0 and stm32f1. It is now implemented explicitly
for those platforms, and only those.
Rational: the periph_common module is required by (most) other periph drivers
and also during startup of the CPU/MCU to run periph_init. The latter is only
required if other periph drivers are used, hence periph_common should be a
depency of periph_* modules and *not* of the CPU/MCU. This PR fixes that
by making periph_common a depency of periph_* and removing the explicit
include in the CPU/MCU implementation.
This driver is compliant with the candev interface. It has been tested
with STM32F0 and STM32F2 and STM32F413 ONLY at this time but should be
compliant with other STM32Fx devices
There is an error when the start byte NACKs
The nack sets the stop bit twice which keeps the stop bit high the next time
When the stop bit is high it creates a timeout when trying to use
This commit fixes so when a NACK occures on the address it doesn't stop twice
USART_CR1_M combines both USART_CR1_M0 and USART_CR1_M1 macros
affecting bits 12 and 28 on 7 data bits capable UARTs. Whereas
for other UARTs USART_CR1_M macro affects only bit 12.
This patch fixes wrong data bits usage on 7 data bits capable
UARTs with using USART_CR1_M0 macro for modes 8-E-x and 8-O-x.
It also simplifies bits unsetting as USART_CR1_M macro clears
all data bits related bits for both UART types.
Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
Add support for specifying data bits, stop bits and parity at
runtime.
Introduce feature periph_uart_modecfg for uart_mode() till all
other CPUs implement it.
STM32 L1, F1, F2, F4 supports following modes:
* 7E1, 7E2
* 7O1, 7O2
* 8N1, 8N2
* 8E1, 8E2
* 8O1, 8O2
STM32 L0, L4, F0, F3, F7 supports following modes:
* 6E1, 6E2
* 6O1, 6O2
* 7E1, 7E2
* 7O1, 7O2
* 7N1, 7N2
* 8N1, 8N2
* 8E1, 8E2
* 8O1, 8O2
Use USART_CR1_M1 macro to detect 7-bit support because
even inside one family there could be devices that don't
support 7-bit mode. So just using a family macro is not
enough.
As stated in the datasheets for L0, L4, F0, F3, F7 devices,
data bits can only be changed when UART is disabled (UE=0).
Introduce uart_stop() routine to satisfy this requirement.
STM32 UART adds parity to the MSB of a byte to send. The same
also applies to the received bytes. As a result this bit must
be masked in order to get the pure data.
Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
Refactors i2c_2 to match the structure of i2c_1 better.
Corrects functionality issues.
Allows the common implementation of read_regs and write_regs.
Documents constraints of hardware.
Matches error messages with API.
Due to the stdio getting called after periph_init the uart may send before initialized.
This adds a simple check so the uart does not get into a locked-up state.
This commit fixes configuration problems when trying to use i2c pins that need to be remapped.
All B8 and B9 pins for STM32F1 need to be remapped, so a check is done if the remappable pins are selected.
Errors flags could not clear making the i2c unusable after error.
This fix removes the error check in start so the error flags can clear and does proper checking for status bits before _bus_check.
The `periph_flash_common` feature was only defined here to trigger
inclusion of a source file with common functions.
It even only defines private symbols `_lock` and `_unlock` so no reason
to expose it to the build system.
And in practice, all stm cpus providing `periph_flashpage` or
`periph_eeprom` were required to provide `periph_flash_common` to allow
including it.
The previous implementation was only parsing in the modules were in
`FEATURES_REQUIRED` wich did not take cases of `FEATURES_OPTIONAL` into
account.
And also, in the same time, as the dependencies was declared in
`Makefile.include` it was processed before `Makefile.dep` so never handled
cases where a module could depend on `periph_flashpage` or
`periph_eeprom` feature.
It is replaced by selecting the common source file when module using it
are included.
The now useless feature `periph_flash_common` is removed from
`FEATURES_PROVIDED`.
`cpu/stm32_common/Makefile.dep` was never included by the global
`Makefile.dep`, so declaring this `USEMODULE +=` here was never shown to
the build system and never exported as `MODULE_PERIPH_I2C_X` variables.
In fact, `USEMODULE` was only used to trigger the `periph.mk`/`SUBMODULES`
mechanism to add matching source files names to `SRC` and so select
the implementation for each CPU type.
It is replaced by just explicitly selecting the right source file.
- dont send stop if bus is busy and before any action is done on bus
- and bus check that looks for bus error, arbitration and nack events
- check for ACK (TXIS) before writing bytes on bus and not between each write
Moving the while loop in a separate function ensures no ordering
optimizations is applied silently by gcc.
This commit fixes the flashpage not working on iotlab-m3.
