Fixes this error with binutils 2.37:
```
/usr/lib/gcc/arm-none-eabi/11.2.0/../../../../arm-none-eabi/bin/ld:cortexm_base.ld:217: warning: memory region `bkup' not declared
/usr/lib/gcc/arm-none-eabi/11.2.0/../../../../arm-none-eabi/bin/ld:cortexm_base.ld:217: syntax error
```
The global core/ldscripts/xfa.ld doesn't match our cortexm_base.ld.
This commit directly adds the two XFA lines to cortexm_base.ld.
In addition to that, a dummy (empty) xfa.ld is added, which the linker will pick
instead of core/ldscripts/xfa.ld, effectingly not using it.
The bit access functions are not tied to Cortex-M CPUs, here they only
provide optimisations via bit-banding.
But the functions are generally useful - so move them to an arch independent
location.
When enabling & disabling interrupts back-to-back pending interrupts
are not serviced on Cortex-M23/M33.
Flush the pipeline to give interrupts a chance of executing in `sched_arch_idle()`.
This fixes `no_idle_thread` on Cortex-M23.
Verified that each warning generated by -Wcast-align is indeed a false positive
and used an (intermediate) cast to `uintptr_t` to silence the warnings.
This modifies the cortex-m thread specifics to allow running the PendSV
interrupt continuously at lower priority and removes the priority
modifications during the interrupt itself. Interrupts are disabled
during the scheduling itself, but enabled briefly after the sleep to
ensure that they are handled if activated during the scheduling or the
sleep.
While the hard fault handler prints the offending program counter, it
does not print information about the context triggering the hard fault.
This commit adds a line printing the thread ID and name that triggered
the hard fault. If the hard fault is triggered during an ISR, it only
prints that the hard fault happened during ISR context, not which ISR
triggered it.
In most places, picolibc and newlib are the same, so use
the existing newlib code when compiling with picolibc.
Signed-off-by: Keith Packard <keithp@keithp.com>
Allocate and initialize a thread-local block for each thread at the
top of the stack.
Set the tls base when switching to a new thread.
Add tdata/tbss linker instructions to cortex_m and risc-v scripts.
Signed-off-by: Keith Packard <keithp@keithp.com>
---
v2:
Squash fixes
v3:
Replace tabs with spaces
v4:
Add tbss to fe310 linker script
Support for picolibc as alternative libc implementation is added with
this commit. For now only cortex-m CPU's are supported.
Enable via PICOLIBC=1
---
v2:
squash fixes in
v3:
Remove picolibc integer printf/scanf stuff from sys/Makefile.include,
it gets set in makefiles/libc/picolibc.mk
fixup for dependency
The PendSV interrupt is used to request a scheduling operation. An
interrupt during the idle sleep can re-request the PendSV interrupt,
while the PendSV is still busy scheduling the next thread. This clears
the request after sleep to prevent triggering an extra PendSV interrupt
after the current PendSV handler finished.
Not all MCUs ≥ Cortex-M3 provide the Bit-Banding feature.
It is up to the manufacturer to implement it.
Instead, rely on the CPU_HAS_BITBAND being set in `periph_cpu.h`.
A race condition is present where an IRQ is serviced between the
priority increase of the PENDSV and the sleep. When the IRQ
is serviced before the WFI sleep, the core will sleep until the next
IRQ and the thread activated by the IRQ will not be scheduled until
a new IRQ triggers.
This commit wraps an IRQ disable and restore around the priority
modification and sleep to prevent interrupts from being serviced until
the WFI call returns.
- Add libstdcpp feature to indicate a platform is providing a libstdc++
implementation ready for use
- The existing cpp feature now only indicates a working C++ toolchain without
libstdc++. (E.g. still useful for the Arduino compatibility layer.)
- Added libstdcpp as required feature were needed
- Added some documentation on C++ on RIOT
The `ldr r1, =sched_active_thread` instruction couldn't be assembled with
LTO, as the no immediate offset could be found to construct the address of
`sched_active_thread`. This commit instructs the assembler to generate a
literate pool which can be used to construct the address. While this issue
was only triggered during LTO, it theoretically could also pop up without LTO
due to unrelated changes. Thus, it is a good idea to create the literate pool
even without LTO enabled.
- Use `irq_enable()` over `bl irq_enable`, as `irq_enable()` is an inline
function and not a C function any more
- Drop `__attribute__((naked))` qualifier
- It must be used with the declaration of the function, but there it is
missing. (And it cannot be added there, as this function would need to
be implemented as "naked" by every platform; which is impossible for
platforms not supporting `__attribute__((naked))`.)
- Only functions consisting completely of basic asm may be marked as naked.
But both the assembly used to trigger the SVC interrupt as well as the
assembly used in `irq_enable()` are extended asm, not basic asm
- Use ` UNREACHABLE();` over a custom asm construct
All bits in the ICSR register in the cortexm system control block are
either read-only or don't have an effect when writing a zero. A
read-modify-write cycle is thus not required when writing bit flags in
the register. This commit removes the reads in the read-modify-store
patterns for this register.
__set_PRIMASK(state) had been directly inlined to avoid a hardfault that
occured when branching after waking up from sleep with DBG_STANDBY,
DBG_STOP or DBG_SLEEP set in DBG_CR.
The hardfault occured when returning from the branch to irq_restore,
since the function is now inlined the branch does not happen either.
Refer to #14015 for more details.
irq_% are not inlined by the compiler which leads to it branching
to a function that actually implement a single machine instruction.
Inlining these functions makes the call more efficient as well as
saving some bytes in ROM.
The ARM CortexM vector table has some reserved fields which are used by
some manufacturers to store their custom image information. In
particular, NXP QN908X stores the checksum, Code Read Protection, image
type and boot block pointer in this region.
This patch allows the cpu and board modules to define the value of these
fields at build time by defining a macro.
This commit enables Cortex-M CPU interrupt sub-priorities
and allows the PendSV interrupt to have a priority different
from the default one. Together these two preprocessor
defines can be used to have PendSV always run as the last interrupt
before returning from the interrupt stack back to the user space.
Running PendSV as the last interrupt before returning to the
user space is recommended by ARM, as it increases efficiency.
Furthermore, that change enhances stability a lot with the
new nRF52 SoftDevice support, currently being worked in
PR #9473.
This commit merely enables sub-priorities and a separate
PendSV priority to be used without changing the default
RIOT behaviour.
This adds cortexm_fpu to the DEFAULT_MODULE list when the feature
cortexm_fpu is provided by the architecture. It also moves the
dependency resolution of this module to the architecture-specific
Makefile.dep file.
This moves the following modules to a architecture-specific Makefile.dep
file:
- cortexm_common
- cortexm_common_periph
- newlib
- newlib_nano
- periph
From the ARMv7-M ARM section B3.5.3:
Where there is an overlap between two regions, the register with
the highest region number takes priority.
We want to make sure the mpu_noexec_ram region has the lowest
priority to allow the mpu_stack_guard region to overwrite the first N
bytes of it.
This change fixes using mpu_noexec_ram and mpu_stack_guard together.
