Since https://github.com/RIOT-OS/RIOT/pull/20935 gpio_write()
uses a `bool` instead of an `int`. This does the same treatment for
`gpio_read()`.
This does indeed add an instruction to `gpio_read()` implementations.
However, users caring about an instruction more are better served with
`gpio_ll_read()` anyway. And `gpio_read() == 1` is often seen in
newcomer's code, which would now work as expected.
The current ISR implementation for AVR8 requires use of
avr8_[enter/exit]_isr pair which add some boilerplate on code.
This add AVR8_ISR which clean-up the code and make it simpler
and hides any schedule detail from the user perspective.
This is a preparation for future scheduling and irq optimizations.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
The avr8_state store state information used to determine scheduling
and uart irq. This move all uart irq states to avr8_state_uart
variable. It introduce the use of General Purpose IO Register 0
(GPIOR0) when available and now all uarts from xmega can be used.
This is a preparation for future scheduling and irq optimizations.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Due to the lack of new official avr-libc releases (which includes the
vendor header files needed to support different version of MCUs),
support for new MCUs was lacking. Distributions such as Debian addressed
this by extending the upstream code with vendor header files directly
obtained from Atmel / Microchip, but without paying attention to
details. As such, a naming inconsistency (ASIZE vs ASPACE) between
officially supported MCUs and new MCUs was introduced.
Now that avr-libc 2.1.0 is officially released, hardware support for new
MCUs is provided by upstream out of the box and only ASIZE is used as
name. This commit adds a bit of glue code to create aliases for ASIZE on
older avr-libc versions where needed. This fixes compilation with the
new avr-libc release and results in more consistent code.
Our AVR port doesn't make use of an ISR stack and just victimizes the
stack of whatever thread happens to be running, which in most cases is
the idle thread. Hence, the idle stack has to be large enough to
support the ztimer ISR.
This introduces KCONFIG_BOARD_CONFIG and KCONFIG_CPU_CONFIG variable for
boards and CPUs (including common directories) to add default
configuration files to be merged. The current approach, as it uses
Makefile.features, would include boards first, not allowing them to
override CPU configurations.
The xfa.ld script is incompatible with binutils > 2.35.2 and results
in firmwares that wont boot. Sadly, I couldn't figure out an elegant
way to fix the issue. Instead, I modified the linker script provided
by binutils to also include XFA.
core_panic() doesn't expect the message to be in program memory, but
in data memory. Bad things will happen on AVR when the address is
interpreted as being in data address space, but the allocation is
done in program address space.
Introduce XMEGA EBI driver. This enable EBI for use with all memory
supported by the device and peripherals. It include support to SRAM,
SDRAM, LCDs or any other external bus access.
Note: This feature only works for A1/A1U series, which are, the series
with EBI hardware.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Update features definitions and configurations. Now atxmega define
features that only are full available on all variations and do not
require any definition at periph_conf.h file.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
The current xmega don't have a way to disable peripherals that are
not in used. Add peripheral management to allow enable only the mcu
blocks that will be used by application. This saves power on active
and sleep modes. By default, at clock initialization, all peripherals
are now disabled and each drive must activate at initialization phase.
The periph_timer and periph_uart were updated with this new feature.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
The current ATxmega clock_init enable DFLL to improve the accuracy of
the 2MHz and 32MHz internal oscillators. In some ATxmega revisions,
after started DFLL the clock become unstable. Add another sync point
for 32MHz internal oscilator.
Note: If clock is not stable, system won't switch from 2MHz to 32MHz
as main clock.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Current there is no way to split code between ATmega and ATxmega in
drivers. This differentiate AVR8 cores into MEGAs and XMEGAs.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Add ATxmega common files and cpu definitions.
This works was originally developed by @Josar. The 2018 version
were port to 2021 mainline.
This version changes original port to have only the atxmega CPU
definition. With that, all family can be accomodated.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
