RIOT-OS/RIOT
RIOT-OS/RIOT
1
0
Fork 0
mirror of https://github.com/RIOT-OS/RIOT.git synced 2024-12-29 04:50:03 +01:00
Code Releases Activity

cpu/atxmega: fix building with avr-libc 2.1.0

Browse Source 
Due to the lack of new official avr-libc releases (which includes the
vendor header files needed to support different version of MCUs),
support for new MCUs was lacking. Distributions such as Debian addressed
this by extending the upstream code with vendor header files directly
obtained from Atmel / Microchip, but without paying attention to
details. As such, a naming inconsistency (ASIZE vs ASPACE) between
officially supported MCUs and new MCUs was introduced.

Now that avr-libc 2.1.0 is officially released, hardware support for new
MCUs is provided by upstream out of the box and only ASIZE is used as
name. This commit adds a bit of glue code to create aliases for ASIZE on
older avr-libc versions where needed. This fixes compilation with the
new avr-libc release and results in more consistent code.
This commit is contained in:
Marian Buschsieweke 2022-09-22 13:42:44 +02:00
parent cbee5f4b96
commit 023b6ae7cf
No known key found for this signature in database
GPG Key ID: CB8E3238CE715A94
2 changed files with 28 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
boards/atxmega-a1u-xpro/include/periph_conf.h
View File

@ -155,7 +155,7 @@ static const ebi_conf_t ebi_config = {
0x0UL,
}, /* CS2 - 256K SRAM */
{ EBI_CS_MODE_LPC_gc,
EBI_CS_ASPACE_256KB_gc,
EBI_CS_ASIZE_256KB_gc,
EBI_CS_SRWS_1CLK_gc,
0x0UL,
}, /* Reserved LCD */

34
cpu/atxmega/include/periph_cpu.h
View File

@ -415,16 +415,36 @@ typedef enum {
*/
#define PERIPH_EBI_SDRAM_CS (3)
/* for compatibility between different versions of AVR libc: Legacy versions
* occasionally use ASPACE instead of ASIZE for some MCUs, while new AVR libc
* uses ASIZE as name consistently */
#ifdef EBI_CS_ASPACE_gm
typedef EBI_CS_ASPACE_t EBI_CS_ASIZE_t;
#define EBI_CS_ASIZE_256B_gc EBI_CS_ASPACE_256B_gc
#define EBI_CS_ASIZE_512B_gc EBI_CS_ASPACE_512B_gc
#define EBI_CS_ASIZE_1KB_gc EBI_CS_ASPACE_1KB_gc
#define EBI_CS_ASIZE_2KB_gc EBI_CS_ASPACE_2KB_gc
#define EBI_CS_ASIZE_4KB_gc EBI_CS_ASPACE_4KB_gc
#define EBI_CS_ASIZE_8KB_gc EBI_CS_ASPACE_8KB_gc
#define EBI_CS_ASIZE_16KB_gc EBI_CS_ASPACE_16KB_gc
#define EBI_CS_ASIZE_32KB_gc EBI_CS_ASPACE_32KB_gc
#define EBI_CS_ASIZE_64KB_gc EBI_CS_ASPACE_64KB_gc
#define EBI_CS_ASIZE_128KB_gc EBI_CS_ASPACE_128KB_gc
#define EBI_CS_ASIZE_256KB_gc EBI_CS_ASPACE_256KB_gc
#define EBI_CS_ASIZE_512KB_gc EBI_CS_ASPACE_512KB_gc
#define EBI_CS_ASIZE_1MB_gc EBI_CS_ASPACE_1MB_gc
#define EBI_CS_ASIZE_2MB_gc EBI_CS_ASPACE_2MB_gc
#define EBI_CS_ASIZE_4MB_gc EBI_CS_ASPACE_4MB_gc
#define EBI_CS_ASIZE_8MB_gc EBI_CS_ASPACE_8MB_gc
#define EBI_CS_ASIZE_16MB_gc EBI_CS_ASPACE_16MB_gc
#endif
/**
* @brief EBI Chip Select configuration structure
*/
typedef struct {
EBI_CS_MODE_t mode; /**< Chip Select address mode */
#if defined (__AVR_ATxmega64A1U__) || defined (__AVR_ATxmega128A1U__)
EBI_CS_ASPACE_t space; /**< Chip Select address space */
#else
EBI_CS_ASIZE_t space; /**< Chip Select address space */
#endif
EBI_CS_SRWS_t wait; /**< SRAM Wait State Selection */
uint32_t address; /**< Chip Select Base Address */
} ebi_cs_t;
@ -508,7 +528,7 @@ typedef struct {
* 0x0UL,
* },
* { EBI_CS_MODE_LPC_gc,
* EBI_CS_ASPACE_256KB_gc,
* EBI_CS_ASIZE_256KB_gc,
* EBI_CS_SRWS_1CLK_gc,
* 0x0UL,
* },
@ -542,12 +562,12 @@ typedef struct {
* 0x0UL,
* },
* { EBI_CS_MODE_LPC_gc,
* EBI_CS_ASPACE_32KB_gc,
* EBI_CS_ASIZE_32KB_gc,
* EBI_CS_SRWS_1CLK_gc,
* 0x0UL,
* },
* { EBI_CS_MODE_LPC_gc,
* EBI_CS_ASPACE_256B_gc,
* EBI_CS_ASIZE_256B_gc,
* EBI_CS_SRWS_5CLK_gc,
* 0x100000UL,
* },