The current xmega don't have a way to disable peripherals that are
not in used. Add peripheral management to allow enable only the mcu
blocks that will be used by application. This saves power on active
and sleep modes. By default, at clock initialization, all peripherals
are now disabled and each drive must activate at initialization phase.
The periph_timer and periph_uart were updated with this new feature.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
The current ATxmega clock_init enable DFLL to improve the accuracy of
the 2MHz and 32MHz internal oscillators. In some ATxmega revisions,
after started DFLL the clock become unstable. Add another sync point
for 32MHz internal oscilator.
Note: If clock is not stable, system won't switch from 2MHz to 32MHz
as main clock.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Fix compilation with module `stm32_eth_link_up` when `stm32_eth_auto`
is not used by relying on the compiler to optimize unused functions
and variables out, rather than using the preprocessor.
- Clear the PTP timer interrupt *after* the user callback is executed
- Otherwise it would be possible that the ISR sets another super
short timeout that triggers during ISR, which also gets cleared
- This is a pretty nasty race condition :-/
- The debug output was a bit too verbose to be generally useful. Some
noise is now silenced unless `DEBUG_VERBOSE` is `#define`d to 1
Atmel AVR-8 CPU was reworked to accomodate variants like ATxmega.
This rename to atmega.inc.mk to avr8.inc.mk to be compliant with
new directory structure.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
ATxmega have many clock options. This introduce clk_init into cpu_init
to allow user select between a default configuration or perform fine
clock tune.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
The XMEGA CPU have a Programmable Multilevel Interrupt Controller.
This enables all three PMIC levels. By default, all interrupts are
preconfigured as LOW Level without Round Robin queue. This works
as any MCU with interrupt enabled.
In order to get benefit from Multilevel Interrupts user need increase
the interrupt level by own.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Current there is no way to split code between ATmega and ATxmega in
drivers. This differentiate AVR8 cores into MEGAs and XMEGAs.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
The current context switch and thread stack init don't have a generic
way to save/restore registers for all AVR-8 variations. This add
defines to check flash/data sizes and rework:
- thread_stack_init
- avr8_context_save
- avr8_context_restore
The new implementation add missing RAMP D/X/Y registers that are used
by XMEGA variations.
The rules to add EIND, RAMP(D,X,Y,Z) register are:
- EIND must be added if device have more than 128k flash. This means,
device can access more than 64k words in flash.
- RAMP D/X/Y must be added if device have or can address more than
64k data.
- RAMPZ must be added if device can address more than 64k bytes of
flash or data.
With above rules there is no necessity to check by device because it is
mandatory the registers for those MCU variations.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Add ATxmega common files and cpu definitions.
This works was originally developed by @Josar. The 2018 version
were port to 2021 mainline.
This version changes original port to have only the atxmega CPU
definition. With that, all family can be accomodated.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Some mega boards enabling global irq at board_init. This moves that
responsability to cpu/avr8_common to create a common point to all
variants.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
The ATxmega can have up to 8 UARTs. This increase from 2 up to 7 to
keep avr8_state flags with 8 bits wide.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Some periph_rtt implementations do not provide `rtt_set_counter()`. This
adds `periph_rtt_set_counter` as feature to allow testing for its
availability. The feature is provided at CPU level if periph_rtt is
provided by the board for all CPUs implementing `rtt_set_counter()`.
Some periph_rtt implementations do not provide `rtt_set_counter()`. This
adds `periph_rtt_set_counter` as feature to allow testing for its
availability. The feature is provided at CPU level if periph_rtt is
provided by the board for all CPUs implementing `rtt_set_counter()`.
Found and fixed the issue for the kinetis-based boards: The kinetis
code is using some macros to map some IRQ names, that differ in
some versions of vendor headers, to a RIOT wide unique name. The
doxygen of this mapping states, that this mapping must be done before
any vendor header is included. Unfortunately, the mapping was so far
placed in cpu/kinetis/vectors.c, before any other include statement.
In some cases, the vendor headers might be included before the
mapping macros in vectors.c, leading to the compilation errors down
the line. To fix this, the adaption defines are moved into
cpu/kinetis/cpu_conf.h, which is the file that actually includes
the vendor headers. This way it is ensured, that these adaption
macros are always defined before any vendor header is included,
and therefore preventing this kind of error for good.
- Adds capabilities for each PHY mode. Converts the uint16_t caps field to an
uint32_t in order to hold all capability bits, size of the structure remains
unchanged due to alignment.
- Modifies the test application to configure the PHY mode using the shell
command. Also adds the PHY modes to the capabilities shell command.
- Updates the nrf802154 and cc2538 radio drivers to specify the PHY mode
supported.
Signed-off-by: Jean Pierre Dudey <me@jeandudey.tech>
If there is an event to be handled by _esp_eth_isr(), don't
overwrite it if a new packet has been received.
In my testing, all SYSTEM_EVENT_ETH_CONNECTED events except the first
are immediately followed by at least one SYSTEM_EVENT_ETH_RX_DONE event.
This causes the SYSTEM_EVENT_ETH_CONNECTED to not get handled, and the
IP stack will not be notified of the new link state.
Protect the other events by dropping the packet instead. If an earlier
unhandled SYSTEM_EVENT_ETH_RX_DONE event exists, overwrite it with the
newer packet.
I only saw this happen with lwIP and not with GNRC - I am not sure why.
But it still is a race waiting to happen. The nice long term solution
is probably to have a queue of unhandled events, allowing them all to
be processed once there is time.
The ADC SYNCBUSY.SWTRIG gets stuck to '1' after wake-up from Standby Sleep mode.
Ignore the ADC `SYNCBUSY.SWTRIG` status bit, this functionality is not used by
the driver anyway.
The global core/ldscripts/xfa.ld doesn't match our cortexm_base.ld.
This commit directly adds the two XFA lines to cortexm_base.ld.
In addition to that, a dummy (empty) xfa.ld is added, which the linker will pick
instead of core/ldscripts/xfa.ld, effectingly not using it.
nRF52833 has POWER_MAINREGSTATUS_MAINREGSTATUS_High, but no POWER->DCDCEN0
register.
This breaks all builds on this MCU.
Fix the ifdef to fix the build.
This allows using the macro inside the periph_conf.h board files since the
periph/gpio.h header can't be included on the peripheral configuration.
Signed-off-by: Jean Pierre Dudey <me@jeandudey.tech>
Deep-sleep was based on using rx pin as external interrupt to be able to
wake up from stop mode. If rx pin cannot be used as interrupt or user
does not need to wake up from stop from the CAN, an option is now
present. If en_deep_sleep_wake_up is set to false, setting the device to
sleep simply unblock stop mode. Otherwise the behavior is unchanged.
In case a non-gpio EXTI (>= 16) is pending, the isr_exti() used to clear
the flag and try to call a callback, which was out-of-bouds, thus
generating a hard fault.
This fixes it by masking the pending_isr variables with 0xFFFF.
The ram size is exposed as macro value and available for use in code.
For the stm32 it has a value in kilobytes suffixed with 'k'. This is
less than optimal for usage in arithmetic. This commit modifies the
value to bytes so that it can be used in preprocessor magic
This patch implements the basic support the last of the FLEXCOMM modes,
Serial Peripheral Interface, in a simple blocking mode with busy wait,
which is enough to test all the SPI functionality end-to-end.
Tested reading and writing registers on a SPI peripheral, and checked
with the oscilloscope that the frequencies were as expected.
Results from `tests/periph_spi`:
```
> init 0 0 2 -1 0
SPI_DEV(0) initialized: mode: 0, clk: 2, cs_port: -1, cs_pin: 0
> bench
1 - write 1000 times 1 byte: 16002 16009
2 - write 1000 times 2 byte: 18001 18008
3 - write 1000 times 100 byte: 802000 802007
4 - write 1000 times 1 byte to register: 24003 24010
5 - write 1000 times 2 byte to register: 26001 26008
6 - write 1000 times 100 byte to register: 810001 810008
7 - read 1000 times 2 byte: 23003 23009
8 - read 1000 times 100 byte: 807002 807009
9 - read 1000 times 2 byte from register: 32002 32009
10 - read 1000 times 100 byte from register: 816002 816009
11 - transfer 1000 times 2 byte: 23003 23009
12 - transfer 1000 times 100 byte: 807003 807010
13 - transfer 1000 times 2 byte to register: 32003 32009
14 - transfer 1000 times 100 byte to register:816002 816009
15 - acquire/release 1000 times: 7222 7228
-- - SUM: 5059250 5059351
```
The macro was moved from Kconfig to the periph_cpu.h which means that
the macro name needed to be updated to BOARD_HAS_ADC_PA06_CAP instead
of CONFIG_BOARD_HAS_ADC_PA06_CAP.
The ADC in the QN908x cpu offers multiple options for ADC conversion
using up to 8 external pins, one external reference pin and some
internal signals like a 1.2V reference, Vss, Vcc and an internal
temperature monitor.
This patch implements support for sampling ADC values from the ADC lines
defined in the board configuration. Some configurations are really
always present and don't require a board configuration, like the Vcc or
internal temperature monitor but to coexist with other board ADC line
options they are only set as part of the board configuration.
