If there is an Ethernet peripheral (periph_eth feature provided), we
can conclude that an Ethernet network interface can be provided.
Co-authored-by: mguetschow <mikolai.guetschow@tu-dresden.de>
The `ethernet` feature has not yet been used, so renaming it should not
cause any issue.
The goal is to eventually have a number of `netif_<type>` features that
would allow filtering boards by the time of connectivity the have.
This gets rid of a long list of boards with network interfaces and
instead let's boards (or MCUs with peripheral network interfaces)
provide the netif feature.
The apps that before used the long list are not depending on the
feature instead (in case of the default example, this is an
optional dependency).
Co-authored-by: mguetschow <mikolai.guetschow@tu-dresden.de>
Co-authored-by: mewen.berthelot <mewen.berthelot@orange.com>
This is a verbatim copy of the PWM config of `boards/nucleo-f746zg`.
However, those boards are almost identical. I successfully tested
the configuration via https://github.com/RIOT-OS/RIOT/pull/18392
1. Move buffer configuration from boards to cpu/stm32
2. Allow overwriting buffer configuration
- If the default configuration ever needs touching, this will be due to a
use case and should be done by the application rather than the board
3. Reduce default RX buffer size
- Now that handling of frames split up into multiple DMA descriptors works,
we can make use of this
Note: With the significantly smaller RX buffers the driver will now perform
much worse when receiving data at maximum throughput. But as long as frames
are small (which is to be expected for IoT or boarder gateway scenarios) the
performance should not be affected.
PA7 is the default MOSI pin, as it is required for compatibility with
Arduino(ish) shields. Sadly, it is also connected to the RMII_DV of
Ethernet PHY. This commit works around this by remapping the MOSI to PB5 when
the on-board Ethernet PHY is used.
openocd configuration file for `stm32f7` relies on probing to find out
FLASH_ADDR. On nucleo-f767zi board probing (`flash probe 0`) fails when
`srst` is asserted, but `srst` needs to be asserted to be able to flash
the `BOARD` when sleeping or after a hardfault.
To circumvent this in boards/common/stm32/dist/stm32f7.cfg we define a new
flash bank with the appropriate fash start address and specify that this is
the flash bank to be used as default configuration instead of the
default by setting FLASH_BANK=4
There is no hardware limitation for custom boards based on STM32 to uses
SPI bus with signals coming from different PORT and alternate functions.
This patch allow alternate's function definition per pin basis, thus enable
the support of SPI bus signals routed on differents PORT.
Signed-off-by: Yannick Gicquel <ygicquel@gmail.com>
cpu/$(CPU)/Makefile.features and cpu/$(CPU)/Makefile.dep are
automatically included
Part of moving CPU/CPU_MODEL definition to Makefile.features to have it
available before Makefile.include.
